US10985650B2 - Open-loop charge pump for increasing ripple frequency of output voltage - Google Patents

Open-loop charge pump for increasing ripple frequency of output voltage Download PDF

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US10985650B2
US10985650B2 US16/185,631 US201816185631A US10985650B2 US 10985650 B2 US10985650 B2 US 10985650B2 US 201816185631 A US201816185631 A US 201816185631A US 10985650 B2 US10985650 B2 US 10985650B2
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switch transistor
circuit
output
voltage
over
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US20190222119A1 (en
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Haijun Zhang
Shaojun GUAN
Ziqing Lu
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M1/0035—Control circuits allowing low power mode operation, e.g. in standby mode using burst mode control
    • H02M2001/0035—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to an open-loop charge pump.
  • a charge bump which is also referred to as a non-inductive direct current/direct current (DC/DC) converter, is a switch DC/DC converter in which a capacitor is used for power storage.
  • a boost charge pump circuit is often used as a power supply converter.
  • the charge-pump type converter with no power inductor has smaller electromagnetic interference (EMI), occupies a smaller area on the board, and has lower system cost.
  • the charge pumps are generally divided into voltage-stabilizing output type charge pumps and non-voltage-stabilizing output type charge pumps.
  • a close-loop control structure is usually adopted in which an output voltage of the charge pump circuit is sampled by using a dividing resistor to obtain a sampled voltage.
  • the sampled voltage is compared with a preset standard voltage, and the output voltage is stabilized to a preset value by using a switch transistor for controlling the power of the charge pump in an output control circuit of an error amplifier.
  • the switch transistor cannot be fully turned on under a gate voltage of the switch transistor, and the conduction impedance is not minimum, which affects the driving capability of the charge pump.
  • the error amplifier is included in the close-loop charge pump, which results in large power consumption of the close-loop charge pump and a large area of an integrated chip.
  • the open-loop charge pump In the open-loop charge pump, a gate voltage of the switch transistor can reach a power supply voltage and a ground voltage, and the conduction impedance can be minimum, while it is not required to perform loop control. Therefore, the open-loop charge pump is widely applied due to high efficiency and driving capability.
  • the open-loop charge pump generally has a current limiting function and an over-voltage protection function, which ensures effective and reliable operation of the open-loop charge pump.
  • the open-loop charge pump enters an over-voltage protection mode, and a load is powered by an output capacitor.
  • a ripple frequency of the output voltage is low and may fall in the audio frequency range (from 20 Hz to 20 KHz), which interferes an audio signal and generates audible noise.
  • An open-loop charge pump is provided in the present disclosure, which can increase a ripple frequency of an output voltage and remove music noise of the open-loop charge pump, thereby improving audio quality.
  • the open-loop charge pump provided in the present disclosure includes: a control circuit, a boost circuit, an output voltage detection circuit, an over-voltage protection circuit, a peak current limiting control circuit, and a clock circuit.
  • the control circuit includes a first input terminal and an output terminal.
  • the boost circuit includes a control terminal and a load terminal.
  • the load terminal of the boost circuit is connected to a load circuit including an output capacitor and an output load, and the load terminal of the boost circuit is connected to the first input terminal of the control circuit via the output voltage detection circuit and the over-voltage protection circuit.
  • the output voltage detection circuit is configured to output a detection voltage based on an output voltage at the load terminal
  • the over-voltage protection circuit is configured to output an over-voltage protection signal based on a reference voltage and the detection voltage.
  • the output terminal of the control circuit is connected to the control terminal of the boost circuit via the peak current limiting control circuit.
  • the control circuit drives the peak current limiting control circuit based on the over-voltage protection signal to control the boost circuit to be in a charging phase continuously or in a normal operation mode. In a case that the output voltage is higher than an upper threshold voltage, the boost circuit is continuously in the charging phase and does not supply power to the output load, and the output capacitor is discharged to supply power to the output load.
  • the boost circuit In a case that the output voltage is lower than a lower threshold voltage, the boost circuit is in the normal operation mode. In a time period of the normal operation mode, the boost circuit switches between a discharging phase and the charging phase based on a frequency of the clock circuit. When the boost circuit switches from the charging phase to the discharging phase, the peak current limiting control circuit decreases a peak current outputted from the boost circuit to increase a ripple frequency of the output voltage.
  • the peak current limiting control circuit includes: a first switch transistor, a second switch transistor, a third switch transistor and a single pulse generator.
  • a gate of the first switch transistor is connected to the control terminal of the boost circuit, a first electrode of the first switch transistor is configured to receive a power supply voltage, and a second electrode of the first switch transistor is connected to the gate of the first switch transistor.
  • a gate of the second switch transistor is connected to an output terminal of the single pulse generator, a first electrode of the second switch transistor is grounded, and a second electrode of the second switch transistor is connected to the second electrode of the first switch transistor.
  • a gate of the third switch transistor is connected to the output terminal of the single pulse generator via a phase inverter, a first electrode of the third switch transistor is grounded, and a second electrode of the third switch transistor is connected to the second electrode of the first switch transistor via a current source.
  • An input terminal of the phase inverter is connected to the output terminal of the single pulse generator, and an output terminal of the phase inverter is connected to the gate of the third switch transistor.
  • An input terminal of the single pulse generator is connected to the output terminal of the control circuit.
  • the first switch transistor is a P-channel Metal Oxide Semiconductor (PMOS) transistor
  • both the second switch transistor and the third switch transistor are N-channel Metal Oxide Semiconductor (NMOS) transistors.
  • PMOS Metal Oxide Semiconductor
  • NMOS N-channel Metal Oxide Semiconductor
  • the boost circuit includes a fourth switch transistor and a function circuit.
  • a gate of the fourth switch transistor is the control terminal of the boost circuit, a first electrode of the fourth switch transistor is configured to receive the power supply voltage, and a second electrode of the fourth switch transistor is connected to the load circuit via the function circuit.
  • the fourth switch transistor and the first switch transistor form a current mirror to limit an output current of the second electrode of the fourth switch transistor, so as to decrease the peak current.
  • the fourth switch transistor is a PMOS transistor.
  • the over-voltage protection circuit outputs the over-voltage protection signal having a high level in a case that the output voltage is higher than the upper threshold voltage, and outputs the over-voltage protection signal having a low level in a case that the output voltage is lower than the lower threshold voltage.
  • the control circuit controls, based on the over-voltage protection signal, the single pulse generator to output a positive pulse signal.
  • the positive pulse signal is used to control the second switch transistor to be turned on, and the positive pulse signal is converted to a negative pulse signal via the phase inverter.
  • the negative pulse signal is used to control the third switch transistor to be turned off, so as to control the fourth switch transistor to be in the charging phase.
  • the control circuit controls, based on the over-voltage protection signal, the single pulse generator to output a negative pulse signal.
  • the negative pulse signal is used to control the second switch transistor to be turned off, and the negative pulse signal is converted to a positive pulse signal through via the phase inverter.
  • the positive pulse signal is used to control the third switch transistor to be turned on such that the current source provides a current-limiting current for the current mirror, so as to decrease the peak current.
  • the single pulse generator is configured to output a pulse signal having a signal width of 0.5 ⁇ s.
  • the peak current limiting control circuit is arranged between the control circuit and the boost circuit.
  • the control circuit drives the peak current limiting control circuit based on the over-voltage protection signal to control the boost circuit to be in the charging phase continuously or in the normal operation mode.
  • the boost circuit In a case that the output voltage is higher than the upper threshold voltage, the boost circuit is continuously in the charging phase and does not supply power to the output load, and the output capacitor is discharged to supply power to the output load.
  • the boost circuit is in the normal operation mode.
  • the boost circuit switches between the discharging phase and the charging phase based on the frequency of the clock circuit.
  • the peak current limiting control circuit decreases the peak current outputted from the boost circuit to increase the ripple frequency of the output voltage. In this way, the music noise, which is caused by the ripple frequency of the output voltage of the charge pump being in an audio frequency range, can be avoided, thereby improving the audio quality.
  • FIG. 1 is a schematic circuit diagram of an open-loop charge pump
  • FIG. 2 is a timing diagram illustrating a voltage of the open-loop charge pump shown in FIG. 1 ;
  • FIG. 3 is a schematic circuit diagram of an open-loop charge pump for increasing a ripple frequency of an output voltage according to an embodiment of the present disclosure
  • FIG. 4 is a schematic circuit diagram of a peak current limiting control circuit in the open-loop charge pump shown in FIG. 3 ;
  • FIG. 5 is a schematic diagram showing waveforms of input and output signals of a single pulse generator.
  • FIG. 6 is a timing diagram illustrating comparison between ripple frequencies of output voltages of the open-loop charge pumps shown in FIG. 1 and FIG. 4 .
  • FIG. 1 is a schematic circuit diagram of an open-loop charge pump
  • FIG. 2 is a timing diagram illustrating a voltage of the open-loop charge pump shown in FIG. 1 .
  • the open-loop charge pump includes: an output voltage detection circuit 14 , an over-voltage protection circuit 13 , a control circuit 12 , a clock circuit 16 , a boost circuit 11 , an over-current detection circuit 17 and a reference circuit 15 .
  • the boost circuit 11 provides an output voltage VOUT to a load circuit 10 .
  • the output voltage detection circuit 14 generates a detection voltage Vovp for the over-voltage protection circuit 13 by dividing the output voltage with resistors.
  • the over-voltage protection circuit 13 compares a reference voltage Vref with the detection voltage Vovp, and then generates an over-voltage protection signal OVP.
  • the over-voltage protection signal OVP is inputted to the control circuit 12 .
  • the control circuit 12 determines whether the boost circuit 11 is in a normal operation mode or in an over-voltage protection mode based on the over-voltage protection signal OVP.
  • the clock circuit 16 generates a switch clock signal OSC for the control circuit 12 and the boost circuit 11 .
  • the control circuit 12 Under a sequence condition corresponding to the clock signal OSC, the control circuit 12 generates a boost control signal Vcon based on the over-voltage protection signal OVP.
  • the boost control signal Vcon is used to control a switch transistor in the boost circuit 11 to be turned on or turned off, so as to charge or discharge flying capacitors CF 1 and CF 2 in the open-loop charge pump and generate the output voltage VOUT.
  • the over-voltage protection circuit 13 and the output voltage detection circuit 14 are required to detect the output voltage VOUT.
  • the over-voltage protection circuit 13 controls the open-loop charge pump to enter the over-voltage protection mode and generates the over-voltage protection signal OVP having a high level.
  • the over-voltage protection signal OVP is inputted to the control circuit 12 such that the control circuit 12 generates the boost control signal Vcon.
  • the switch transistor in the boost circuit 11 is in a charging phase under control of the boost control signal Vcon, and does not supply power to an output load Rout.
  • the output load Rout is powered by an output capacitor Cout, and the output voltage VOUT of the boost circuit 11 is gradually decreased.
  • the over-voltage protection signal OVP changes to a low level, and the open-loop charge pump operates normally, and the output voltage VOUT is increased.
  • the open-loop charge pump shown in FIG. 1 has the following disadvantages.
  • the switch transistor in the boost circuit 11 is in the charging phase or is turned off, and the output load Rout is powered by the output capacitor Cout.
  • a large transient peak current IPEAK of the switch transistor which is generally up to 2 A, completely flows to the output capacitor Cout, the output voltage VOUT is increased, and the highest voltage of the output voltage VOUT is increased, and thus the ripple amplitude of the output voltage VOUT is increased.
  • the over-voltage protection circuit 13 outputs the over-voltage protection signal OVP to control the open-loop charge pump to be in the over-voltage protection mode.
  • OVP over-voltage protection signal
  • the output voltage VOUT is gradually decreased from a peak voltage, which results in the decreased ripple frequency of the output voltage, music noise in the audio frequency range, and the poor audio quality.
  • a peak current liming control module is added to the open-loop charge pump shown in FIG. 1 , to solve the above problem.
  • FIG. 3 is a schematic circuit diagram of an open-loop charge pump for increasing a ripple frequency of an output voltage according to an embodiment of the present disclosure.
  • the open-loop charge pump shown in FIG. 3 includes a control circuit 12 and a boost circuit 11 .
  • the control circuit 12 includes a first input terminal and an output terminal.
  • the boost circuit 11 includes a control terminal and a load terminal.
  • the load terminal of the boost circuit 11 is connected to a load circuit 10 .
  • the load circuit 10 includes an output capacitor Cout and an output load Rout.
  • the load terminal of the boost circuit 11 is connected to the first input terminal of the control circuit 12 via an output voltage detection circuit 14 and an over-voltage protection circuit 13 .
  • the output voltage detection circuit 14 is configured to output a detection voltage Vovp based on an output voltage VOUT at the load terminal.
  • the over-voltage protection circuit 13 is configured to output an over-voltage protection signal OVP based on a reference voltage Vref and the detection voltage Vovp.
  • the output terminal of the control circuit 12 is connected to the control terminal of the boost circuit 11 via a peak current limiting control circuit 18 .
  • the control circuit 12 drives the peak current limiting control circuit 18 based on the over-voltage protection signal OVP to control the boost circuit 11 to be in a charging phase continuously or in a normal operation mode.
  • the boost circuit 11 In a case that the output voltage VOUT is higher than an upper threshold voltage V OPVIN , the boost circuit 11 is in the charging phase and does not supply power to the output load Rout, and the output capacitor Cout is discharged to supply power to the output load Rout. In a case that the output voltage VOUT is lower than a lower threshold voltage V OVPOUT , the boost circuit 11 is in the normal operation mode. In a time period of the normal operation mode, the boost circuit 11 switches between a discharging phase and the charging phase based on a frequency of a clock circuit. When the boost circuit 11 switches from the charging phase to the discharging phase, the peak current limiting control circuit 18 is used to decrease a peak current outputted from the boost circuit 11 to increase a ripple frequency of the output voltage VOUT.
  • the boost circuit 11 further includes an over-current detection terminal
  • the control circuit 12 further includes a second input terminal.
  • the over-current detection terminal is connected to the second input terminal via an over-current detection circuit 17 .
  • the over-current detection circuit 17 is used to detect a current of the boost circuit 11 , generate a current detection signal OCP based on a current detection result, and transmit the current detection signal OCP to the control circuit 12 .
  • the control circuit 12 further includes a third input terminal.
  • the third input terminal is connected to a clock circuit 16 .
  • the clock circuit 16 generates a switch clock signal OSC for the control circuit 12 and the boost circuit 11 .
  • the control circuit 12 further includes a fourth input terminal.
  • the fourth input terminal is connected to a reference circuit 15 .
  • the reference circuit 15 is used to provide the reference voltage Vref for the over-voltage protection circuit 13 .
  • the peak current limiting control circuit 18 is added to the open-loop charge pump shown in FIG. 1 , which solves the problem of the poor audio quality caused by the extremely low ripple frequency of the output voltage VOUT.
  • the generated over-voltage protection signal OVP is a high level.
  • the over-voltage protection signal OVP is inputted to the control circuit 12 and the peak current limiting control circuit 18 , and the switch transistor in the boost circuit 11 is in the charging phase under control of a boost control signal Vcon and does not supply power to the output load Rout.
  • the output load Rout is powered by the output capacitor Cout, and the output voltage VOUT is gradually decreased.
  • the over-voltage protection signal OVP changes from the high level to a low level, and the peak current limiting control circuit 18 generates a single pulse signal to perform current limiting control on the switch transistor in the boost circuit 11 , such that a current-limiting current Ilimit flows through the switch transistor in the open-loop charge pump.
  • the current-limiting current Ilimit completely flows to the output capacitor Cout. In this way, the output voltage VOUT is increased in a smaller amplitude as compared with the case shown in FIG. 1 , thereby increasing the ripple frequency of the output voltage VOUT.
  • FIG. 4 is a schematic circuit diagram of a peak current limiting control circuit in the open-loop charge pump shown in FIG. 3 .
  • the peak current limiting control circuit 18 includes: a first switch transistor MPlim, a second switch transistor MN 0 , a third switch transistor MN 1 , and a single pulse generator 181 .
  • the single pulse generator 181 is configured to output a pulse signal having a signal width of 0.5 ⁇ s. It should be noted that the signal width may be adjusted according to requirements, which is not limited to 0.5 ⁇ s.
  • a gate of the first switch transistor MPlim is connected to the control terminal of the boost circuit 11 , a first electrode of the first switch transistor MPlim is configured to receive a power supply voltage VBAT, and a second electrode of the first switch transistor MPlim is connected to the gate of the first switch transistor MPlim.
  • a gate of the second switch transistor MN 0 is connected to an output terminal of the single pulse generator 181 , a first electrode of the second switch transistor MN 0 is grounded, and a second electrode of the second switch transistor MN 0 is connected to the second electrode of the first switch transistor MPlim.
  • a gate of the third switch transistor MN 1 is connected to the output terminal of the single pulse generator 181 via a phase inverter 183 , a first electrode of the third switch transistor MN 1 is grounded, and a second electrode of the third switch transistor MN 1 is connected to the second electrode of the first switch transistor MPlim via a current source 182 .
  • An input terminal of the phase inverter 183 is connected to the output terminal of the single pulse generator 181 , and an output terminal of the phase inverter 183 is connected to the gate of the third switch transistor MN 1 . That is, a single pulse signal OVP_ILN inputted to the third switch transistor MN 1 and a single pulse signal OVP_IL inputted to the second switch transistor MN 0 have the same amplitude and opposite phases.
  • An input terminal of the single pulse generator 181 is connected to the output terminal of the control circuit 12 .
  • the first switch transistor MPlim is a PMOS transistor
  • both the second switch transistor MN 0 and the third switch transistor MN 1 are NMOS transistors.
  • the boost circuit 11 includes a fourth switch transistor MP 0 and a function circuit 111 .
  • a gate of the fourth switch transistor MP 0 is the control terminal of the boost circuit 11
  • a first electrode of the fourth switch transistor MP 0 is configured to receive the power supply voltage VBAT
  • a second electrode of the fourth switch transistor MP 0 is connected to the load circuit 10 via the function circuit 111 .
  • the boost circuit 11 may be implemented by an existing boost circuit, which is not described in detail herein.
  • the fourth switch transistor MP 0 and the first switch transistor MPlim form a current mirror to limit an output current Ilimit of the second electrode of the fourth switch transistor MP 0 , so as to decrease the peak current.
  • the fourth switch transistor MP 0 is a PMOS transistor.
  • the over-voltage protection circuit 13 outputs the over-voltage protection signal OVP having a high level in a case that the output voltage VOUT is higher than the upper threshold voltage V OVPIN , and outputs the over-voltage protection signal OVP having a low level in a case that the output voltage VOUT is lower than the lower threshold voltage V OVPOUT .
  • the control circuit 12 controls, based on the over-voltage protection signal OVP, the single pulse generator 181 to output a positive pulse signal.
  • the positive pulse signal is used to control the second switch transistor MN 0 to be turned on, and the positive pulse signal is converted to a negative pulse signal via the phase inverter 183 .
  • the negative pulse signal is used to control the third switch transistor MN 1 to be turned off, so as to control the fourth switch transistor MP 0 to be in the charging phase.
  • the control circuit 12 controls the single pulse generator 181 to generate a set pulse signal by using a control signal OVP_CTRL.
  • the control circuit 12 controls, based on the over-voltage protection signal OVP, the single pulse generator 181 to output a negative pulse signal.
  • the negative pulse signal is used to control the second switch transistor MN 0 to be turned off, and the negative pulse signal is converted to a positive pulse signal via the phase inverter 183 .
  • the positive pulse signal is used to control the third switch transistor MN 1 to be turned on such that the current source 182 provides a current-limiting current for the current mirror, so as to decrease the peak current.
  • the over-voltage protection circuit 13 compares the detection voltage Vovp outputted by the output voltage detection circuit 14 with the reference voltage Vref. When the output voltage VOUT exceeds the upper threshold voltage V OVPIN , the generated over-voltage protection signal OVP is a high level.
  • the over-voltage protection signal OVP is imputed to the control circuit 12 and the single pulse generator 181 in the peak current limiting control circuit 18 , and a signal OVP_IL and an inversion signal OVP_ILN of the signal OVP_IL are generated, which are shown in FIG. 5 .
  • FIG. 5 is a schematic diagram showing waveforms of input and output signals of a single pulse generator.
  • the signal OVP_IL and the signal OVP_ILN are respectively used to control the second switch transistor MN 0 and the third switch transistor MN 1 .
  • the over-voltage protection signal OVP is a high level.
  • the signal OVP_IL is a high level
  • the signal OVP_ILN is a low level
  • the second switch transistor MN 0 is turned on.
  • the switch transistor in the boost circuit 11 is in a charging phase under control of the boost control signal Vcon, and does not supply power to the output load Rout. In this case, a load current is provided by the output capacitor Cout, and the output voltage VOUT is gradually decreased.
  • the over-voltage protection signal changes to a low level, and a negative pulse signal OVP_IL and a positive pulse signal OVP_ILN having signal widths of ⁇ t are generated by the single pulse generator 181 .
  • the second switch transistor MN 0 is turned off, the third switch transistor MN 1 is turned on, and a current-limiting current Ilim_ref flows to the current mirror formed by the first switch transistor MPlim and the fourth switch transistor MP 0 .
  • a current-limiting current limit flows from the fourth switch transistor MP 0 after the current-limiting current Ilim_ref is mirrored by K times, which decreases a peak amplitude of the output voltage VOUT compared with the case shown in FIG. 1 that the peak current I PEAK flows from the open-loop charge pump.
  • ⁇ t is set as 0.5 ⁇ s
  • a capacitance Cout of the output capacitor Cout is set as 5 ⁇ F.
  • the peak current I PEAK which is up to 2 A, flows from the switch transistor in the boost circuit 11 to the output capacitor Cout.
  • the frequency is in the audio frequency range (from 20 Hz to 20 KHz), which results in the music noise and the poor audio quality, affecting the hearing effect.
  • the frequency is out of the audio frequency range (from 20 Hz to 20 KHz), which does not affect the audio quality and the hearing effect.
  • FIG. 6 is a timing diagram illustrating comparison between ripple frequencies of output voltages of the open-loop charge pumps shown in FIG. 1 and FIG. 4 .
  • a timing diagram of a voltage signal of the open-loop charge pump shown in FIG. 1 is shown in the upper half of FIG. 6
  • a timing diagram of a voltage signal of the open-loop charge pump shown in FIG. 4 is shown in the lower half of FIG. 6 .
  • the ripple frequency may be further increased, as long as a lower current-limiting current Ilimit is set.
  • the ripple frequency is increased to a frequency being out of the audio frequency range, thereby improving the audio quality and the hearing effect.

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US11362528B2 (en) 2019-06-20 2022-06-14 Microsoft Technology Licensing, Llc Mitigation of audible output in a charging circuit
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