US10057516B2 - Image sensor and image capture device supporting rolling shutter mechanism and global shutter mechanism - Google Patents

Image sensor and image capture device supporting rolling shutter mechanism and global shutter mechanism Download PDF

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US10057516B2
US10057516B2 US15/152,322 US201615152322A US10057516B2 US 10057516 B2 US10057516 B2 US 10057516B2 US 201615152322 A US201615152322 A US 201615152322A US 10057516 B2 US10057516 B2 US 10057516B2
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image
voltage
array
analog
image data
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US20170195593A1 (en
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Mei-Chao Yeh
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Pixart Imaging Inc
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Pixart Imaging Inc
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    • H04N5/3532—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/531—Control of the integration time by controlling rolling shutters in CMOS SSIS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/73—Circuitry for compensating brightness variation in the scene by influencing the exposure time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H04N5/2353—
    • H04N5/3745—

Definitions

  • the instant disclosure relates to an image sensor; in particular, to an image sensor that can support both the rolling shutter mechanism and the global shutter mechanism, and relates to an image capture device using the same.
  • the image sensors can be generally classified into two types. One is the complementary metal-oxide-semiconductor (CMOS) image sensor, and the other one is the charge-coupled device (CCD) image sensor.
  • CMOS complementary metal-oxide-semiconductor
  • CCD charge-coupled device
  • the image sensor comprises a plurality of pixels arranged in a matrix and a plurality of comparators.
  • the pixels in the same column are connected to the same comparator.
  • Each pixel detects the brightness information and correspondingly generates image data.
  • Each pixel commonly comprises a light-sensing element and a reading circuit composed of at least one output transistor. Specifically, the light-sensing element detects the incident light, and correspondingly outputs and stores charges into the floating diffusion region.
  • the output transistor converts the charges stored in the floating diffusion region to image data and outputs the image data to the comparator.
  • the comparator outputs a corresponding comparison result image data to the image processing circuit according to the image data and a reference voltage to generate corresponding images.
  • the current image sensors can support two kinds of shutter mechanisms, which are the rolling shutter mechanism and the global shutter mechanism.
  • shutter mechanisms which are the rolling shutter mechanism and the global shutter mechanism.
  • the pixels are row by row exposed, and image data are generated and row by row provided to the comparator.
  • the image sensor is working under the global shutter mechanism, all pixels are simultaneously exposed, and row by row provide image data to the comparator.
  • Each comparator has different voltages when it is working under the rolling shutter mechanism and under the global shutter mechanism.
  • the current image sensors use two kinds of comparators and the corresponding image processing circuits to respectively process the image data under the rolling shutter mechanism and under the global shutter mechanism. If the same comparator and the corresponding image processing circuit are used to process the image data under the rolling shutter mechanism and under the global shutter mechanism, the various voltage requirements of the comparator will result in difficulty and complexity for designing the comparator.
  • using two kinds of comparators and the corresponding image processing circuits to respectively process the image data under the rolling shutter mechanism and under the global shutter mechanism has greater cost and requires a larger element area.
  • the instant disclosure provides an image sensor, and the image sensor is connected to an analog-to-digital converter array, wherein the analog-to-digital converter array comprises a plurality of comparators.
  • the image sensor comprises an image sensing array and a voltage supply array.
  • the image sensing array captures image data and comprises a plurality of pixels.
  • the image sensing array is set to support the rolling shutter mechanism or the global shutter mechanism.
  • the voltage supply array is connected to the analog-to-digital converter array, and comprises a plurality of voltage supply circuits to provide a dummy voltage. During an auto-zero period, the voltage supply array provides the dummy voltage to the analog-to-digital converter array, and the comparators execute an auto-zero function according to the dummy voltage.
  • the image sensing array outputs the image data signal to the analog-to-digital converter array after the comparators complete the auto-zero function.
  • the analog-to-digital converter array converts the image data signal to digital image data signal.
  • the instant disclosure further provides an image capture device, and the image capture device comprises an image capture sensor and an image sensor.
  • the image capture sensor comprises a plurality of comparators.
  • the image sensor is connected to the analog-to-digital converter array, and comprises an image sensing array and a voltage supply array.
  • the image sensing array captures image data, and comprises a plurality of pixels.
  • the image sensing array is set to support the rolling shutter mechanism and or the global shutter mechanism.
  • the voltage supply array is connected to the analog-to-digital converter array, and comprises a plurality of voltage supply circuits to provide a dummy voltage.
  • the voltage supply array provides the dummy voltage to the analog-to-digital converter array, and the comparators execute an auto-zero function according to the dummy voltage.
  • the image sensing array outputs the image data signal to the analog-to-digital converter array after the comparators complete the auto-zero function, and the analog-to-digital converter array converts the image data signal to a digital image data signal.
  • the voltage supply array can provide a stable dummy voltage to the comparator of the analog-to-digital converter array.
  • the image capture device uses the same analog-to-digital converter array and the same image processing circuit which can support both the rolling shutter mechanism and the global shutter mechanism, to generate images.
  • the image sensor and the image capture device using the same provided by the instant disclosure have a simplified circuit design which decreases the manufacturing difficulty and the manufacturing cost.
  • FIG. 1 shows a schematic diagram of an image capture device of one embodiment of the instant disclosure.
  • FIG. 2 shows a schematic diagram of an image sensor and an analog-to-digital converter array of one embodiment of the instant disclosure.
  • FIG. 3 shows a schematic diagram of a comparator of one embodiment of the instant disclosure.
  • FIG. 4 shows a waveform diagram indicating the operation of a conventional comparator under the rolling shutter mechanism and the global shutter mechanism.
  • FIG. 5 shows a waveform diagram indicating the operation of a comparator of one embodiment of the instant disclosure.
  • FIG. 1 shows a schematic diagram of an image capture device of one embodiment of the instant disclosure.
  • the image capture device 1 comprises an image sensor 10 , an analog-to-digital converter array 11 and an image processing circuit 12 .
  • the image sensor 10 is connected to the analog-to-digital converter array 11 .
  • the analog-to-digital converter array 11 is connected to the image processing circuit 12 .
  • the image capture device 1 can be applied to electric devices having an imaging function, such as a digital camera, digital camcorder, driving recorder, car navigation system, scanner, web camera, video phone and surveillance system. However, it is not limited herein.
  • the image sensor 10 can be, for example, the complementary metal-oxide-semiconductor (CMOS) image sensor and the charge-coupled device (CCD) image sensor.
  • CMOS complementary metal-oxide-semiconductor
  • CCD charge-coupled device
  • the image sensor 10 captures image data, and outputs the image data signal to the analog-to-digital converter array 11 .
  • the detailed configuration of the image sensor 10 is illustrated as follows.
  • the analog-to-digital converter array 11 comprises proper logics, circuits and/or coding, and is configured to convert the analog image data signal into the digital image data, wherein the digital image data are written in binary codes. After that, the analog-to-digital converter array 11 outputs the digital image data signal to the image processing circuit 12 .
  • the detailed configuration of the analog-to-digital converter array 11 is illustrated as follows.
  • the image processing circuit 12 comprises proper logics, circuits and/or coding, and is configured to obtain real images from the digital image data signal or to process the digital image data signal.
  • the image processing circuit 12 can implement the pixel luminance compensation and the pixel integrated process for the digital image data signal.
  • the image processing circuit 12 has a pixel compensation mechanism that can compensate the pixel luminance for the digital image data signal according to the surrounding illumination and the conversion gain of each pixel.
  • FIG. 2 shows a schematic diagram of an image sensor and an analog-to-digital converter array of one embodiment of the instant disclosure.
  • the image sensor 10 comprises an image sensing array and a voltage supply array.
  • the image sensing array comprises a plurality of pixels that forms a pixel array.
  • the voltage supply array comprises a plurality of voltage supply circuits 101 .
  • the analog-to-digital converter array 11 comprises a plurality of comparators 110 , a plurality of counters 111 , a plurality of first capacitors C 1 and a plurality of second capacitors C 2 .
  • the first capacitors C 1 and the second capacitors C 2 are respectively connected to the inversing input ends and the non-inversing input ends of the comparators 110 .
  • the output ends of the comparators 110 are respectively connected to the counters 111 .
  • the output ends of the counters 111 are respectively connected to the image processing circuit 12 .
  • the image sensing array has a configuration of the column analog-to-digital converter.
  • the pixels in the same column are connected to the same comparator 110 and form a plurality of column pixel matrixes 100 , wherein the column pixel matrixes 100 are arranged in parallel and form an image sensing array.
  • the amount of the comparators 110 corresponds to the column number of the image sensing array.
  • a voltage supply circuit 101 is connected to the column pixel matrix 100 and the comparator 110 , and thus the amount of the voltage supply circuits 101 also corresponds to the column number of the image sensing array. It should be noted that, for understanding easily, there is only one column pixel matrix 100 and one voltage supply circuit 101 shown in FIG. 2 .
  • the pixel number of the column pixel matrixes 100 and the amount of the voltage supply circuits 101 are not limited herein.
  • one voltage supply circuit 101 can be connected to a plurality of column pixel matrixes 100 and a plurality of comparators 101 .
  • the image sensing array captures image data.
  • the image sensing array can be set to support the rolling shutter mechanism or the global shutter mechanism.
  • the image sensing array is working under the rolling shutter mechanism, the pixels are exposed row by row, the image data signals PXO are generated, and the image data signals PXO are row by row provided to the analog-to-digital converter array 11 .
  • the image sensor is working under the global shutter mechanism, all pixels are exposed simultaneously, and the exposed pixels row by row provide the image data signals PXO to the analog-to-digital converter array 11 .
  • the pixel in this embodiment has a four-transistor (4T) configuration.
  • Each pixel comprises a light-sensing element PD, a floating diffusion region FD, a source follower SF, a row selection transistor RSL, a reset transistor RST and a transfer transistor TG
  • One end of the light-sensing element PD is connected to the transfer transistor TG, and the other end of the light-sensing element PD is grounded.
  • the transfer transistor TG is connected between the light-sensing element PD and the floating diffusion region FD.
  • the gate of the source follower SF is connected to the floating diffusion region FD, and the drain of the source follower SF is connected to a power supply to receive the supplied power from the power supply VDD.
  • the drain of the row selection transistor RSL is connected to source of the source follower SF, and the source of the row selection transistor RSL is connected to the comparator 110 .
  • the reset transistor RST is connected between the power supply VDD and the floating diffusion region FD.
  • the gate of the transfer transistor TG, the gate of the reset transistor RST and the gate of the row selection transistor RSL are respectively connected to a driving circuit (not shown in FIG. 2 ).
  • the light-sensing element PD detects the incident light and correspondingly generates charges.
  • the light-sensing element PD can be an electric element, such as a photo diode, a photo transistor, a photo-gate, a pinned photo diode or the combination thereof, which can convert the light to charges.
  • the floating diffusion region FD is composed of the parasitic capacitance between the light-sensing element PD and the source follower SF and/or the additional plug-in capacitance.
  • the floating diffusion region FD receives and stores charges generated by the light-sensing element PD.
  • the transfer transistor TG selectively transfers the charges generated by the light-sensing element PD to the floating diffusion region FD. Specifically, the transfer transistor TG is controlled by the transferring signal output by the driving circuit. When the driving circuit outputs the transferring signal at low level to cut off the transfer transistor TG, the charges generated by the light-sensing element PD cannot be transferred to the floating diffusion region FD. When the driving circuit outputs the transferring signal at high level, the transfer transistor TG transfers the charges generated by the light-sensing element PD to the floating diffusion region FD, wherein the charges are stored and accumulated.
  • the source follower SF When turned on, the source follower SF has a gate voltage at its gate according to the charges output by the floating diffusion region, and correspondingly generates the image data signal PXO.
  • the row selection transistor RSL receives the image data PXO signal, and selectively outputs the image data signal PXO to the comparator 110 according to the row selection signal RSEL output by the driving circuit.
  • the reset transistor RST selectively resets the floating diffusion region with the supplied voltage from the power supply VDD according to the reset signal output by the driving circuit. For example, when the reset signal is at low level, the reset transistor RST is cut off and thus the voltage of cathode of the light-sensing element PD drops. At this moment, the light-sensing element PD detects the incident light and correspondingly generates charges, and then the charges are stored in the floating diffusion region FD. When the reset signal is at low level, the reset transistor RST is turned on such that the voltage of the cathode of the light-sensing element PD is reset as the initial voltage (that is, the supplied voltage from the power supply VDD) to release and remove the charges left in the floating diffusion region. In other words, the floating diffusion region FD is reset.
  • the pixels have a four-transistor (4T) configuration, but it is not limited herein.
  • the pixels can have a three-transistor (3T) configuration or a five-transistor (5T) configuration. If the pixels have a 3T configuration, the pixels do not comprise the transfer transistor TG If the pixels have a 5T configuration, the pixels further comprise a global shutter transistor, in addition to the light-sensing element PD, the floating diffusion region FD, the source follower SF, the row selection transistor RSL, the reset transistor RST and the transfer transistor TG Those skilled in the art should be familiar with the working principles regarding to the pixels having a 3T configuration or a 5T configuration, so the information is not repeated herein.
  • the voltage supply circuit 101 comprises proper logics, circuits and/or coding, and is configured to provide a dummy voltage V dummy to the comparator 110 .
  • the dummy voltage V dummy is a stable fixed voltage.
  • the comparator 110 executes the auto-zero function according to the dummy voltage V dummy , to overcome the mismatch resulted from the processing differences of the transistors of the comparators 110 .
  • the voltage supply circuit 101 is a shading pixel.
  • the shading pixel has the same configuration as the configuration of the above mentioned pixel, such as the 4T configuration. Different from the above mentioned pixel, the light-sensing element PD of the shading pixel is not influenced by the incident light because of being shaded. Thus, the voltage of the floating diffusion region FD of the shading pixel is stable.
  • the shading pixel provides a stable dummy voltage V dummy to the comparator 110 according to the voltage of the floating diffusion region FD, and the comparator 110 executes the auto-zero function.
  • the configuration of the voltage supply circuit 101 is not limited in this embodiment. In other embodiments, the voltage supply circuit 101 can have a 3T configuration or a 5T configuration, or can be other circuits that can provide a stable voltage. However, for decreasing the manufacturing difficulty, the voltage supply circuit 101 is designed to have the same configuration as the configuration of the pixels in the image sensing array.
  • FIG. 3 shows a schematic diagram of a comparator of one embodiment of the instant disclosure.
  • the comparator 110 comprises a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a first switch transistor SW 1 , a second switch transistor SW 2 and a current source IS.
  • the first transistor M 1 and the second transistor M 2 are NMOS transistors
  • the third transistor M 3 and the fourth transistor M 4 are PMOS transistors.
  • the source of the first transistor M 1 is connected to the current source IS, and the drain of the first transistor M 1 is connected to the third transistor M 3 .
  • the source of the second transistor M 2 is connected to the current source IS, and the drain of the second transistor M 2 is connected to the fourth transistor M 4 .
  • the current source IS controls the current flowing through the first transistor M 1 and the second transistor M 2 .
  • the gate of the first transistor M 1 is connected to the first capacitor C 1 .
  • the gate of the second transistor M 2 is connected to the second capacitor C 2 .
  • the gate and drain of the fourth transistor M 4 are mutually connected, and the drain of the fourth transistor M 4 is further connected to the counter 111 .
  • first switch transistor SW 1 is electrically connected between the drain and gate of the first transistor M 1 .
  • the second switch transistor SW 2 is electrically connected between the drain and gate of the second transistor M 2 .
  • the first switch transistor SW 1 and the second switch transistor SW 2 are PMOS transistors, but it is not limited herein.
  • the first switch transistor SW 1 and the second switch transistor SW 2 can also be NMOS transistors. Those skilled in the art can determine and change the types of the first switch transistor SW 1 and the second switch transistor SW 2 according to the voltage requirements of the comparator 110 .
  • the comparator 110 receives the ramp voltage RDAC via gate of the first transistor M 1 and receives the image data signal PXO provided by the column pixel matrix 100 via the gate of the second transistor M 2 .
  • the comparator 110 outputs a comparison result to the counter 111 according to the ramp voltage RDAC and the image data signal PXO.
  • the above mentioned configuration of the comparator 110 is for illustrating but not for restricting the instant disclosure.
  • the comparator 111 can have different configurations.
  • FIG. 4 shows a waveform diagram indicating the operation of a conventional comparator under the rolling shutter mechanism and the global shutter mechanism.
  • the ramp voltage RDAC has a fixed waveform.
  • the comparator 110 can be set to support the rolling shutter mechanism or the global shutter mechanism. It should be noted that, in this embodiment, the image sensor 10 does not comprise the voltage supply array, or the voltage supply circuit 101 of the voltage supply array does not provide the dummy voltage V dummy to the comparator 110 .
  • the descriptions to illustrate the operation when the image sensing array is working under the rolling shutter mechanism are as follows.
  • the pixels in the image sensing array of the image sensor 10 are row by row exposed.
  • the comparator 110 executes the auto-zero function.
  • the floating diffusion region FD has not yet received charges because the transfer transistors TG of the pixels have not yet been turned on.
  • the voltages of the image data signal PXO outputted by the pixels equal to the reference voltage.
  • the row selection transistor RSL of the pixel receives the row selection signal RSEL at high level such that the pixels start to provide the image data signal PXO at high level to the corresponding comparator 110 .
  • the first switch transistor SW 1 and the second switch transistor SW 2 of the comparator 110 are turned on, so the comparator 110 calibrates and records the offset voltages V offset among the first transistor M 1 , the second transistor M 2 , the third transistor M 3 and the fourth transistor M 4 , and stores the offset voltages V offset in the first capacitor C 1 and the second capacitor C 2 to complete the auto-zero function.
  • the duration from the timing T 1 to the timing T 2 refers to the auto-zero period of the comparator 110 .
  • the voltage of the first terminal V dip of the comparator 110 is the difference between the supplied power provided by the power supply VDD and the working voltage V th _ p of the third transistor M 3 (that is, VDD-V th _ p ), and the voltage of the second terminal V din of the comparator 110 is the difference between the supplied power VDD and the working voltage V th _ p of the fourth transistor M 4 (that is, VDD-V th _ p ).
  • the comparator 110 enters into the first comparison period.
  • the offset voltage V offset is stored in the first capacitor C 1 , so the voltage of the first terminal V dip of the comparator 110 turns to be VDD-V th _ p +V offset .
  • the voltage of the first terminal V dip of the comparator 110 starts to drop with the decrease of the ramp voltage RDAC.
  • the counter 111 starts to count for calculating the time consumption for the voltage of the first terminal V dip of the comparator 110 dropping to be less than the voltage of the second terminal V din of the comparator 110 .
  • the transfer transistor TG has not yet been turned on to transfer charges to the floating diffusion region FD, so the voltage of the image data signal PXO is the reference voltage which is at high level.
  • the voltage of the second terminal V din of the comparator 110 maintains at VDD-V th _ p .
  • the counter 111 stops counting and outputs the counting value to the image processing circuit.
  • the counting value obtained by the counter 111 in the first comparison period corresponds to the offset voltage V offset .
  • the image processing circuit 12 converts the counting value to the gray level value of the image.
  • the image capture device 1 uses the counting value to represent the voltage of the image data signal, and then the image processing circuit 12 converts the time counting value to the gray level value.
  • the ramp voltage RDAC is a step signal.
  • the counting values generated by the counter 111 correspond to each step of the ramp voltage RDAC.
  • the counting value “1” corresponds to the first step of the step signal
  • the counting value “2” corresponds to the second step of the step signal.
  • the counting value can also correspond to one of the gray level values “0 ⁇ 255”. Accordingly, the image processing circuit 12 can directly determine the binary gray level value of the image according to the counting value output by the counter 111 .
  • first switch transistor SW 1 and the second switch transistor SW 2 are cut off once the comparator enters into the comparison mode (that is, in the first comparison period or in the second comparison period).
  • the comparator 110 enters into the second comparison period.
  • the ramp voltage RDAC returns to be at the initial logic level. That is, the voltage of the first terminal V dip of the comparator 110 turns back to VDD-V th _ p +V offset . After that, the ramp voltage RDAC starts to drop such that the voltage of the first terminal V dip of the comparator 110 varies again.
  • the counter 111 is reset and again starts to count. At this moment, the transfer transistors TG of the pixels in the first row in the image sensing array are turned on, such that the images captured by the pixels are transferred to the floating diffusion region FD.
  • the pixels respectively output the image data signals PXO at low level.
  • the image data signals PXO are coupled to the voltage of the second terminal V din of the comparator 110 , such that the voltage of the second terminal V din of the comparator 110 turns VDD-V th _ p ⁇
  • the counter 111 calculates the time consumption for the voltage of the first terminal V dip of the comparator 110 dropping to be less than the voltage of the second terminal V din of the comparator 110 , and outputs the counting value to the image processing circuit 12 .
  • the counting value obtained by the counter 111 in the second comparison period corresponds to the sum of the offset voltage and the real image, which is V offset +
  • the voltage of the current source IS is set to be less than the voltage of the voltage of the second terminal V din of the comparator 110 , because once the voltage of the second terminal V din of the comparator 110 is less than the voltage of the current source IS, the current source IS cannot normally provide current to the elements of the comparator 110 .
  • the comparator 110 ends the second comparison period.
  • the row selection signal RSEL turns to be at low level such that row selection transistor RSL is cut off.
  • the image processing circuit 12 calculates the difference between the gray level values corresponding to the counting values respectively obtained in the first comparison period and the second comparison period, and the gray level value of the real image
  • the following descriptions illustrate the operation of the comparator 110 under the global shutter mechanism.
  • the global shutter mechanism all pixels in the image sensing array of the image sensor 10 are simultaneously exposed, and the image sensing array row by row provides the image data signal PXO to the corresponding comparator 110 .
  • the voltage of the transistor in the comparator 110 is set to be at relatively high level.
  • the comparator 110 executes the auto-zero function.
  • the comparator 110 receives the image data signal PXO at low level because the pixels have captured images.
  • the comparator 110 calibrates and records the offset voltages V offset among the first transistor M 1 , the second transistor M 2 , the third transistor M 3 and the fourth transistor M 4 , and then stores the offset voltages V offset in the first capacitor C 1 and the second capacitor C 2 to complete the auto-zero function.
  • the voltage of the first terminal V dip of the comparator 110 is the difference between the supplied power VDD and the working voltage of the third transistor M 3 , which is VDD-V th _ p .
  • the voltage of the second terminal V din of the comparator 110 is the difference between the supplied power VDD and the working voltage of the fourth transistor M 4 , which is VDD-V th _ p .
  • the comparator 110 enters into the first comparison period.
  • the voltage of the first terminal V dip of the comparator 110 is VDD-V th _ p +V offset , and the voltage of the first terminal V dip of the comparator 110 drops with the increase of the ramp voltage RDAC.
  • the counter 111 starts to count for calculating the time consumption for the voltage of the first terminal V dip of the comparator 110 dropping to be less than the voltage of the second terminal V din of the comparator 110 .
  • the comparator 110 enters into the second comparison period.
  • the reset transistor RST of the pixel is turned on such that the floating diffusion region FD is reset.
  • the comparator 110 receives the image data signal PXO at high level, which is the reference voltage.
  • the voltage of the real image ⁇ V is coupled to the voltage of the second terminal V din of the comparator 110 , such that the voltage of the second terminal V din of the comparator 110 turns to be VDD-V th _ p +
  • the second capacitor C 2 of the analog-to-digital converter array 11 has stored the offset voltages V offset .
  • the comparator 110 receives the image data signal PXO at high level, the second switch transistor SW 2 will be incidentally turned on, which results in the loss of the charges in the second capacitor C 2 . Under this situation, the comparator 110 cannot complete the auto-zero function.
  • the comparator 110 cannot work in its working voltage range because of receiving the image data signal PXO at high level.
  • each element of the comparator 110 consumes its working voltage
  • the working voltage range of the comparator 110 is 0 ⁇ 3.3V.
  • the current source IS also consumes its working voltage, such as 0.5V, and the voltage of the second terminal V din of the comparator 110 cannot be less than the working voltage of the current source IS.
  • the voltage of the comparator 110 maintains at 2.8V and that the comparator 110 receives the image data signal PXO at high level, such as 0.6V, as a result the voltage of the comparator 110 will be over its working voltage range, and each element of the comparator 110 will not be able to work normally.
  • FIG. 5 shows a waveform diagram indicating the operation of a comparator of one embodiment of the instant disclosure.
  • the image sensor 10 in this embodiment further provides a dummy voltage V dummy to the image sensor 10 via the voltage supply array.
  • the comparator 110 enters into the auto-zero period to execute the auto-zero function. All pixels in the image sensing array of the image sensor 10 are simultaneously exposed. At this moment, the row selection signal RSEL maintains at low level such that the row selection transistor RSL is cut off and thus the image data signal PXO captured by the pixels will not be inputted to the comparator 110 .
  • the voltage supply circuit 101 of the voltage supply array starts to provide the dummy voltage V dummy at high level to the corresponding comparator 110 .
  • the comparator 110 completes the auto-zero function according to the dummy voltage V dummy at high level, and stores the offset voltages in the first capacitor C 1 and the second capacitor C 2 .
  • the voltage of the first terminal V dip of the comparator 110 and the voltage of the second terminal V din of the comparator 110 both equal to VDD-V th _ p .
  • the comparator 110 enters into the comparison mode.
  • the voltage supply array stops providing the dummy voltage V dummy .
  • the voltage of the first terminal V dip of the comparator 110 is VDD-V th _ p +V offset , and the voltage of the first terminal V dip of the comparator 110 drops with the decrease of the ramp voltage RDAC.
  • the row selection signal RSEL turns to be at high level to turn on the row selection transistor RSL.
  • the pixels start to input the image data signals PXO to the comparator 110 .
  • the voltage of the real image ⁇ V is coupled to the voltage of the second terminal V din of the comparator 110 , such that the voltage of the second terminal V din of the comparator 110 turns to be VDD-V th _ p ⁇
  • the voltage of the second terminal V din of the comparator 110 equals to the voltage of the second terminal V din of the comparator 110 during the second comparison period shown in the above embodiment, wherein the image sensing array is working under the rolling shutter mechanism.
  • the comparator 110 compares the voltage of its first terminal V dip and the voltage of its second terminal V din , and outputs a first comparison result to the counter 111 .
  • the counter 111 calculates the time consumption for the voltage of the first terminal V dip of the comparator 110 dropping to be less than the voltage of the second terminal V din of the comparator 110 according to the first comparison result, and outputs the corresponding counting value to the image processing circuit 12 .
  • the counting value obtained by the counter 111 corresponds to the sum of the offset voltage V offset and the absolute value of the real image, which is V offset +
  • the comparator 110 enters into the second comparison period, and the voltage of the first terminal V dip of the comparator 110 returns to be VDD-V th _ p +V offset .
  • the reset transistor RST of the pixel is turned on such that the floating diffusion region SD is reset.
  • the comparator 110 receives the image data signal PXO at high level, which is the reference voltage.
  • the voltage of the second terminal V din of the comparator 110 returns to be VDD-V th _ p that equals to the voltage of the second terminal V din of the comparator 110 during the first comparison period in the above embodiment, wherein the image sensing array is working under the rolling shutter mechanism.
  • the voltages of the second terminal V din of the comparator 110 are the same as the comparator 110 operating under the rolling shutter mechanism and the global shutter mechanism.
  • the image capture device 1 can use the same analog-to-digital converter array 11 and the image processing circuit 12 to process the image data signals PXO.
  • the comparator 110 compares the voltage of its first terminal V dip and the voltage of its second terminal V din , and outputs a second comparison result to the counter 111 .
  • the counter 111 calculates the time consumption for the voltage of the first terminal V dip of the comparator 110 dropping to be less than the voltage of the second terminal V din of the comparator 110 according to the second comparison result, and outputs the corresponding counting value to the image processing circuit 12 .
  • the counting value obtained by the counter 111 corresponds to the offset voltage V offset .
  • the comparator 110 ends the second comparison period.
  • the row selection signal RSEL turns to be at low level such that the row selection transistor RSL is cut off.
  • the image processing circuit 12 calculates the difference between the gray level values corresponding to the counting values obtained in the first comparison period and the second comparison period, to obtain the gray level value of the real image
  • the comparator 110 can still work normally such that the image processing circuit 12 can obtain the real image
  • the voltage supply circuit 101 also can provide the dummy voltage V dummy at high level to the corresponding comparator 110 such that the comparator 110 can complete the auto-zero function; however, it is not limited herein.
  • the corresponding transfer transistors TG of the pixels will be turned on after the comparator 110 has completed the auto-zero function.
  • the pixels still provide the voltage signal at high level to the comparator 110 for executing the auto-zero function.
  • the voltage supply circuit 101 does not need to provide the dummy voltage V dummy to the comparator 110 .
  • the voltage supply array can provide a stable dummy voltage to the comparator of the analog-to-digital converter array.
  • the image capture device uses the same analog-to-digital converter array and the same image processing circuit which can support both the rolling shutter mechanism and the global shutter mechanism, to generate images.
  • the image sensor and the image capture device using the same provided by the instant disclosure have a simplified circuit design which decreases the manufacturing difficulty and the manufacturing cost.
  • the image data captured by the image sensor are converted to the binary image data signals via the counter of the analog-to-digital converter array.
  • the image processing circuit executes the binary data calculation, so there will be no time consumption for additionally executing the format conversion.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
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