UA89153U - Pulse counter - Google Patents

Abstract

A pulse counter comprises n-digit register, whose each digit comprises a trigger and an AND element, an analysis unit comprising n-1 AND elements, a disposition unit comprising n-1 AND elements having inverters at inputs, a control unit comprising n-1 AND element united by AND element, a reset unit comprising n-1 OR and AND elements, to whose first input a clock bus is connected. The outputs of n-1 AND elements of the analysis unit are connected to the first inputs of n-1 AND elements of the register unit, whose second inputs and the first input of AND element of the reset unit are connected to the input bus of synchro clock pulses. Direct inputs of n-1 triggers are connected to the third inputs of AND elements of the register unit, whose fourth inputs are connected to outputs of n-2 AND elements of disposition units, the output of n-1 AND element of the disposition unit is connected to the third unit of AND element of the reset unit. The outputs of AND elements of register unit are connected to one condition set unit, trigger inverse outputs are connected to the first and second inputs of n-1 AND elements of the analysis unit. The trigger direct outputs are connected to the first and second inputs of n-1 AND elements of the control unit. The direct output of n-th trigger is connected to the second input of AND element of the reset unit, the outputs of AND elements of the control unit are connected to the inputs of OR element. Moreover, auxiliary inverters are introduced, forming a disposition unit and supplementary connections of reset unit OR elements.