UA31505U - Multi-channel scaling device - Google Patents

Abstract

A multi-channel scaling unit comprises a frequency divider, inverting input of which is connected to clock pulses input, control inputs – to input of control bus, the first storage device, the first inputs group of which – to the frequency divider output, the second inputs group- to control bus input, outputs – to the fist group of outputs. Moreover, a parallel-to-series code converter is introduced, time reading inputs are connected to outputs of the frequency divider, informational inputs – to input of the control bus, a communication line with the first input being connected to clock pulses input, the second - to parallel-to-series code converter output, a timer. Complementing input of the timer is connected clock pulses output of the communication line, start input – to output of series code of communication line. And also it is introduced a series-to- parallel code converter with information input being connected to output of series input of the communication line, inputs of time reading – to timer outputs, the second storage unit, the first input group of which is connected to timer outputs, the second input group- to output of series –to-parallel code converter, outputs – to the second outputs group.

Description

Description of the invention

The useful model belongs to pulse technology and can be used in devices for processing discrete 2 information, in measuring equipment, in synchronizers.

A known frequency division circuit with a variable division ratio, which contains a counter, equivalence circuits, circuit I, a memory device, a control panel, a generator | Japanese application Mo51-37862 dated 18.10.1976, cl. NOZK21/36, national classification - 98(5) P.321.

The disadvantage of such a device is limited functionality due to the presence of only one output. 70 Known multi-channel timer, which contains a discrete delay line, a memory device, a control counter, M-3 logical elements 1, Mtriggers, a logical element OR | patent of Ukraine for an invention

Mo39381A.

The disadvantage of this device is limited functionality due to the need to have a trigger pulse at the input to form the output signals, as well as the need for a large number of communication lines to transmit 75 part of the output signals over a distance.

The closest in technical essence to a useful model containing a pulse counter, the counting input of which is connected to the input bus, matching elements, the first inputs of which are connected to the outputs of the program block, and the outputs are connected to the control inputs of the counting pulses, a pulse distributor, the input of which connected to the output of the pulse counter and the second inputs of the matching elements, the first group of outputs - to the control inputs of the software block, and the second group of outputs - to the output buses (patent of Ukraine for the invention Mo583814АЙ.

The disadvantage of the known device is limited functionality, which does not provide the required number of outputs at a distance with a limited number of communication lines.

The useful model is based on the task of creating a device with enhanced functionality by reducing the required number of communication lines. 29 The problem is solved by the fact that the device, which contains a frequency divider, the counting input of which 2 is connected to the input of clock pulses, and the control inputs - to the input of the control bus and the first memory device, the first group of inputs of which is connected to the outputs of the frequency divider, the second group of inputs is to the input of the control bus, and the outputs are to the first group of outputs, a parallel-to-serial converter is additionally introduced, the inputs of which are connected to the outputs of the frequency divider, and the input information is to the input of the control bus, a communication line, the first the input of which is connected to the input of the clock pulses, and the second - to the output of the parallel code to serial converter, the timer, the counter input of which is connected to the output of the clock pulses of the communication line, and the start input - to the output of the serial code of the communication line, which, serial code to parallel converter, the information input of which is connected to the output of the serial code "- the communication line, and the inputs of the time reference - to the timer moves, the second memory device, the first group of inputs of which is connected to the timer outputs, the second group of inputs - to the outputs of the serial code converter in so parallel, and the outputs - to the second group of outputs.

The causal relationship between the set of features of the invention and the technical result is as follows.

Additional input of a parallel-to-serial converter, a timer, a serial-to-parallel converter, a second storage device, a communication line for transmitting clock pulses and 70 serial codes provides an opportunity to expand the functionality of a multi-channel counting device, namely: get the required number of outputs at a distance with a limited number of communication lines. with" The figure shows the structural diagram of the proposed device.

The multi-channel counting device contains a frequency divider 1, the first storage device 2, a parallel-to-serial converter 3, a communication line 4, a timer 5, a serial-to-parallel converter 6, a second storage device 7. se Counting input of the frequency divider 1 is connected to the input of clock pulses, the control inputs are to the control bus input, and the outputs are to the timing inputs of the parallel-to-serial code converter and to the first group of inputs of the memory device 2, the second group of inputs of which is connected to the control bus input, and about exits - to the first group of exits. The information inputs of the parallel-to-serial code converter 20 are connected to the input of the control bus, and the output is to the second input of the communication line 4, the first input of which is connected to the input of the clock pulses. The output of the clock pulses of the communication line is connected to the counting input of the timer "sl 5, and the output of the serial code - to the input of the start of the timer 5 and the information input of the converter 6 of the serial code to parallel.

The outputs of the timer 5 are connected to the time counting inputs of the serial-to-parallel code converter 6 and to 29 of the first group of inputs of the second storage device 7. The second group of inputs of the second storage device 7 is connected to the outputs of the serial-to-parallel code converter 6, and the outputs are to the second group of exits.

In the initial state, clock pulses are received at the input of the clock pulses of the device, and at the input of the control bus - a parallel code that determines the division coefficient of the frequency divider 1, the phase and duration of 60 pulses received at the first and second group of outputs.

The claimed device works as follows.

Frequency divider 1 is activated at the arrival of each clock pulse. At the same time, the code of the time interval that has passed since the start of work changes on its outputs.

When the time interval code reaches the final value, the frequency divider 1 transitions to the output 62 state. At the same time, the time interval code takes an initial value, for example, zero.

In the initial state (for example, the code at the output of the divider takes a zero value). The final value of the time slot code is determined by the code applied to the frequency divider control inputs 1. The frequency divider cycle is repeated again.

During the operation cycle of the frequency divider 1, the storage device 1 forms pulses at the outputs at given combinations of the time interval code and the control code at its inputs.

The parallel-to-serial converter starts working after the time interval code received at its timing input takes the initial value. At the same time, a sequential code consisting of start and information bits is formed. The start bit marks the beginning of the code. 70 The composition of the information bits corresponds to the composition of the parallel code received at the information inputs of the converter From parallel code to serial.

With the help of a communication line, 4 clock pulses and a serial code are transmitted over a distance on two channels.

For example, moving electrical contacts between a rotating platform and a stationary platform can be used as a communication line.

Serial code and clock pulses from the outputs of the communication line are sent to the inputs of timer 5. Timer 5 starts working when a start bit in the serial code is received at its start input. At the same time, the time interval code at the outputs of timer 5 takes the initial value.

Timer 5 is triggered by each clock pulse received at its counter input. At the same time, the time interval code that has passed since the start of timer 5 changes. When the time interval code reaches the specified value, the timer stops. The timer 5 cycle starts again when the next sequence code is received.

The serial code to parallel converter 6 starts working after starting the timer 5. The work lasts for a time equal to the duration of the serial code. After that, the value of the parallel code corresponding to the composition of the serial code is fixed at the outputs of the serial code to parallel converter 6. This value does not change until the end of the timer 5 cycle.

The second storage device 7 forms pulses at the outputs at given combinations of the time interval code - coming from the timer 5 and the control code coming from the serial-to-parallel code converter b.

A new operating cycle begins when frequency divider 1 goes to the initial state. The duration and phase of the pulses at the outputs of the device will be determined by the signals that will be established at the input of the control spike at that moment. o iv)

Claims (1)

The formula of the invention "- 35 and and what, , , and , , and p A multi-channel calculating device containing a frequency divider, the counter input of which is connected to the clock input, and the control inputs to the control bus input, and a first memory device, the first group of inputs of which is connected to the frequency divider outputs, the second group of inputs to the input control buses, and the outputs - to the first group of outputs, which is distinguished by the fact that " a parallel-to-serial code converter, the timing inputs of which are connected to the outputs of frequency divider 7, and the information inputs are to the control bus input, a communication line, the first input of which is connected to the input c of clock pulses, and the second to the output of the parallel code converter y serial, timer, counting :z" whose input is connected to the output of the clock pulses of the communication line, and the start input - to the output of the serial code of the communication line, the serial code to parallel converter, the information input of which is connected to the output of the serial code of the communication line connection, and the inputs of the time count - to the outputs of the timer, the second storage device, with the first group of inputs of which is connected to the outputs of the timer, and the second group of inputs - to the outputs of the serial code to parallel converter, and the outputs - to the second group of outputs. - 1 ("c") "sl p 60 b5