UA142396U - PERIODIC SEQUENCE FORMER FOR TWO-PULSE CODE SERIES WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

The shaper of the periodic sequence of two-pulse code series with configured time parameters contains: common power supply (± E); reversible binary counter configured for subtraction mode, with input of synchronous parallel loading permission and inputs of loading variables (provide setting of the shaper to the set time parameters of output pulses), input of digital mode resolution and input of asynchronous setting to zero state; JK-trigger with the input of the asynchronous installation to zero; the first and second elements of I; two-input and four-input elements OR; two inverters; a circuit consisting of a series-connected resistor and a capacitor connected to a common power supply, the common point of which is connected to the first inputs of the first and second elements I; the output of the second element And is connected to the input of the asynchronous installation of the counter to zero; the outputs of the second, third and fourth digits of the meter are connected to the inputs of the four-input element OR; the input of the first inverter is connected to the output of the counter overflow; the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz oscillator. Introduced: first and second RS-flip-flops, digital comparator; the third and fourth elements of I; the first and second buttons working on short circuit: the second, third and fourth resistors which first conclusions are connected to a plus of a power supply. The second output of the second resistor forms the output level of the logic unit. The second output of the third resistor is connected to the input S of the first RS-flip-flop and the first contact of the first button. The input R of the first RS-flip-flop is connected to the output of the first element I. The output of the first RS-flip-flop is connected to the first input of the two-input element OR, the second input of which is connected to the output of the comparator and the first input of the fourth element. connected to the second input of the first element And and the first contact of the second button. The second contacts of the buttons are connected to a common point (minus) of the power supply. The output of the first inverter is connected to the input of the resolution of the meter count mode. The input of the second inverter is connected to the output of the first (junior) digit of the meter, and its output is connected to the first input of the four-input element OR. The output of the four-input element OR is connected to the inputs J and K of the JK-flip-flop, with the first input of the third element I and the input of the installation in the unit state of the second RS-flip-flop. The clock input of the JK-flip-flop is connected to the input of the shaper. The second input of the third element I is connected to the overflow output of the counter. The direct output of the second RS-flip-flop is connected to the second input of the fourth element I, the output of which forms the output of the shaper. The first group of inputs of the comparator is connected to the outputs of the corresponding bits of the counter. The inputs of the asynchronous set to zero state of JK and RS-flip-flops are connected to the output of the second element I. When setting the shaper to form a periodic sequence of two-pulse code series, the duration of the first (odd) pulses is equal to seven periods of clock pulses and the second pulses is equal to two periods of clock pulses, the duration of the second (paired) pulses is equal to eleven periods of clock pulses, the duration of the pause between the second and first pulses is equal to one period of clock pulses, ie the period of two pulse series is twenty-one. The delay in the beginning of the formation relative to the start signal is equal to twelve periods. The first input of the parallel load of the counter is connected to the direct output of the JK-flip-flop, the second input is connected to the logic zero level, the third input is connected to the inverse output of the JK-flip-flop. The fourth input is connected to the level of the logical unit. The first input of the second group of inputs of the comparator is connected to the inverse output of the JK-flip-flop. The second input is connected to the direct output of the JK-flip-flop. The third and fourth inputs of the second group of inputs of the comparator are connected to the level of logical zero. The first and third control inputs of the comparator are connected to the logic zero level. The second control input is connected to the level of the logical unit.

Description

counter The inputs of the asynchronous installation in the zero state of the UkK and B5 flip-flops are connected to the output of the second element I. When setting the generator to form a periodic sequence of two-pulse code series, the duration of the first (odd) pulses in which is equal to seven periods of clock pulses, the duration of the pause between the first and second pulses is equal to two periods of clock pulses, the duration of the second (even) pulses is equal to eleven periods of clock pulses, the duration of the pause between the second and first pulses is equal to one period of clock pulses, i.e. the period of passage of two-pulse series is equal to twenty one periods of clock pulses. The delay of the start of formation relative to the start signal is equal to twelve periods. The first input of parallel loading of the counter is connected to the direct output of the UV-trigger, the second input is connected to the logical zero level, the third input is connected to the inverse output of the UV-trigger. The fourth input is connected to the logic unit level. The first input of the second input group of the comparator is connected to the inverse output of the /UkK trigger. The second input is connected to the direct output of the UV trigger. The third and fourth inputs of the second group of comparator inputs are connected to the logical zero level. The first and third control inputs of the comparator are connected to the logical zero level. The second control input is connected to the logic unit level. and KZ Her: E E Ge Va Z kYa; E |:

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The useful model belongs to the pulse technique and is intended for the formation of a periodic sequence of two-pulse code series with the adjusted duration of the pulses, the period of passage and the delay of the start of formation relative to the starting pulse, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of an external quartz generator.

There are known generators that contain a set crystal oscillator operating in continuous mode, a synchronizing device and an output device that ensures the formation of the necessary series of pulses, the time parameters of which are determined by the time parameters of the pulses fed to the input of the clock generator. A.S. USSR Mo 307502. - B.V. Mo20, 1971;

Clock generator. A.S. USSR Mo 354544. - B.V. May 30, 1972 I.

The disadvantage of known devices is limited functionality due to setting the time parameters of the output sequence of pulses to a fixed mode.

Known generators of a periodic sequence of pulses with a programmable duration and fixed spacing (patents of Ukraine for the useful model MoMo 93714, 93715, 93716, 937118, 93734, 93735, 937381.

The disadvantage of these devices is the complexity of their manufacture and, as a result, high power consumption and high cost, which are due to the need to use two reversible counters.

The closest analogue of the utility model in terms of technical essence and the achieved result is the generator of a periodic sequence of two-pulse code series with adjusted time parameters (utility model patent of Ukraine Mo 93714, Bull. Me19, 2014), which contains: common power source (JHE); reversible binary counter configured for the subtraction mode, with the input of enabling synchronous parallel loading and the input of supplying variables to be loaded (provide the adjustment of the shaper to the given time parameters of the output pulses), the input of enabling the counting mode and the input of asynchronous installation in the zero state, the overflow output; UV-trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input and four-input OR elements; two inverters; a circuit consisting of a series-connected resistor and capacitor connected to a common power source, the common point of which is connected to the first inputs of the first and

From the second element I; the output of the second element And is connected to the input of the asynchronous counter installation in the zero state; the outputs of the second, third and fourth digits of the counter are connected to the inputs of the four-input OR element; the input of the first inverter is connected to the overflow output of the counter; the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external crystal oscillator.

The disadvantage of the known device is limited functionality.

The useful model is based on the task of expanding the functionality of the generator of a periodic sequence of two-pulse code series with adjusted time parameters.

The task is solved by having a generator of a periodic sequence of two-pulse code series with adjusted time parameters, which contains: a common power source (PE); reversible binary counter configured for the subtraction mode, with the input of enabling synchronous parallel loading and the input of supplying variables to be loaded (provide the adjustment of the shaper to the given time parameters of the output pulses), the input of enabling the counting mode and the input of asynchronous installation in the zero state, the overflow output; UV-trigger with the input of the asynchronous installation in the zero state; the first and second elements of I!; two-input and four-input OR elements; two inverters; a chain consisting of a resistor and a capacitor connected in series, connected to a common power source, the common point of which is connected to the first inputs of the first and second elements of And; output of the second element I! connected to the input of the asynchronous setting of the counter in the zero state; the outputs of the second, third and fourth digits of the counter are connected to the inputs of the four-input OR element; the input of the first inverter is connected to the overflow output of the counter; the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz generator, according to the useful model, the following are introduced: the first and second Nb flip-flops, a digital comparator; the third and fourth elements. Their first and second buttons, which work to close: the second, third and fourth resistors, the first outputs of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output of the third resistor is connected to input 5 of the first H5 trigger and the first contact of the first button; input A of the first

The Vb-trigger is connected to the output of the first element I; the output of the first No-trigger is connected to 60 the first input of the two-input OR element, the second input of which is connected to the output of the comparator and the first input of the fourth element AND; the second output of the fourth resistor is connected to the second input of the first element I and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the output of the first inverter is connected to the enable input of the counter reading mode; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the output of the four-input OR element is connected to inputs 9 and K

UV-trigger, with the first input of the third element I and the input of the unit to the single state of the second

B5-trigger; the clock input of the DC-trigger is connected to the input of the shaper; the second input of the third element | connected to the counter overflow output; the direct output of the second No-trigger is connected to the second input of the fourth element I, the output of which forms the output of the shaper; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; the inputs of the asynchronous unit in the zero state of the UC and B5 triggers are connected to the output of the second element |; when setting the generator to generate a periodic sequence of two-pulse code series, the duration of the first (odd) pulses in which is equal to seven periods of clock pulses, the duration of the pause between the first and second pulses is equal to two periods of clock pulses, the duration of the second (even) pulses is equal to eleven periods of clock pulses, the duration of the pause between the second and first pulses is equal to one period of clock pulses, that is, the period of passage of two-pulse series is equal to twenty-one periods of clock pulses, the delay of the start of formation relative to the start signal is equal to twelve periods, the first input of parallel loading of the counter is connected to the direct output of the K-trigger, the second input is connected to the logical zero level, the third input is connected to the inverse output of the UV trigger; the fourth input is connected to the level of a logical unit, the first input of the second group of comparator inputs is connected to the inverse output of the UV-trigger, the second input is connected to the direct output of the K-trigger, the third and fourth inputs of the second group of comparator inputs are connected to level of logic zero, the first and third control inputs of the comparator are connected to the level of logic zero, the second control input is connected to the level of logic one.

A useful model is explained by drawings (Fig. 1-3), where in Fig. 1 shows the scheme of the former.

The generator contains: a reversible binary counter (1), which has an input for supplying clock pulses С, an input for setting the summation/subtraction mode Ш, an input for enabling synchronous parallel loading И and inputs for supplying data when loading бо, О:, ХО2, Оз, an enable input of the counting mode E, the input of the asynchronous unit to the zero state B, the overflow output Ra.; the first (2) and second (3) asynchronous A5 triggers; UV-trigger (4) with the input of the asynchronous setting of zero B; four-bit digital comparator (5), which has the first group of inputs Ao, An, Ag, Az, the second group of inputs Vo, Vi, Be2, Vz, the first, second and third control inputs

And the first (b), second (7), third (8) and fourth (9) two-input elements And; two-input element

OR (10); four-input element OR (11); first (12) and second (13) inverters; the first B1 (14), the second B2 (15), the third VZ (16) and the fourth NA (17) resistors; buttons 5iap (18) and 5ior (19), working for closing; capacitor C1 (20).

The common point of the circuit, consisting of a resistor 14 and a capacitor 20 connected in series, is connected to a common power source (5E), connected to the first inputs of the first (b) and second (7) elements of I. The output of the element is connected to by the EC input of trigger 2. The output of element 7 is connected to the input of the asynchronous installation of the counter (1), triggers (3,4) in the zero state.

The outputs of the second (Cx), third (O2) and fourth (Oz) digits of the counter are connected to the inputs of the four-input OR element (11). The input of the inverter 12 is connected to the overflow output (Ra) of the counter, and its output is connected to the enable input of the counting mode (B). The clock input of the counter forms the input of the shaper (C), which receives a continuous periodic sequence of pulses from the output of the external quartz oscillator. The second output of the resistor 15 forms the output of the level of the logical unit "1". The second output of the resistor 16 is connected to the input 5 of the trigger 2 and the first contact of the buy button. The second output of the resistor 17 is connected to the input of the element 6 and the first contact of the button 5ior. The second contacts of the buttons are connected to the common point of the power source (-E). The input of the inverter 13 is connected to the output of the first (O0) digit of the counter, and its output is connected to the first input of the element 11. The output of the element 11 is connected to the input of the element 8, inputs y and K of the trigger 4 and input 5 of the trigger 3. The second input of element 8 is connected to the overflow output of the counter. The direct output of the trigger Z is connected to the first input of element 9, the second input of which is connected to the output А»B of the comparator and to the second input of element 10, the output of element 9 forms the output of the shaper P. The input of the counter is connected to the direct output ( OZ) of the trigger 4. The input of the counter is connected to the logical zero level "0" (with the minus of the power source 60). Input O2 is connected to the inverse output (93) of flip-flop 4. Input Oz is connected to the level of logic unit "1". The first group of inputs (Abo, Ach, Ag, Az) of the comparator (5) is connected to the outputs of the corresponding digits (Co, C, C)2, C)z3) of the counter. The first input (Vo) of the second group of comparator inputs is connected to the inverse output (93) of trigger 4, the second input (Vi) is connected to the direct output (93 of trigger 4, the third (Vg2) and fourth (Vz) inputs of the second group of inputs comparator is connected to the level of logical zero, the first and third control inputs (I) of the comparator are connected to the level of logical zero "0", the second control input is connected to the level of logical unit "1" (with the second output of resistor 15).

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 14 and a capacitor 20 connected to the supply voltage bus "SHE", when the power source is turned on for a certain period of time (determined by the time constant of the circuit H:iC:i) forms a logical zero level at the inputs of elements b, 7, ensuring the formation of a logical zero level at their outputs connected to the input of the asynchronous unit in the zero state of the triggers and the counter. After the end of the transient process associated with turning on the power supply, the flip-flops and the counter go to the zero state, forming a logical zero level, respectively: at the output

A" of the comparator, at the output of the overflow of the counter, which leads to the formation of a logical zero level at the input of element 8 (provides a zero value at the input Y of the counter) at the output of elements 10, 7 (at the inputs A of the counter, ensures its zero state and after the end of the transient process , associated with the charge of the capacitor 20, when the voltage on it will exceed the logical zero level). Since the signal at input A has priority over all other control signals at the inputs of the counter, as long as the logic zero level is maintained at the inputs of elements 10, 7 (and therefore at their outputs), then when clock pulses arrive, the zero state of the counter , triggers and the zero value of the signal at the output of the shaper will remain unchanged.

When the button 5iagi is pressed, a level of logical zero is formed at input 5 of flip-flop 2, which leads to its transition to a single state (01-11), forming a level of logical one at the output of element 10, and therefore at the input and output of element 7 (at the input B of the counter ), removes the zero state lock, and then a zero value on the counter's synchronous parallel loading enable input prepares it to receive information from its synchronous parallel loading inputs

From parallel loading (Oz YuO2 O0y Yuo-1100).

Then, upon arrival of the first (after the end of the transient process associated with the start) clock pulse C along its edge, parallel loading occurs.

The counter goes to the state (О30201000-1100. As a result of this transition, a single value is formed at the overflow output of the counter and the output of element 8, and a zero value is formed at the output of inverter 12 (at the input E of the counter), which leads to the prohibition of parallel loading and the permission of the counter counting mode . The zero state of flip-flop 3 remains unchanged, which ensures a zero value of the output signal regardless of the ratio of the value at the inputs of the first and second groups of the comparator. When the next clock pulses arrive, the content of the counter decreases. At the same time, as long as the content of the counter exceeds a single value , the single value at the outputs of element 11 remains unchanged, which ensures the invariance of the zero value at the direct output of the trigger C and at the output of the shaper.

As soon as the content of the counter becomes equal to 0001, a level of logical zero is formed at the output of element 11, which leads to the formation of a level of logical zero at the input of element 8 (at the input of the permission to load the counter) and at input 5 of flip-flop 3, which leads to its transition to a single state . And then, upon arrival of the next clock pulse, the counter goes into state О3020100-1001, due to the value of the signals generated at its inputs of parallel loading (Оз ХО2 Ой ХОо-1001). On the outputs of the comparator A»B (as well as on the outputs

E of the generator) the formation of a single value begins, since the value of the signals at the outputs of the counter 03020100 exceeds the value of the signals at the inputs of the second group of signals

VzV28V1Vo-0010 comparator.

When the following clock pulses arrive, the content of the counter decreases. At the same time, as long as its content exceeds the value set at the inputs of the second comparator group (VzV2V1Vo-0010), the value of the signal at the output of the generator will remain equal to 1. As soon as the content of the counter becomes equal to 0010, the value of the signal at the output of the comparator will become equal to 0, which leads to the formation of a zero value of the signal at the output of the shaper. When the next clock pulses arrive, the content of the counter continues to decrease, and the value of the signal at the output remains equal to 0. As soon as the content of the counter becomes equal to 0001, the value of the signal at the output of element 11 becomes equal to 0, which leads to the permission to load the counter and to allow the transition of the OK flip-flop to next (zero) state. When the next clock pulse arrives, the counter goes to the state 1100, and the trigger 4 - to zero, which leads to the formation of the value VzV2ViVo-0001 at the inputs of the second comparator group and a single value at the output of the generator. When the following clock pulses arrive, the content of the counter decreases. At the same time, as long as its content exceeds the value set at the inputs of the second comparator group (BzB2B:B0-0001), the value of the signal at the output of the generator will remain equal to 1. As soon as the content of the counter becomes equal to 0001, the value of the signal at the output of the comparator will become equal to 0. As soon as the content of the counter becomes equal to 0001, the value of the signal at the output of element 11 will become equal to 0, which leads to the permission to load the counter and the permission to transition the UV flip-flop to the next (single) state. When the next clock pulse arrives, the counter again goes to state 1001, and trigger 4 - to single, which leads to the formation at the inputs of the second comparator group of the value ВзВ2ВиВО-0010 and a single value at the output of the generator, starting a new cycle of forming a two-pulse code series.

When subsequent clock pulses arrive, the processes are repeated.

Thus, after the end of the transient process associated with the start-up, when entering the input of the generator of a periodic sequence of pulses (with a period equal to T), a periodic sequence of two-pulse code series is generated at the output of the generator, the duration of the first (odd) pulses of which is seven periods of clock pulses (1-7), the duration of the pause between the first and second pulses is equal to two periods (y-21), the duration of the second (even) pulses is equal to eleven periods (yin2-117), the duration of the pause between the second and the next first pulses is equal to two periods (ip2-Y), that is, the period of two-pulse series is equal to twenty-one periods of clock pulses (Te-21T), the delay of the start of formation relative to the start signal is equal to twelve periods (iz-12 1) (Fig. 3).

The output sequence formation mode is stopped by pressing the bor button, which forms a logical zero level at the input and output of element 6, as well as at input A of trigger 2, which leads to its transition to the zero state (01-00). The moment of pressing is asynchronous relative to the pulses of the clock generator and to the state of the counter and triggers.

If at the moment of pressing button 5ior, the content of the counter is less than the value of the signals at the inputs of the second group of signals BzB2B:Bó (the value of the signal at the outputs of the comparator A»B is equal to

From 0), then when trigger 2 goes to the zero state, a logical zero level will be formed at the inputs of element 10 and at its output, causing a zero level at the input and output of element 7 (at input A of the counter), which will lead to the transition of the counter to zero state, and therefore to the termination of the generation mode.

If at the moment of pressing the button 5ior, the content of the counter is greater than the value of the signals at the inputs of the second group of signals VzV2ViVo, then when the tripper 2 goes to the zero state, the unit value at the output of element 10 will remain unchanged, since the level of the logic unit is at the outputs of the comparator A»B. This means that in this case, at the moment of pressing the button, the termination of the generation will not occur, thereby preventing the distortion of the last pulse in the generated output sequence.

At the arrival of each successive pulse at the input of the shaper C, the transition of the counter will occur according to the algorithm until its content becomes equal to the value of the signals at the inputs of the second group of signals VzV2ViVo, causing the level of zero at the input and output and the outputs of elements 10, 7, which will lead to before the transition of the counter to the zero state, and therefore before the termination of the generation mode. The next time you press the 5iag button, all processes are repeated.

In Fig. 2 shows the transition graph of the shaper consisting of four rings. The upper (first) ring is the signal value at the direct output of the second trigger, the second ring is the transition graph of the counter, the third ring is the signal value at the direct output of the UV trigger, the fourth ring is the signal value at outputs of the shaper.

Since the pressing of the Er button is asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range: 12T" to "13T.

Unlike the known device, the claimed former has a new composition of elements and a new organization of communication between them, which provide new technical properties.

The technical result of the useful model is the expansion of the functional capabilities of the former and its area of use by ensuring the delay of the start of formation in relation to the start signal.

Claims (1)

USEFUL MODEL FORMULA Generator of a periodic sequence of two-pulse code series with adjusted time parameters, which includes: a common power source (PU); reversible binary counter configured for the subtraction mode, with the input of enabling synchronous parallel loading and the input of supplying variables to be loaded (provide the adjustment of the shaper to the given time parameters of the output pulses), the input of enabling the counting mode and the input of asynchronous installation in the zero state, the overflow output; /K-trigger with the input of the asynchronous installation in the zero state; the first and second elements of I!; two-input and four-input OR elements; two inverters; a chain consisting of a series-connected resistor and a capacitor connected to a common power source, the common point of which is connected to the first inputs of the first and second elements of And; the output of the second element is connected to the input of the asynchronous installation of the counter in the zero state; the outputs of the second, third and fourth digits of the counter are connected to the inputs of the four-input OR element; the input of the first inverter is connected to the overflow output of the counter; the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz generator, which differs in that it is introduced: the first and second B5o flip-flops, a digital comparator; the third and fourth elements of I; the first and second buttons that work for shorting: the second, third and fourth resistors, the first outputs of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output of the third resistor is connected to input 5 of the first No-trigger and the first contact of the first button; input B of the first B5 flip-flop is connected to the output of the first element |; the output of the first H5 flip-flop is connected to the first input of the two-input OR element, the second input of which is connected to the output of the comparator and the first input of the fourth element AND!; the second output of the fourth resistor is connected to the second input of the first element I and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the output of the first inverter is connected to the enable input of the counter reading mode; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the output of the four-input OR element is connected to the inputs ./ and К of the УК-trigger, with the first input of the third element И and the input of the unit in the single state of the second НО-trigger; the clock input of the OK-trigger is connected to the input of the shaper; the second input of the third element AND is connected to the overflow output of the counter; the direct output of the second H5 trigger is connected to the second input of the fourth element !, the output of which forms the output of the shaper; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; the inputs of the asynchronous unit to the zero state of the K- and B5-triggers are connected to the output of the second element I; when setting the generator to generate a periodic sequence of two-pulse code series, the duration of the first (odd) pulses in which is equal to seven periods of clock pulses, the duration of the pause between the first and second pulses is equal to two periods of clock pulses, the duration of the second (even) pulses is equal to eleven periods of clock pulses, the duration of the pause between the second and first pulses is equal to one period of clock pulses, that is, the period of passage of two-pulse series is equal to twenty-one periods of clock pulses, the delay of the start of formation relative to the start signal is equal to twelve periods, the first input of parallel loading of the counter is connected to the direct output of the UV-trigger, the second input is connected to the logical zero level, the third input is connected to the inverse output of the UV trigger; the fourth input is connected to the level of a logical unit, the first input of the second group of comparator inputs is connected to the inverse output of the K-trigger, the second input is connected to the direct output of the UK-trigger, the third and fourth inputs of the second group of comparator inputs are connected to level of logic zero, the first and third control inputs of the comparator are connected to the level of logic zero, the second control input is connected to the level of logic one. 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