UA136654U - PERIODIC SEQUENCE PULSE FORMER WITH ADJUSTABLE TIME PARAMETERS - Google Patents

Abstract

The periodic pulse generator with reconfigurable time parameters contains a two-input OR element, an inverter, two reversible binary counters, each of which is configured to subtract mode, with synchronous parallel loading input inputs and input variables input settings and input input condition, overflow outputs; a starting device comprising a trigger with the input of an asynchronous zero setting, the first and second two-input elements I, a three-input element OR; a circuit consisting of a resistor connected in series and a capacitor connected to a power supply. Additionally introduced a second resistor, one output of which is connected to the plus power supply, and the second forms the output level of the logic unit, the input of the asynchronous trigger in the unit state, four-digit digital comparator, two four-input elements OR, the third two-input element I and the second, third fourth inverters.

Description

The useful model belongs to pulse technology and is intended for the formation of a periodic sequence with a programmable duration of pulses, a period of passage and a delay of the start of formation relative to the starting pulse, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of an external quartz generator.

There are known generators that contain a setting crystal oscillator operating in continuous mode, a synchronization device and an output device that ensures the formation of the necessary series of pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Clock generator. A.S. USSR Mo 307502. - B.V. Mo 20, 1971; Clock generator. AS USSR Mo 354544. - B.V. Mo 30, 1972).

The disadvantage of known devices is limited functionality due to setting the time parameters of the output sequence of pulses to a fixed mode.

The closest in terms of technical essence and the achieved result is the pulse shaper (utility model patent of Ukraine Mo 53542, Bull. Mo 15, 2010), which contains: a two-input OR element; inverter: two reversible binary counters, each of which is configured for subtraction mode, with synchronous parallel loading enable inputs and tuning variable supply inputs (which provide tuning of the shaper to the given time parameters of the output pulses), a count mode enable input and an asynchronous reset input in the zero state , overflow outputs; a start-stop device containing a trigger with an asynchronous zero setting input, the first and second two-input AND elements, a three-input OR element; a chain consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the second input of the first element AND forms the stop input of the zior formation mode, the output of the first element AND! connected to the input of the asynchronous setting of the trigger to the zero state, the second input of the second element AND is connected to the output of the three-input OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the inputs of the synchronous setting of the counters to zero state; the overflow output of the first counter is connected to the inverter input and the first input of the two-input OR element, the second input of which is connected to the overflow output of the second counter, the output of the two-input OR element is connected to the load enable input of the first counter; the clock inputs of the first and second counters are connected to each other, forming the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz master generator.

The disadvantage of the known device is limited functionality.

The basis of the useful model is the task of expanding the functionality of the periodic pulse sequence generator.

The task is solved by the fact that the pulse generator, which contains a two-input OR element; inverter; two reversible binary counters, each of which is configured for the subtraction mode, with inputs for enabling synchronous parallel loading and inputs for supplying setting variables, an input for enabling counting mode and an input for asynchronous setting to the zero state, and overflow outputs; a start-stop device containing a trigger with an asynchronous zero setting input, the first and second two-input AND elements, a three-input OR element; a chain consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the second input of the first element AND forms the stop input of the formation mode (Bohr), the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second input of the second element of AND is connected to the output of the three-input OR element, the first input of which is connected to the output of the trigger, the input of the second element of AND is connected to the inputs of the synchronous installation of counters in zero state; the overflow output of the first counter is connected to the inverter input and the first input of the two-input OR element, the second input of which is connected to the overflow output of the second counter, the output of the two-input OR element is connected to the load enable input of the first counter; the clock inputs of the first and second counters are connected together, forming the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz master generator, according to a useful model, a second resistor is introduced, one output of which is connected to the plus of the power source, and the second forms the output of the level of a logical unit, the input of the asynchronous trigger unit in the single state, a four-bit digital comparator, two four-input OR elements, the second, third and fourth inverters, while the input of the asynchronous trigger unit in the single state forms the input for starting the formation mode (e5iag); the first group of comparator inputs (AZA2ATAO) is connected to the outputs of the corresponding digits (23020100) of the second counter; the overflow output 60 of which is connected to the input of the second inverter, the output of which is connected to its enable input of the counting mode; the output of the third inverter is connected to the first input of the first four-input OR element; the output of the fourth inverter is connected to the first input of the second four-input OR element; the input of the third inverter is connected to the output of the first digit of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to other inputs of the first four-input OR element; the output of which is connected to the first input of the third element I; the second input of the third element AND! connected to the output of the second four-input OR element; the input of the fourth inverter is connected to the output of the junior digit of the second counter; the outputs of the second, third and fourth digits of the second counter are connected to other inputs of the second four-input OR element; the output of the digital comparator, which forms the output of the shaper, is connected to the third input of the three-input OR element; when setting the generator to form a periodic sequence with a passage period equal to eleven periods of clock pulses, a duration equal to four periods of clock pulses and a delay of the start of formation relative to the start pulse by three periods of clock pulses, the first and second inputs of the parallel loading of the first counter are connected to by the second output of the second resistor (the level of a logical unit), the third and fourth inputs of the parallel load of the first counter are connected to a common point (the level of logical zero), the first, second and fourth inputs of the parallel load of the second counter are connected to the level of a logical unit, the third input of parallel loading of the second counter is connected to the level of logical zero, the first, second and third inputs of the second group of comparator inputs are connected to the level of a logical unit, the fourth input of the second group of comparator inputs is connected to the level of logical zero.

In Fig. 1 shows the scheme of the former, in Fig. 2 - graph of transitions, in Fig. C - graphs illustrating the operation of the shaper for the considered configuration option.

The generator contains two reversible binary counters 1, 2, each of which has an input for supplying synchronization pulses C, an input for setting the summation/subtraction mode Ш, an input for enabling synchronous parallel loading / and inputs for supplying data during loading, an input for enabling the counting mode EE, an input for asynchronous setting to the zero state K, overflow output Ra, trigger Z with inputs of asynchronous setting of zero K and unit 5;

Zo four-bit digital comparator 4; the first 5, the second b, and the third 7 two-input elements AND: two-input element OR 8; three-input element OR 9; first and second four-input elements OR 10 and 11; first, second, third and fourth inverters 12, 13, 14 and 15; resistor K 16. The start-stop device contains a flip-flop C with inputs of an asynchronous installation in the zero and one state, two two-input elements AND 5, 6, a three-input element OR 9, a chain consisting of a series-connected resistor 17 and a capacitor 18 connected to the source power JHE, the common point of which is connected to the first inputs of elements 5 and 6, the second input of element 5 forms the stop input of the forming mode (510p), the output of element 5 is connected to the input K of trigger 3, the second input of element b is connected to the output of element 9, the first input of which is connected to the output О of the trigger, the second - to the overflow output of the first counter, the third - to the output А»B of comparator 4. Input 5 of the trigger forms the start input (Mag) of the mode of forming a given pulse sequence at the output Е shaper (at the output

A»B comparator 4). The output of element 6 is connected to the inputs of the asynchronous installation of counters in the zero state.

When setting the generator to form a periodic sequence of pulses with a duration ii equal to four periods of clock pulses (1-4), a passage period Te equal to eleven periods of clock pulses (Te-11T), and a delay of the start of formation relative to the start pulse by three periods of clock pulses (I3-37T), at the inputs of the synchronous parallel loading of the first counter 1, a value equal to three is set (О3020100-0011), at the inputs of the synchronous parallel loading of the second counter 2 - a value equal to eleven (О3020100-1011), at the inputs of the second group of comparator inputs 4 - value equal to seven (VzV2V1iVo-0111).

The input of allowing synchronous parallel loading of counter 1 is connected to the output of element 8, the inputs of which are connected to the overflow outputs of the first 1 and second 2 counters.

The output of the lower digit Oo of counter 1 is connected to the input of element 14, the output of which is connected to the input of element 10. The remaining inputs of element 10 are connected to other outputs of counter 1, the output of element 10 is connected to the input of element 7.

The synchronous parallel loading permission input of counter 2 is connected to the output of element 7, the second input of which is connected to the output of element 11. The output of the lower digit Oo of counter 2 is connected to the input of element 15 and the input of the lower digit of the first group of inputs

Comparator A 4. The output of element 15 is connected to the first input of element 11. The remaining inputs of element 10 and the first group of inputs A of comparator 4 are connected to other outputs of counter 2.

The former works in the following sequence.

The presence of a chain consisting of a series-connected resistor 17 and a capacitor 18 connected to the supply voltage bus E, when the power source is turned on for a certain period of time (determined by the time constant of the circuit K:C:i) forms a logical zero level at the inputs of elements 5, 6 , ensuring the formation of a logical zero level at their outputs connected to the inputs of the asynchronous installation in the zero state of trigger C and counters 1, 2. After the end of the transient process associated with turning on the power source, the trigger and both counters go to the zero state, forming the level of logical zero, respectively, at the output of the trigger and at the overflow outputs of counters 1, 2, which leads to the formation of a logical zero level at the output of element 9, which ensures confirmation (blocking) of the logical zero level at its output and after the transient process associated with the charge capacitor 17, when the voltage on it will exceed the level of logical zero, which ensures the level of logical zero at the inputs K synchronous setting of counters 1, 2 in the zero state. Since the mode of asynchronous setting of the counters to the zero state has priority over all other modes, as long as the logical zero level remains at the input of the OR element 9 (and therefore at its output), the zero state of the counters will remain unchanged.

When the start pulse (5iagi) arrives at input 5 of flip-flop Z, its transition to the single state 2-1 occurs, forming the level of a logical unit at the output of element 9, and therefore at the input and output of element 6, which ensures the level of a logical unit at the inputs K of the counters, removing the blocking, and then the active value at the synchronous parallel download permission input of counter 1 prepares to receive information from the Oz0O20100-0011 inputs.

Upon arrival of the first (after the end of the transient process associated with the start) clock pulse C along its front, parallel loading occurs, counter 1 goes into state Oz302010)0-0011. As a result of this transition, a single value is formed at the overflow output of counter 1 and the output of element 7, and a zero value is formed at the output of inverter 12, which leads to the prohibition of parallel loading and the enablement of the counting mode of counter 1. The initial (zero) state of counter 2 and the zero value of the signal on come out

From the shaper remains unchanged.

When the second clock pulse arrives (after the transient process ends), the content of counter 1 becomes equal to 0001, as a result of which a logical zero level is formed at the output of element 10, which leads to the formation of a logical zero level at the input of element 7 (at the enable input of counter 2). And then, when the next (third) clock pulse arrives, counter 1 goes to the zero state, and counter 2 goes to the state determined by the value of the signals at its inputs of parallel loading (O30201O00-1011), which leads to the formation of a single value at the output of the shaper. At the same time, as long as the content of counter 2 exceeds the value set at the inputs of the second group of comparator 4 (0111), the value of the signal at the output of the generator will remain equal to 1. As soon as the content of counter 2 becomes equal to 0111, the value of the signal at the output of the generator will become equal to 0. When the following clock pulses arrive, the content of counter 2 continues to decrease, and the value of the signal at the output will remain equal to 0 until the content of counter 2 becomes equal to 0001. As soon as counter 2 goes to the state 0001, at the output of elements 11 and 7 and a logical zero level is formed at the load enable input of counter 2. When the next clock pulse arrives, counter 2 again goes to state 1011, forming the average arithmetic value at the output. When subsequent clock pulses arrive, the processes are repeated.

Thus, after the end of the transient process associated with the start-up, during the input to the generator of a periodic sequence of pulses (with a period equal to T), a periodic sequence of pulses is generated at the output of the generator, a multiple of the period of clock pulses, the time parameters of which (pulse duration and /-4T, the duration of the pause yp-7T, the duration of the delay from the start of formation relative to the start pulse for three periods of clock pulses yz3-3Tt, the passage period Toe-11T are determined by the values of the setting variables set at the inputs of parallel loading of counters 1, 2 and comparator 4.

The stop of the mode of formation of the output sequence is carried out by applying a pulse corresponding to the logical zero level to the stop input (or), which forms an active signal level at the input of the asynchronous unit K trigger 7, which leads to its transition to the zero state (0-0). The Zior pulse is asynchronous with respect to the pulses of the clock generator and to the state of counters 1, 2.

If at the moment of arrival of the pulse (Zior) the content of counter 2 is less than or equal to 0111, then when the trigger goes to the zero state, a logical zero level will be formed at the inputs of element 9 and at its output, causing a zero level at the input and output of element 6, which will lead to until blocking the zero state of the first counter and transition of the second to the zero state, and therefore before the termination of the generation mode.

If at the moment of arrival of the pulse (5ior) the content of the counter 2 is greater than 0111, then when the flip-flop З goes to the zero state, the single value at the output of the element 9 will remain unchanged, since the level of the logical unit is at the output of the comparator 4. It follows that in this case, at the moment of arrival of the pulse (5ior), the termination of generation will not occur, thereby preventing the distortion of the last pulse in the formed output sequence. When each successive pulse arrives at the input of the shaper C, the transition of the second counter 2 will occur, according to the algorithm, until its content becomes equal to 0111, causing the level of zero at the input and output of element 6, which will lead to the transition of the counter 2 to zero state, and therefore to the termination of the generation mode. With the arrival of the next pulse that starts the trigger, all processes are repeated.

Independent setting of the former for the given duration of pulses and pauses, as well as the delay of the start of formation relative to the starting pulse, expands its functionality and scope of use.

Claims (1)

USEFUL MODEL FORMULA A periodic pulse train generator with reconfigurable time parameters, which contains a two-input OR element; inverter; two reversible binary counters, each of which is configured for the subtraction mode, with inputs for enabling synchronous parallel loading and inputs for supplying setting variables, an input for enabling counting mode and an input for asynchronous setting to the zero state, and overflow outputs; a start-stop device containing a trigger with an input of an asynchronous setting of zero, the first and second two-input elements I. a three-input element OR; a circuit consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to With the first inputs of the first and second elements I, the second input of the first element I forms the stop input of the formation mode (5i0or), the output of the first element I! connected to the input of the asynchronous setting of the trigger to the zero state, the second input of the second element AND is connected to the output of the three-input OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the inputs of the synchronous setting of the counters to zero state; the overflow output of the first counter is connected to the inverter input and the first input of the two-input OR element, the second input of which is connected to the overflow output of the second counter, the output of the two-input OR element is connected to the load enable input of the first counter; the clock inputs of the first and second counters are connected to each other, forming the input of the shaper, which receives a continuous periodic sequence of pulses from the output of an external quartz master generator, which differs in that a second resistor is introduced, one output of which is connected to the plus of the power source, and the second forms the output of the level of a logical unit, the input of the asynchronous trigger unit in the single state, a four-bit digital comparator, two four-input OR elements, the second, third and fourth inverters, while the input of the asynchronous trigger unit in the single state forms the input for starting the formation mode (5iap); the first group of comparator inputs is connected to the outputs of the corresponding digits of the second counter; the overflow output of which is connected to the input of the second inverter, the output of which is connected to its enable input of the counting mode; the output of the third inverter is connected to the first input of the first four-input OR element; the output of the fourth inverter is connected to the first input of the second four-input OR element; the input of the third inverter is connected to the output of the first digit of the first counter; the outputs of the second, third and fourth digits of the first counter are connected to other inputs of the first four-input OR element; the output of which is connected to the first input of the third element I; the second input of the third AND element is connected to the output of the second four-input OR element; the input of the fourth inverter is connected to the output of the junior digit of the second counter; the outputs of the second, third and fourth digits of the second counter are connected to other inputs of the second four-input OR element; the output of the digital comparator, which forms the output of the shaper, is connected to the third input of the three-input OR element; when setting the generator to generate a periodic sequence with a passage period equal to eleven periods of clock pulses, a duration equal to four periods of clock pulses and a delay of the start of the formation relative to the start pulse for three periods, the first and second inputs of the parallel loading of the first counter are connected to the second by the output of the second resistor (the level of a logical unit), the third and fourth inputs of the parallel loading of the first counter are connected to a common point (the level of logical zero), the first, second and fourth inputs of the parallel loading of the second counter are connected to the level of a logical unit, the third input of the parallel loading of the second counter is connected to the logical zero level, the first, second and third inputs of the second group of comparator inputs are connected to the logical unit level, the fourth input of the second group of comparator inputs is connected to the logical zero level. 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