UA136205U - FORMER OF SINGLE THREE-PHASE SERIES OF PULSEWAYS WITH ADJUSTABLE DURATION AND DELAY OF THE BEGINNING OF FORMATION REGARDING THE STARTING PULSE - Google Patents

Abstract

The shaper of a single three-phase series of pulses with reconfigurable duration and delay of the beginning of formation relative to the starting pulse has two binary counters, the first of which is reversible, set to subtraction mode, having input pulse of synchronization pulses, input of input digit mode resolution, asynchronous setup input to zero state, bit outputs, overflow output; the starting device, which contains a trigger with the input of the asynchronous set to zero and a circuit consisting of a series-connected resistor and a capacitor, is connected to a power supply; the first and second elements of I; the first and second two-input elements OR. Additionally introduced: four-bit cyclic device with a sequence of transitions 0000-0001-0011-0111-1111-1110-1100-1000 (second counter, Johnson counter) with the input of the synchronous loading permission (transition), the loading input of the first digit connected to the inverse output of the fourth category; the input of the asynchronous zero setting, made on four synchronous D-flip-flops with the input of the synchronous transition resolution; three-input element OR; the third and fourth elements of I; first and second inverters; the starting device is made on an asynchronous RS-trigger.

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a single three-phase series of pulses with adjustable duration and delay of the start of formation relative to the starting pulse.

There are well-known generators that contain a quartz setting generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov. Basic digital technology. - M.: MIR, 2001. - Fig. 5.13-5.18).

The disadvantage of known devices is the complexity of the internal structure.

There are well-known generators of a periodic multiphase sequence of pulses with adjustable time parameters (Ukrainian invention patents Mo Mo 87081, 89240, 106091, 106395, 10807, 106867, 10888, 106091, 107028).

The disadvantage of the devices is the complexity of the structure, due to the need to use two multi-bit binary counters, decoders.

The closest in terms of technical essence and the result achieved is the generator of a single three-phase series of pulses with adjustable duration (patent of Ukraine for utility model 86547), which contains two reversible binary counters configured for subtraction mode, having an input for supplying synchronization pulses, an input for permission synchronous parallel loading and data feed inputs during loading, digit mode enable input, asynchronous setup input to the zero state (at the same time, the active signal on the synchronous parallel download enable input has priority over the active signal on the digital mode enable input, and the active signal on the input of the asynchronous installation in the zero state has priority in relation to the active signal at the input of the permission of synchronous parallel loading and at the input of the permission of the digital mode), discharge outputs, overflow output; a decoder with an input for enabling signals on the outputs connected to the outputs of the second counter's digits, a start-stop device that contains a trigger with an input of an asynchronous installation in the zero state and a chain consisting of a resistor and a capacitor connected in series, connected to the power source; the first, second elements of I; the first and second OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs

From the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first element OR is connected to the input of the second element AND!; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator.

The disadvantage of this device is limited functionality.

The basis of a useful model is the task of spreading functional capabilities due to the introduction of a delay in the start of formation relative to the starting pulse.

The problem is solved by the fact that in the generator of a single three-phase series of pulses with adjustable duration and delay of the start of formation relative to the start pulse, which contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for enabling synchronous parallel download and input of data supply during download, input of permission of counting mode, input of asynchronous installation in the zero state, outputs of discharges, output of overflow; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first and second elements of I; first and second two-way OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; output of the first element

OR connected to the first input of the second element AND; the output of the second element I is connected to the inputs of the asynchronous installation of counters in the zero state; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator, according to the useful model introduced: a four-bit cyclic device with a sequence of transitions 0000-0001-0011-0111- 1111-1110-1100-1000 (the second counter, Johnson counter ) with the synchronous loading (transition) enable input, the loading input of the first digit connected to the inverse 60 output of the fourth digit; input of asynchronous setting of zero, performed on four synchronous SW flip-flops with input of permission of synchronous transition; three-input element OR; the third and fourth elements of I!; first and second inverters; the start-stop device is made on an asynchronous KoZ trigger; the inputs of the three-input OR element are connected to the outputs of the second, third and fourth digits of the first counter; the overflow output of the first counter is connected to the input of the first inverter, the output of which is connected to the first input of the second element

OR; the second input of the second OR element is connected to the output of the three-input OR element; the output of the second OR element is connected to the transition enable input of the second counter; the output of the fourth digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element Ii; setting the shaper to form a single three-phase series with the given parameters (the duration of the first, second and third pulses and the delay of the start of formation relative to the start pulse) is provided by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the level of logical zero or one depending on the set values of these parameters, and the nature of the schematic implementation of the output functions; the output of the third element forms the output of the first phase of a single series (1); output of the fourth element | forms the output of the third phase of a single series (EZ3); the output of the second digit of the second counter forms the output of the second phase of the single series (2); when setting the shaper to form a single three-phase series, the duration of the first pulse of which is equal to two periods of clock pulses (supplied to the shaper input from the output of an external quartz generator), the duration of the second pulse is equal to eight periods, the duration of the third pulse is equal to four periods, with a delay in the start of formation relative to of the start pulse, which is equal to ten periods, the first and third inputs of the synchronous parallel loading of the first counter are connected to the logical zero level, the second loading input is connected to the logical one level, the fourth loading input is connected to the direct overflow output (with the output of the first inverter); the inputs of the third element AND are connected to the direct output of the first and the inverse output of the second digits of the second counter; inputs of the fourth element AND! connected to the direct output of the fourth and inverse output of the second digits of the second counter; a single value at the output of the second phase is formed at the output of the second digit of the second counter,

In fig. 1 shows the scheme of the former.

З The shaper contains: the first (1) and the second (2) binary counters, the first of which is a reversible four-bit counter configured for the subtraction mode, which has an input for supplying synchronization pulses C, an input for enabling synchronous parallel loading (I) and inputs for supplying data during loading ( Оо-Оз), the input of the permission of the counting mode (Е), the input of the asynchronous installation in the zero state (К), the outputs of the discharges (00-Сз), the overflow output (Ре); a four-bit cyclic device (2) with a sequence of transitions 0000-0001-0011-0111-1111-1100-1000 (the second counter) is made on four synchronous SW flip-flops with an input (I) enabling synchronous loading (transition), an input of loading the first bit ( О0о) and the input of the asynchronous installation to the zero state (K); K5 - trigger (3); the first (4), second (5), third (b) and fourth (7) two-input elements I; the first (8) and second (10) two-input OR elements; three-input element OR (9); the first (11) and second (12) inverters; resistor (13) and capacitor (14) are connected in series, connected to the same power source.

The common point of series-connected resistor 13 and capacitor 14 is connected to the first inputs of elements 4, 5. The second input of element 4 is connected to the output of inverter 12. The output of element 4 is connected to the input of the installation in the zero state of the K5-trigger. The second input of element 5 is connected to the output of element 8, the first input of which is connected to the output of the K5 flip-flop, and the second - to the output of the fourth digit (Oz) of the second counter. The output of element 5 is connected to the input (K) of setting the counters to the zero state. The inputs of element 9 are connected to the outputs of the second (О)), third (02) and fourth (03) digits of counter 1. The output of element 9 is connected to the input of enabling the load mode (I) of counter 1 and the input of element 10. The second input element 10 is connected to the output of inverter 11, the input of which is connected to the overflow output (Ra) of counter 1. The output of element 10 is connected to the input of enabling the transition mode (I) of counter 2. The output of the fourth digit (C) of the counter 2 is connected to the input of the inverter 12, the output of which is connected to the second input of element 4. The clock inputs (C) of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator.

Tuning the generator to form a single three-phase series with the given parameters (the duration of the first, second and third pulses and the delay of the start of formation relative to the start pulse) is ensured by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the level of logical zero or one depending on the set values of these parameters. When setting the shaper to form a single three-phase series, the duration of the first pulse of which is equal to two periods of clock pulses (11-27) (supplied to the input of the shaper from the output of an external quartz generator), the duration of the second pulse is equal to eight periods (2-81), the duration of the third pulse is equal to four periods (iz-4T), with a delay of the start of formation relative to the starting pulse, which is equal to ten periods (I3-10T), the first (Со) and third (О2) inputs of the synchronous parallel loading of the first counter are connected to the logic level zero, the second input (01) of the load is connected to the level of a logical unit, the fourth input (Oz) of the load is connected to the direct output of the overflow (with the output of the first inverter (Юо-02-0, 01-1, ЮОз-Ра). The output of element 6 forms the output of the first phase of the single series 1-00 8 SL, The output of element 7 forms the output of the third phase of the single series Е3-О3 8. СУ, The output of the second digit of the second counter forms the output of the second phase of the single series E2 -:01.

The presence of a circuit consisting of a series-connected resistor 13 and a capacitor 14 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs , that is, at the inputs of the asynchronous installation in the zero state (K) of the trigger and counters. At the end of the charge of the capacitor, the unit value at the first inputs of elements 4, 5 remains unchanged.

After the end of the transient process associated with turning on the power source, the counters and the trigger go to the zero state, forming: the logical zero level at the overflow output of counter 1, at its outputs Oo-Oz, at the output of element 9, the signal value at which is equal to the logical the sum of the signals from the outputs C, 2, Oz (I -031 m О2 m Oz), at the output of element 8, which is connected to the input of element 5, which provides a logical zero level at the inputs Kk of the asynchronous installation to the zero state of the counters and upon completion of the transient process associated with the charge of capacitor 14. Since the mode of asynchronous setting of the first and second counters to the zero state has priority over all the last modes, as long as the logic zero level is maintained at the inputs of element 8, upon the arrival of clock pulses the zero state of the first and second counters will remain unchanged, that is, the zero value at the outputs of the generator will also remain unchanged.

During the arrival of the trigger pulse (ziag) at the input 5 of the C flip-flop, the flip-flop goes into a single state, forming the level of a logical unit at its output (0-1), the output of element 8, and therefore at the input and output of element 5, which provides a level of logic units at the K inputs of the first and second counters, removing the blocking. Since the level of logical zero is at the input of I. counter 1, and the level of logical one is at the input of counter 2, then until the next clock pulse arrives, the first counter is in the loading readiness mode, and the second counter is in the transition prohibition mode.

During the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at its parallel loading inputs

O3020100-1010. Counter 1 goes to the state О3020:00-1010-10 (ten), which leads to the formation of a single value at the overflow output of counter 1, a single value at the outputs of elements 9, 10, at the inputs of Г! counters, i.e. prohibition of loading counters, enabling the counting (subtraction) mode of counter 1. During the arrival of further clock pulses, the content of counter 1 will decrease, and the zero state of the second counter remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 9, 10. As a result, the first counter goes into download mode, and the second into transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals at their inputs Yuz0O20100-0010. Counter 1 goes into state Oz0201О0-0010-2. The second counter will go to the next state О3020100-0001-1, forming a single value at the output E1.

In the future, the processes are similar, that is, every time, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 9, 10. As a result, the first counter goes into loading mode, and the second counter goes into transition mode. A single value at the output E2 is formed and remains unchanged in the states of the second counter: 0011, 0111, 1111, 1110. At the same time, as soon as the content of counter 2 becomes equal to 1111, a zero value is formed at the output of the inverter 12 and the input K of the trigger Z, which leads to transition of the trigger to the zero state (2-0). The single value at the output of the EZ is formed in the following states: 1100, 1000. In the future, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 9, 10, the second counter goes into the mode of enabling the transition. And then, during the arrival of the next clock pulse, the transition of the second counter to the zero state occurs, forming a zero value at the outputs of elements 8, 5, which will lead to the transition to the zero state 60 of the first counter, and therefore to the termination of the formation process.

With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the graph of transitions of the shaper, which consists of five rings, the upper (first) ring is the transition graph of counter 1, the second ring is the transition graph of the second counter, the third ring is the value of the signals at the output E1, the fourth ring is the value of the signals at the output E2, p' ring value of the signals at the output of the EZ, with a common peak corresponding to the zero state of the counters, and in Fig. C shows graphs illustrating the work for the given configuration option Oo-02-0, 0-1, YuOz-R. for the formation of a single three-phase series of pulses, the duration of the first pulse of which is equal to two periods of the clock pulses supplied to the input of the shaper from the output of the external quartz generator (11-27), the duration of the second pulse is equal to eight periods (12-81), the duration of the third pulse is four periods (iz-4T), with a delay in the beginning of the formation of the series relative to the starting pulse, which is equal to ten periods (iz-10T). Since the start pulses are asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range: 10Т« из -11тТ.

In contrast to the known device, the presence of a delay in the start of formation relative to the start pulse extends the functionality of the former, the simplification of the structure of the start-stop device and the second counter simplifies the former's manufacturing technology, reduces power consumption and cost.

Claims (1)

UTILITY MODEL FORMULA A single three-phase pulse train generator with adjustable duration and start delay relative to the start pulse, which contains two binary counters, the first of which is reversible, configured for subtraction mode, having a sync pulse supply input, a synchronous parallel loading enable input and supply inputs data during loading, the input of the permission of the counting mode, the input of the asynchronous installation in the zero state, the outputs of the digits, the output of the overflow; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first and second elements of I; the first and second two-input OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the second AND element; the output of the second element I is connected to the inputs of the asynchronous installation of counters in the zero state; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator, which differs in that it is introduced: a four-bit cyclic device with a sequence of transitions 0000-0001-0011-0111-1111-1110-1100-1000 (second counter, Johnson counter) with a synchronous load (transition) enable input, the load input of the first digit connected to the inverse output of the fourth digit; input of asynchronous setting of zero, performed on four synchronous SW flip-flops with input of permission of synchronous transition; three-input element OR; the third and fourth elements of I; first and second inverters; the start-stop device is made on an asynchronous No-trigger; the inputs of the three-input OR element are connected to the outputs of the second, third and fourth digits of the first counter; the overflow output of the first counter is connected to the input of the first inverter, the output of which is connected to the first input of the second OR element; the second input of the second OR element is connected to the output of the three-input OR element; the output of the second OR element is connected to the transition enable input of the second counter; the output of the fourth digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element I; setting the shaper to form a single three-phase series with given parameters (the duration of the first, second and third pulses and the delay of the start of formation relative to the start pulse) is ensured by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the logical zero level, or units depending on the given values of these parameters and the nature of the schematic implementation of the output functions; the output of the third element I forms the output of the first phase of the single series (E1); the output of the fourth element I forms the output of the third phase of the single series (ЕЗ3); the output of the second digit of the second counter forms the output of the second phase of the single series (E2); when setting the shaper to form a single three-phase series, the duration of the first pulse of which is equal to two periods of clock pulses (supplied to the shaper input from the output of the external generator), the duration of the second pulse is equal to eight periods, the duration of the third pulse is equal to four periods, with a delay in the start of formation relative to of the start pulse, which is equal to ten periods, the first and third inputs of the synchronous parallel loading of the first counter are connected to the logical zero level, the second loading input is connected to the logical one level, the fourth loading input is connected to the direct overflow output (with the output of the first inverter); the inputs of the third element are connected to the direct output of the first and the inverse output of the second digits of the second counter; the inputs of the fourth element AND are connected to the direct output of the fourth and the inverse output of the second digits of the second counter; a single value at the output of the second phase is formed at the output of the second digit of the second counter. chic with VE Z z z ra rve. and eV. в и пи NN more ooo In What I with I I | E not ZE Ku Ya i i o ZE ZHE di i SHU EE: SHI ; iv y I S-Z ts s: Z o U - boju Z reshe Z Z dpnchyannannd nannya V eta y : shiy y Fig. NK KO ND en ny pi I E sake svky kovu same ek ha EE dni na sho ny no to py NY tinu I : | І І і покой нн жо жо від" with the year уюююююююю" гнка ОО ОО» o In se k i a vnshi Mnir IN OKO ODO O Fig. 2