UA122992U - PERIODIC SEQUENCE FORMER WITH ADJUSTED PULSE AND PAUSE DURATION AND PROGRAMMED BEGINNING FORMATION AFTER STARTING - Google Patents

Abstract

A periodic shaper with a reconfigurable pulse and pause duration and a programmable delay of the start of the formation relative to the start pulse contains two binary counters. The first of which is reversible, tuned to the subtraction mode, having the input pulse synchronization, the input of the synchronous parallel load and the inputs of the feed at boot, the values of the signals of which determine the time parameters of the pulse sequence at the input. The second counter is made single-digit (the second D-flip-flop with the input of the transition resolution - L and the input of the asynchronous installation to the zero state), which provides the formation of pulses at the input. The first group of inputs of the unicast multiplexer forms the inputs of the programmer programming for a predetermined delay time of the beginning of the formation of a periodic sequence with a reconfigured pulse duration and a pause relative to the starting pulse. The second group of inputs of the multiplexer forms the inputs of the shaper setting for a given pulse duration and output pause. The outputs of the multiplexer are connected to the inputs of parallel loading of the first counter. The starting device contains a synchronous D-trigger with the input of the asynchronous zero setting, which provides the start and stop of pulse formation.

Description

The useful model belongs to the pulse, computing and measuring equipment, designed for the formation of a periodic sequence with adjustable duration of pulses and pauses and a programmable delay of the start of formation relative to the starting pulse.

Well-known analogs are generators containing a quartz reference generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. - M.: "MIR" 2001. - Fig. 5.13-5.18).

The disadvantage of analogues is the complexity of the internal structure.

Well-known analogues are pulse generators with adjustable duration (patents

of Ukraine for useful model MoMo 56879, 57976, 58272, 59473, 59474, 59481, 61842, 62967, 63177).

The disadvantage of analogues is the complexity of the structure, due to the need to use two multi-bit binary counters.

The closest analogue to the utility model is a periodic sequence generator with adjustable pulse and pause durations and a programmable delay of the start of formation relative to the start pulse (Ukraine patent for a utility model Mo 61853, which contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has sync pulse input, synchronous parallel load enable input and data load input inputs, count mode enable input, asynchronous set to zero input, overflow output; inverter; circuit consisting of series connected resistor and capacitor connected to the source power supply; a start-stop device that contains a synchronous SW flip-flop with an input of an asynchronous device in the zero state, the first and second two-input AND elements; the first, second and third OR elements, while the first input of the first OR element is connected to the output of the SW flip-flop; the output of the first OR element is connected to the first input of the dru of that element I!; the common point of the series-connected resistor and capacitor is connected to the information input of the JO-trigger, with one input of the first and the second input of the second element I; output of the first element

Zo is connected to the input of the asynchronous installation of the Y-trigger in the zero state; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of the closest analogue is the complexity of the scheme of reconfiguring the shaper for a given duration of pulses, which is due to the need to use a second counter that determines the given duration and, as a result, high power consumption and high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that the generator of a periodic sequence with adjustable duration of pulses and pauses and a programmable delay of the start of the formation relative to the start pulse contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for enabling synchronous parallel loading and input of data supply during loading, input of the permission of the counting mode, input of the asynchronous installation in the zero state, overflow output; inverter; a circuit consisting of a series-connected resistor and capacitor connected to a power source; start-stop device, which contains a synchronous SW-trigger with an input of an asynchronous installation in the zero state, the first and second two-input elements I; the first, second and third OR elements, while the first input of the first OR element is connected to the output of the O-trigger; the output of the first element is ORed to the first input of the second element

The common point of the series-connected resistor and capacitor is connected to the information input of the JO-trigger, with one input of the first and the second input of the second elements of I!; output of the first element I! connected to the input of the O-trigger asynchronous installation in the zero state; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input for the supply of pulses to stop the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses, according to the useful model, a unidirectional multiplexer is introduced, and the second counter is made single-bit (the second O-flip-flop with the input of the transition permission - G. and the input of the asynchronous installation in the zero state) ; the first group of multiplexer inputs forms inputs for programming the shaper for the specified duration of the delay of the start of the formation of a periodic sequence with a reconfigurable duration of pulses and pauses relative to the start pulse, the second group of multiplexer inputs forms inputs for setting the shaper for the specified duration of pulses and pauses at the output; the outputs of the multiplexer are connected to the inputs of the parallel loading of the first counter; while setting to form a sequence of pulses with a duration equal to two periods of clock pulses fed to the input of the shaper from the output of an external quartz oscillator, and the duration of the pause is equal to nine periods of clock pulses, the second input of the second group of multiplexer inputs is connected to by the inverse output of the second SW flip-flop, the third input of the second group of multiplexer inputs is connected to the logical zero level, the first and fourth inputs of the second group of multiplexer inputs are connected to the second input of the first OR element and the direct output of the second SW flip-flop, which forms the output shaper, the address input of the multiplexer is connected to the overflow output of the first counter and the input of the inverter, the output of which is connected to the first input of the second element

OR; the output of the second OR element is connected to the transition permission input of the second counter (its input of the second U-trigger); the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element, the output of which is connected to the second input of the second OR element and the input of allowing synchronous loading of the first counter.

A useful model is explained with drawings.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for configuring the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and inputs for supplying data to be loaded 0о-ХО3, an input for enabling the counting mode Ро , the input of the asynchronous installation to the zero state YAN, the overflow output R.y; synchronous ОЙ - trigger 2 with the input of allowing the transition of the GI. and the entry of the asynchronous installation into the zero state of the KE; synchronous O-trigger Z with input

From the asynchronous installation to the zero state B; the first 4 and the second 5 elements of I; the first 6, the second 7 and the third 8 elements OR; inverter 9; a unidirectional multiplexer (10), the first group of inputs of which (Юоо-ЮОоз) forms the inputs (rzb2ribo) for programming the duration of the delay of the start of the formation relative to the start pulse (5iagi), the second group of inputs (О10-О13) of the multiplexer forms the inputs for adjusting the shaper to the specified duration of the pulses and pauses; a chain consisting of a series-connected resistor 11 and a capacitor 12. The common point of a series-connected resistor 11 and a capacitor 12 connected to the power source (uE) is connected to the information input of the trigger 3, to one input of element 4 and to one input element 5.

The second input of element 4 forms the input of the supply of stop pulses (Sior) of the formation of output pulses.

When setting the shaper to generate a sequence of pulses, the duration of which is equal to two periods of clock pulses (supplied to the input of the shaper from the output of an external quartz generator), and the duration of the pause is equal to 9T, the second (011) input of the second group of multiplexer inputs is connected to the inverse output of the second SW flip-flop, the third (O:2) input of the second group of multiplexer inputs is connected to the logical zero level, the first (O:o) and fourth (Phiz) inputs of the second group of multiplexer inputs are connected to the second input of the first element

OR and with the direct output of the second SW-trigger, which forms the output (ER) of the shaper. The address input of the multiplexer (A) is connected to the overflow output of counter 1 and the input of inverter 9, the output of which is connected to the first input of element 7. The output of element 7 is connected to the enable input of the second counter (input | trigger 2). The outputs of the second (0), third (O") and fourth (Oz) digits of counter 1 are connected to the inputs of element 8, the output of which is connected to the second input of element 7 and the input (HER) of enabling synchronous parallel loading of counter 1. Direct the output of flip-flop 2 is connected to the second input of element 6. The inverse output of flip-flop 2 is connected to its input 0. The output of element 5 is connected to inputs B of counter 1 and flip-flop 2. Clock inputs C of counter 1 and flip-flop 2 are connected to each other , forming the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator. The clock input C of the trigger Z forms the input of the supply of start pulses (stage of the formation of output pulses).

A useful model works as follows.

The presence of a circuit consisting of a series-connected resistor 11 and a capacitor 60 12 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs, that is, at inputs B of the asynchronous installation in the zero state of trigger 3, trigger 2 and counter 1.

After the transient process associated with turning on the power supply, the triggers and the counter go to the zero state, forming a logical zero level at the outputs of triggers 2, З and at the outputs of counter 1, respectively, which leads to the formation of a logical zero level at the output of element 6, which is connected to the input of element 5, which provides a logical zero level at the inputs of the MK asynchronous setting to the zero state of counter 1 and trigger 2 and after the end of the transient process associated with the charge of capacitor 12. Since the mode of asynchronous setting of the counter and trigger to zero state has priority in relation to all the last modes, then as long as the logic zero level is maintained at the input of element 6 (and therefore at its output), when clock pulses arrive, the zero state of counter 1 and flip-flop 2 will remain unchanged, i.e. will remain unchanged a zero value on its overflow output, on the output of element 8, on the enable input of the counter load 1, on the address at the input of the multiplexer, at the output of the shaper, a single value at the output of the inverter, at the input and output of element 7, i.e. at input I of trigger 2.

During the arrival of the start pulse (5iap) to the clock input C of the flip-flop Z on its edge, the flip-flop goes into a single state (0-10 -0), forming a logical unit level at the output of element b, and therefore at the input and output of element 5, which provides the level of a logical unit at the inputs B of counter 1 and flip-flop 2, removing the blocking of the zero state. Since the I input of counter 1 has a logical zero level, and the Y input of trigger 2 has a logical one level, then by the time of the arrival of the next clock pulse, counter 1 is in the loading readiness mode, and trigger 2 is in the transition prohibition mode.

During the arrival of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals that are applied to the corresponding inputs Oo-Yuz from the outputs of the multiplexer, determined by the values of the signals at its inputs of the first group

The counter goes into the state Oz3-rz, O2-Yur2, 01-r1i, Oo-ro, which leads to the formation of a single value at the overflow output of counter 1, at the output of element 8 and zero

From the value at the output of the inverter 9, forming a zero value at its output. The zero state of trigger 2 (the zero value of the signal at the output of the shaper) remains unchanged.

As a result of this transition, counter 1 will enter the counting (subtraction) mode. During the introduction of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 7, 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode. During the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals applied to the corresponding inputs Oo-Yuz from the outputs of the multiplexer, which are determined by the values of the signals at its inputs of the second group (0010), forming a single value at the output of the generator.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the unit state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 7, 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode.

During the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals applied to the corresponding inputs Оо-ХОз from the outputs of the multiplexer, which are determined by the values of the signals at its inputs of the second group (1001), and trigger 2 will go to the zero state. During the arrival of further clock pulses, the content of counter 1 will decrease, and the state of flip-flop 2 remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 7, 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode.

In the future, the processes are repeated. Thus, after the end of the transient process associated with the removal of blocking, during input C of the generator of a periodic sequence of pulses with a period T, a periodic sequence of pulses is generated at the direct output of trigger 2, the duration of which is equal to two periods of clock pulses (supplied to the input shaper from the output of an external quartz generator), and the duration of the pause is equal to 9T, with a programmable delay relative to the start pulse, which is determined by the value of the programming signals B-brzbrgbribo.

The process of forming the output sequence of pulses is stopped by applying a pulse corresponding to the logical zero level to the stop input (Stor), which forms an active signal level at input A of the asynchronous unit of the Y-trigger Z, which leads to its transition to the zero state (0-0 ). The OR pulse is, as a rule, asynchronous with respect to the pulses of the external generator and to the state of trigger 2.

If flip-flop 2 is in the zero state at the time of the arrival of the clock pulse, then when the SW flip-flop З goes to the zero state, a logical 0 level will be formed at the inputs of element b and its output, causing a logical zero level at the input and output of element 5, which will lead to transition of counter 1 to the zero state, and therefore to the termination of the generation process.

If, at the moment of the transition, trigger 2 is in a state other than zero, then the output of the shaper connected to the input of element 6 will have a level of logic one, determining the level of a logic unit at its output and the input of element 5. Since at the second input of element 5 also the level of a logical unit, determined by the voltage on capacitor 12, which was charged when the power source was turned on, then there will be a level of a logical unit at the inputs of the IR counter and trigger 2. It follows from this that at the moment of the introduction of the pulse 5ior, the termination of the generation will not happen, thereby determining the prevention of distortion of the last pulse in the output sequence. And only with the introduction of further clock pulses, when the transition of trigger 2 to the zero state will occur at the inputs of element b and its output, a level of logical 0 will be formed, causing a level of logical zero at the input and output of element 5, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the generation process. With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the transition graph of the shaper consisting of two rings (the upper ring is the transition graph of counter 1, the lower ring is the transition graph of trigger 2) with a common vertex corresponding to the zero state of the counter and trigger 2, and in Fig. C shows the graphs illustrating the operation for the option of setting the generator to a duration of pulses equal to 2T, a pause between them equal to 9 and programming the duration of the delay (iZ) of the beginning of the formation of pulses at the output relative to the start pulse, which is determined by the value

V-rzb2riro-0011-3. Since the start pulses are asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range: ЗТ "Из" 4T.

In contrast to the analogue, the simplification of the structure of the second counter made it possible to simplify

From the technology of its manufacture, to reduce the power consumption and cost.

Claims (1)

USEFUL MODEL FORMULA A periodic sequence generator with adjustable pulse duration and pause and programmable delay of the start of the formation relative to the start pulse, containing two binary counters, the first of which is reversible, configured for subtraction mode, having a synchronization pulse supply input, a synchronous parallel loading enable input and input of data supply during loading, input of permission of counting mode, input of asynchronous installation in the zero state, overflow output; inverter; a circuit consisting of a series-connected resistor and capacitor connected to a power source; start-stop device, which contains a synchronous O-trigger with an input of an asynchronous unit in the zero state, the first and second two-input elements I; the first, second and third OR elements, while the first input of the first OR element is connected to the output of the SW flip-flop; the output of the first OR element is connected to the first input of the second AND element; the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with one input of the first and the second input of the second element I; the output of the first element I is connected to the input of the asynchronous installation of the Y-trigger in the zero state; output of the second element | connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses, which differs in that a unidirectional multiplexer is introduced, and the second counter is made of a single bit (the second O-flip-flop with the input of enabling the I transition and the input of the asynchronous installation in the zero state); the first group of multiplexer inputs forms inputs for programming the shaper for a given duration of the delay of the start of the formation of a periodic sequence with a reconfigurable duration of pulses and pauses relative to the start pulse, the second group of multiplexer inputs forms inputs for setting the shaper for a given duration of pulses and pauses at the output; the outputs of the multiplexer are connected to the inputs of the parallel loading of the first counter; at the same time, when setting to form a sequence of pulses with a duration equal to the period of clock pulses supplied to the input of the shaper from the output of an external quartz oscillator, and the duration of the pause is equal to nine periods of clock pulses, the first input of the second group of multiplexer inputs is connected to by the level of a logical unit, the second and third inputs of the second group of inputs of the multiplexer are connected to the level of logical zero, the fourth input of the second group of inputs of the multiplexer is connected to the second input of the first OR element and to the direct output of the second SW flip-flop, the address input of the multiplexer is connected with the overflow output of the first counter and the input of the inverter, the output of which is connected to the first input of the second OR element; the output of the second OR element is connected to the transition permission input of the second counter (its input of the second U-trigger); the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element, the output of which is connected to the second input of the second OR element and the input of allowing synchronous loading of the first counter. I S her prh og ZK shchi a mk Es Z i Y mk Ti t KI I E I A-TACHGI t j! ate Vishnu about Z Y Fig. 1 Fig. 2