UA136345U - TRIKANAL SERIES FORMER WITH ADJUSTABLE DURATION AND NUMBER OF PULSES IN CHANNELS AND DELAY OF BEGINNING OF RELATIONSHIP RELATIONSHIP - Google Patents

Abstract

The shaper of the three-channel series with the reconfigured number and duration of pulses in channels and a delay of the beginning of formation concerning a starting pulse contains two counters, the first reversible binary counter is adjusted to a subtraction mode, has an input digit mode resolution, asynchronous setup input to zero state, bit outputs, overflow output; start-up device, which contains a trigger with the inputs of the asynchronous installation to zero and one state, a circuit consisting of a series-connected resistor and a capacitor connected to a power supply; the first, second, third, fourth and fifth elements of I; the first and second elements OR; first and second inverters; XOR element. Introduced three-input element OR, the inputs of which are connected to the outputs of the second, third and fourth digits of the first counter, the output - with the input of the download permission of the first counter and the first input of the second element OR; the second counter is a three-bit cyclic device with a sequence of transitions 000-001-011-111-110-100, made on three synchronous D-flip-flops with input inputs of clock pulses.

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a three-channel series with adjustable duration and number of pulses in the channels and the delay of the start of formation relative to the starting pulse.

There are known shapers that contain a quartz setting generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses fed to the input |Yu. V. Novikov Fundamentals of digital technology. - M.: MIR, 2001, Fig. 5.13-5.18.

The disadvantage of known devices is the complexity of the internal structure.

A well-known generator containing two typical reversible binary counters configured for the subtraction mode, a two-digit counter made of K-triggers, a start-stop device made of a synchronous SW-trigger (patent of Ukraine for utility model Mo 652511.

The disadvantage of the known device is the complexity of the structure and limited functionality.

The closest in terms of technical essence and the result achieved is a three-channel series generator with adjustable number and duration of pulses in the channels and a delay of the start of formation relative to the start pulse (patent of Ukraine for a useful model Mo 65276), which contains two reversible binary counters configured for the mode subtraction, each of which has a sync pulse supply input, a synchronous parallel load enable input and a load data supply inputs, a count mode enable input, an asynchronous reset input to the zero state (while an active signal at the synchronous parallel load enable input has priority over of the active signal at the input of the digital mode permission, and the active signal at the input of the asynchronous installation in the zero state has priority in relation to the active signal at the input of the permission of synchronous parallel loading and at the input of the permission of the digital mode), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; HORN element, parallel inputs

From the loading of the first counter, the tuning inputs of the shaper for the given parameters of the output pulses are formed; the clock inputs of the first counter form the input of the shaper - the input of the supply of a periodic sequence of pulses 3 of the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first element OR is connected to the input of the second element AND!; output of the second element I! connected to the input of the asynchronous installation of the first counter in the zero state; the inverse overflow output of the first counter is connected to the input of the first inverter; the first entry of the element

The HOV is connected to the input of the shaper, the second input of the HOV element forms the input for adjusting the shaper for the given duration of pulses, the output of the HOV element is connected to the first inputs of the third, fourth and fifth elements of Y.

The disadvantage of this device is the complexity of the internal structure and limited functionality.

The useful model is based on the task of expanding the functionality and simplifying the internal structure of the former.

The task is solved by the fact that in a three-channel series generator with adjustable number and duration of pulses in the channels and a delay of the start of formation relative to the start pulse, which contains two counters, the first reversible binary counter is configured for subtraction mode, has an input for supplying synchronization pulses, an input for enabling synchronous parallel download and data input inputs during download, digit mode enable input, asynchronous setup input to zero state (at the same time, the active signal at the synchronous parallel download enable input has priority in relation to the active signal at the digital mode enable input, and the active signal at the asynchronous setup input in the zero state has priority in relation to the active signal at the synchronous parallel loading enable input and at the digit mode enable input), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; 60 element of HOV; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the first counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of the second element AND is connected to the input of the asynchronous counter installation in the zero state; the inverse overflow output of the counter is connected to the input of the first inverter; to the first inputs of the third, fourth and fifth elements AND, the output of the XOV element is connected, the second input of which forms the input of adjusting the shaper for the given duration of pulses, according to the useful model, a three-input OR element is introduced, the inputs of which are connected to the outputs of the second, third and the fourth digits of the first counter, the output - with the input of the permission to load the first counter and the first input of the second OR element; the second counter is a three-bit cyclic device with a sequence of transitions 000-001-011-111-110-100, made on three synchronous U-flip-flops with inputs for supplying clock pulses, an input for allowing synchronous loading (transition), inputs for asynchronous setting to the zero state, inputs loading, input of asynchronous setting of zero; the load input of the first SW-trigger is connected to the inverse output of the third SW-trigger, the load input of the second SW-trigger is connected to the direct output of the first SW-trigger, the load input of the third

The SW-trigger is connected to the direct output of the second SW-trigger; the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input of the second counter; the output of the third digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element I; the loading inputs of the first counter are connected to its inverse or direct overflow output or to the logical zero or one level; the output of the third element AND forms the output of the first channel

K1; the output of the fourth element I forms the output of the second channel K2; the output of the fifth element forms the output of the third short circuit channel; if the number of pulses of the first and second channels is six, the number of pulses of the third channel is three with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, the first input

From synchronous parallel loading, the first counter is connected to the inverse output of the overflow of the first counter, the second - to the level of logical one, the third - to the level of logical zero, the fourth - to the direct output of overflow (with the output of the first inverter); the second and third inputs of the third element And are connected to the direct output of the first digit and the inverse output of the second digit of the second counter; the second and third inputs of the fourth element are connected to the direct outputs of the first and second digits of the digits of the second counter; the second and third inputs of the fifth element AND are connected to the direct output of the third and the inverse output of the first digit of the second counter.

In fig. 1 shows a diagram of the former, in fig. 2 - graph of transitions of the shaper, in fig. C - graphs illustrating the work for a given configuration option (Ро Ра рі-1, 02-0,

Oz-Ra).

The generator contains the first 1 and the second binary counters, the counter 1 is a reversible four-bit, configured for the subtraction mode, which has an input for supplying synchronization pulses C, an input for enabling synchronous parallel loading I! and inputs of data supply during loading (О0о-ЖОз), the input of the permission of the counting mode E, the input of the asynchronous installation in the zero state B, the outputs of the digits (00-Сз,), the overflow output Ры; the second three-bit counter with the sequence of transitions 000-001-011-111-110-100 (Johnson counter), made on three synchronous SW flip-flops 2, 3, 4 with inputs for supplying clock pulses C, inputs I for enabling synchronous loading (transition), loading inputs (00-02), inputs of the asynchronous installation in the zero state EN, the start-stop device on the asynchronous H5-trigger 5; the first 6, the second 7, the third 8, the fourth 9 and the fifth 10 elements of I; the first 11 and the second 13 two-input OR elements; three-input element OR 12; element XO 14; the first 15 and the second 16 inverters; connected to the power source, the resistor 17 and the capacitor 18 are connected in series.

The common point of series-connected resistor 17 and capacitor 18 is connected to the first inputs of elements 6, 7. The second input of element b is connected to the output of inverter 16. The output of element 6 is connected to the input of the installation in the zero state of No-trigger 5. The second the input of element 7 is connected to the output of element 11, the first input of which is connected to the output of No-trigger 5, and the second - to the output of the third digit 02 of the second counter. The output of element 7 is connected to input B to set the counters to zero. The inputs of the element 12 are connected to the outputs of the second C, 60 of the third 0" and the fourth Oz of the digits of the first counter; the overflow output of the first counter P4 is connected to the input of the inverter 15, the output of which is connected to the first input of element 13; the second input of element 13 is connected to the output of element 11. The output of element 13 is connected to the enable inputs of the second counter transition mode (inputs of IO flip-flops). The output of the third digit 02 of the second counter is connected to the input of the inverter 16, the output of which is connected to the second input of element 6.

The clock inputs C of the counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator,

Tuning the shaper to form a single three-channel series with given parameters (pulse duration, the number of pulses of the first, second and third channels and the duration of the delay of the start of formation relative to the start pulse) is ensured by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the level logical zero or one depending on the set values of these parameters. When setting the shaper to form a single three-channel series, the pulse duration of which is equal to the duration of the clock pulses, the control input of the M element

HOB 14 is connected to the level of logic 0, if the duration of the pulses is equal to the duration of the pause between clock pulses, the control input M of the element of HOB 14 is connected to the level of a logical unit.

If the number of pulses of the first channel is equal to three (pi-3) clock pulses fed to the input of the shaper from the output of the external generator, the number of pulses of the second and third channels is equal to six (p2-pz-6b), with a delay of the start of the formation relative to the start pulse, which is equal to ten periods (8-10T), the first input Oo of the synchronous parallel loading of the First counter is connected to the inverse overflow output

Ra of the first counter; second input 0; the load is connected to the level of logic one, the third input O2 is connected to the level of logic zero, the fourth input Oz of the load is connected to the direct overflow output (output of the first inverter) (Oo-Ra, 0-1, 02-0, Oz -Ra). The output of element 8 forms the output of the first channel of the unit series: K1- o 8008 (UVS). The output of element 9 forms the output of the second channel of the unit series: К2О2:О145008 (МФО). The output of element 10 forms the output of the third channel of the unit series: K3-O O8O28 (US).

The presence of a circuit consisting of a resistor 17 and a capacitor 18 connected in series, connected to the supply voltage bus 4-E, when the power source is turned on during

For a certain period of time, a logical zero level is formed at the inputs of elements 6 and 7, ensuring the formation of a logical zero level at their outputs, that is, at the inputs of the asynchronous installation in the zero state of the JK trigger and counters. After the end of the capacitor charge, the unit value at the first inputs of elements 6, 7 remains unchanged.

After the end of the transient process associated with turning on the power source, the counters and the trigger go to the zero state, forming: a logical zero level at the overflow output of counter 1, at the Oo-Oz outputs at the output of element 12, the signal value at which is equal to the logical sum of the signals from the outputs C, C», Oz (1-01 m O»2 m Oz), at the output of element 11, which is connected to the input of element 7, which provides a logical zero level at the inputs B of the asynchronous installation in the zero state of the counters and after the end of the transient process associated with the charge of capacitor 18. While the mode of asynchronous setting of the counters to the zero state has priority over all the last modes, until then the logical zero level will be maintained at the inputs of element 11, when clock pulses arrive, the zero state of the first and second of counters will remain unchanged, that is, the zero value at the outputs of the generator will also remain unchanged.

During the arrival of the trigger pulse eiai at the input 5 of the flip-flop 5, the flip-flop goes into a single state, forming the level of a logical unit at its output (0-1), the output of element 11, and therefore at the input and output of element 7, which provides a level of logical unit at inputs A of the first 1 and second counters, removing the blocking of the zero state. Since there is a logical zero level at the Y input of counter 1, and a logical one level at the I input of the second counter, until the arrival of the next clock pulse, counter 1 is in the loading readiness mode, and the second counter is in the transition prohibition mode.

During the entry of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is parallel loaded with the values of the signals generated at its inputs of parallel loading Oz020100-1010. Counter 1 goes into state О3020100-1010-10, which leads to the formation of a single value at the overflow output of counter 1, a single value at the output of elements 12, 13, at the input I of the counters, i.e. prohibiting the loading of counters and allowing the counting (subtraction) mode of counter 1 During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of the second counter will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 12, 13. As a result, the first counter 1 again switches to the download mode, and the second - to the transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals at their inputs ЮОз020100-0010. Counter 1 goes into state Oz3020100-0010-2. The second counter will go to the next state 020100-001-1, starting the formation of the first pulse at the CI output. In the future, the processes are similar, that is, every time, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 12, 13. As a result, counter 1 goes into loading mode, and the second counter goes into transition mode. Pulses at the output of K2 are formed in the states: 011, 111. At the same time, as soon as the content of the second counter becomes equal to 111, a zero value is formed at the output of the inverter 16 and the input A of the trigger 5, which leads to the transition of the trigger to the zero state (0-0). Pulses at the output of the short circuit are formed in the following states: 100, 100. In the future, as soon as the content of counter 1 becomes equal to 0001, then during the arrival of the next clock pulse, the transition of the second counter to the zero state occurs, forming a zero value at the output of elements 11,7, which will lead to the transition to the zero state of the first counter, and therefore to the termination of the formation process.

With the arrival of the next start pulse, all processes are repeated.

In contrast to the known, the proposed former has a simplified internal structure and expanded functionality.

Claims (1)

USEFUL MODEL FORMULA A three-channel series generator with adjustable number and duration of pulses in the channels and a delay of the start of the formation relative to the start pulse, containing two counters, the first reversible binary counter configured for subtraction mode, has a synchronization pulse supply input, a synchronous parallel loading enable input and supply inputs data during download, the input of the digital mode permission, the input of the asynchronous installation in the zero state (at the same time, the active signal at the input of the permission of synchronous parallel loading has priority in relation to the active signal at the input of the permission of the digital mode, and the active signal at the input of the asynchronous installation in the zero state has priority in relation to the active signal at the synchronous parallel loading enable input and at the digital mode enable input), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; CHOR element; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the first counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of the second element AND is connected to the input of the asynchronous counter installation in the zero state; the inverse overflow output of the counter is connected to the input of the first inverter; with the first inputs of the third, fourth and fifth elements AND, the output of the XOV element is connected, the second input of which forms the input of adjusting the shaper for the given duration of pulses, which differs in that a three-input OR element is introduced, the inputs of which are connected to the outputs of the second, the third and fourth digits of the first counter, the output - with the input of the permission to load the first counter and the first input of the second OR element; the second counter is a three-bit cyclic device with a sequence of transitions 000-001-011-111-110-100, made on three synchronous SW flip-flops with inputs for supplying clock pulses, an input for allowing synchronous loading (transition), inputs for asynchronous setting to the zero state, inputs loading, input of asynchronous setting of zero; the load input of the first O-flip-flop is connected to the inverse output of the third U-flip-flop, the load input of the second O-flip-flop is connected to the direct output of the first U-flip-flop, the load input of the third U-flip-flop is connected to the direct output of the second O-flip-flop ; the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input 60 of the second counter; the output of the third digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element I; the loading inputs of the first counter are connected to its inverse or direct overflow output or to the logical zero or one level; the output of the third element AND forms the output of the first CI channel; the output of the fourth element I forms the output of the second channel Kg; the output of the fifth element I forms the output of the third short-circuit channel; if the number of pulses of the first and second channels is six, the number of pulses of the third channel is three with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, the first input of the synchronous parallel loading of the first counter is connected to the inverse overflow output of the first counter, the second - with a level of logical one, the third - with a level of logical zero, the fourth - with a direct overflow output (with the output of the first inverter); the second and third inputs of the third element And are connected to the direct output of the first digit and the inverse output of the second digit of the second counter; the second and third inputs of the fourth element are connected to the direct outputs of the first and second digits of the digits of the second counter; the second and third inputs of the fifth element AND are connected to the direct output of the third and the inverse output of the first digit of the second counter. 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