UA132974U - THREE-TANNER SERIES SHAPTER WITH ADJUSTED DURATION AND NUMBER OF PULSES IN CHANNELS AND DELAYED START FORMATION AFTER STARTING - Google Patents

Abstract

Shaper three-channel series with adjustable number and duration of pulses in the channels and delayed start of the formation relative to the starting pulse has two counters, the first reversible binary counter is tuned to the subtraction mode, has a pulse input input synchronous input and input load synchronous input digital mode resolution, asynchronous zero input, with the active signal at the input of the synchronous parallel load permissions has priorities Theta relative to the active signal at the input of digital mode resolution. The active signal at the input of the asynchronous zero setting takes precedence over the active signal at the synchronous parallel boot resolution input and the digital mode resolution input. Additionally, a three-input OR element is input, the inputs of which are connected to the outputs of the second, third and fourth digits of the first counter, the output - to the input of the first counter loading load and the first input of the second OR element.

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a three-channel series with adjustable duration and number of pulses in the channels and the delay of the start of formation relative to the starting pulse.

There are well-known shapers that contain a quartz setting generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y. V. Novikov Fundamentals of digital technology, M "MIR" 2001, Fig. 5.13-5.18).

The disadvantage of known devices is the complexity of the internal structure.

A well-known shaper containing two typical reversible binary counters configured for subtraction mode, a two-digit counter made on "K-flip-flops, a start-stop device made on a synchronous O-flip-flop (patent of Ukraine for utility model Mob5251). The disadvantage of the known device is the complexity of the structure and limited functionality.

The closest analogue is a three-channel series generator with adjustable number and duration of pulses in the channels and a delay in the start of formation relative to the start pulse (patent of Ukraine for a useful model Mob65276), which contains two reversible binary counters configured for subtraction mode, each of which has an input for supplying synchronization pulses , the synchronous parallel loading enable input and data feed inputs during loading, the count mode enable input, the asynchronous setting input in the zero state (while the active signal at the synchronous parallel load enable input has priority over the active signal at the count mode enable input, and the active signal at the input of the asynchronous installation in the zero state has priority relative to the active signal at the input of the permission of synchronous parallel loading and at the input of the permission of the digital mode), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one states, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; the HOV element, the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; clock inputs of the first

From the counter, the input of the shaper is formed - the input of the supply of a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; output of the second element | connected to the input of the asynchronous installation of the first counter in the zero state; the inverse overflow output of the first counter is connected to the input of the first inverter; the first input of the HOMV element is connected to the input of the shaper, the second input of the HOMK element forms the input for adjusting the shaper for the given duration of pulses, the output of the HOV element is connected to the first inputs of the third, fourth and fifth elements of I.

The disadvantage of this device is the complexity of the internal structure and limited functionality.

The basis of the useful model is the task of expanding the functional capabilities due to the introduction of a delay in the start of formation relative to the starting pulse and simplification of the internal structure of the former.

The task is solved by the fact that the three-channel series generator with adjustable number and duration of pulses in the channels and the delay of the start of formation relative to the start pulse, containing two counters, the first reversible binary counter is configured for subtraction mode, has an input for supplying synchronization pulses, an input for enabling synchronous parallel download and data feed inputs during download, digit mode enable input, asynchronous device input to zero state (at the same time, the active signal at the synchronous parallel download enable input has priority relative to the active signal at the digital mode enable input, and the active signal at the asynchronous device input in the zero state has priority relative to the active signal at the synchronous parallel loading enable input and at the digit mode enable input), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; 60 element HOV, the inputs of the parallel load of the counter form the inputs of tuning the shaper to the given parameters of the output pulses; clock inputs of the counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of the second element is connected to the input of the asynchronous installation of the counter in the zero state; the inverse overflow output of the counter is connected to the input of the first inverter; to the first inputs of the third, fourth and fifth elements AND, the output of the XOV element is connected, the second input of which forms the input for adjusting the shaper to the given duration of pulses according to the useful model, a three-input OR element is introduced, the inputs of which are connected to the outputs of the second, third and the fourth digit of the first counter, the output - with the input of the permission to load the first counter and the first input of the second OR element; the second counter is a three-bit cyclic device with a sequence of transitions 000-001-011-111-110-100, made on three synchronous O-triggers with inputs for supplying clock pulses, an input for allowing synchronous loading (transition), inputs for asynchronous setting to the zero state, inputs loading, input of asynchronous setting of zero; the loading input of the first SW flip-flop is connected to the inverse output of the third SW flip-flop, the loading input of the second SW flip-flop is connected to the direct output of the first SW flip-flop, the load input of the third SW flip-flop is connected to the direct output of the second

SW-trigger; the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input of the second counter; the output of the third digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element AND, the loading inputs of the first counter are connected to its inverse or direct overflow output or to the level of logic zero or one; the output of the third element I forms the output of the first channel K1; output of the fourth element | forms the output of the second channel K2; the output of the fifth element I forms the output of the third short-circuit channel; if the number of pulses of the first channel is nine, the number of pulses of the second and third channels is three with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, the first input of the synchronous

From the parallel loading of the first counter, it is connected to the inverse output of the overflow of the first counter, the second - to the level of logical one, the third - to the level of logical zero, the fourth - to the direct output of overflow (with the output of the first inverter); the second input of the third element And is connected to the direct output of the first digit of the second counter; the second and third inputs of the fourth element AND! connected to the direct output of the second and the inverse output of the first digit of the second counter; the second and third inputs of the fifth element AND! connected to the direct output of the third and inverse output of the second digit of the second counter.

In fig. 1 shows a diagram of the former, in fig. 2 - graph of transitions of the shaper, in fig. Z - graphs explaining the operation for a given configuration option (Ro also "01-1, ОЮ2-0, Oz-Ra).

The shaper contains two counters, the first counter 1 is a reversible four-bit, configured for the subtraction mode, which has an input for supplying synchronization pulses C, an input for enabling synchronous parallel loading GI and inputs for supplying data when loading Yuo-Yuz, an input for enabling the counting mode E, an input for asynchronous installation in zero state B, outputs of Xu-Oz discharges, output of overflow P. ; the second three-bit counter with the sequence of transitions 000-001-011-111-110-100 (Johnson's counter), made on three synchronous O-flip-flops 2, 3, 4 with inputs for supplying clock pulses C, inputs GI. permission of synchronous loading (transition), loading inputs Oo-O2, inputs of asynchronous installation in zero state H, start-stop device on asynchronous H5-trigger 5; the first 6, the second 7, the third 8, the fourth 9 and the fifth 10 elements of I; the first 11 and the second 13 two-input OR elements; three-input element OR 12; element XO 14; the first 15 and the second 16 inverters; resistor 17 and capacitor 18 are connected in series to the same power source.

The common point of series-connected resistor 17 and capacitor 18 is connected to the first inputs of elements 6, 7. The second input of element b is connected to the output of inverter 16. The output of element 6 is connected to the input of the installation in the zero state of No-trigger 5. The second the input of element 7 is connected to the output of element 11, the first input of which is connected to the output of No-trigger 5, and the second - to the output of the third digit 02 of the second counter. The output of element 7 is connected to input B to set the counters to zero. The inputs of element 12 are connected to the outputs of the second C, the third O2 and the fourth Oz of the digits of the first counter; the overflow output of the first RA counter is connected to the input of the inverter 15, the output of which is connected to the first input of the element

13; the second input of the element 13 is connected to the output of the element 11. The output of the element 13 is connected to the AND inputs of the transition mode permission of the second counter (O-triggers). The output of the third digit 02 of the second counter is connected to the input of the inverter 16, the output of which is connected to the second input of element 6.

The clock inputs C of the counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator. Inputs E of the counters form the input of the asynchronous device of the generator in the zero state.

Tuning the shaper to form a single three-channel series with given parameters (pulse duration, the number of pulses of the first, second and third channels and the duration of the delay of the start of formation relative to the start pulse) is ensured by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the level logical zero or one depending on the set values of these parameters. When setting the shaper to form a single three-channel series, the pulse duration of which is equal to the duration of the clock pulses, the control input of the M element

HOB 14 is connected to the level of logic 0, if the duration of the pulses is equal to the duration of the pause between clock pulses, the control input M of the element of HOB 14 is connected to the level of a logical unit.

If the number of pulses of the first channel is equal to nine (pi-9) clock pulses fed to the input of the shaper from the output of the external quartz generator, the number of pulses of the second and third channels is equal to three (p2-pz-3), the delay of the start of the formation is relatively of the starting pulse is equal to ten periods (iIzZ-107), the first input (Oso) of the synchronous parallel loading of the first counter is connected to the inverse overflow output

R. of the first counter; the second input O: the load is connected to the level of a logical unit, the third input O2 is connected to the level of logical zero, the fourth input UOz of the load is connected to the output of the first inverter (Oo-Re "01-1, U2-0, Oz- Ra). The output of element 8 forms the output of the first channel of the unit series: k1-918 00 8 (M b C). The output of element 9 forms the output of the second channel of the unit series: K2-O018(M is C). The output of element 10 forms the output of the third channel of the unit series: KZ- 9 1 8. 028. (MES).

The presence of a circuit consisting of a resistor 17 and a capacitor 18 connected in series, connected to the supply voltage bus 4-E, when the power source is turned on during

For a certain period of time, a logical zero level is formed at the inputs of elements 6 and 7, ensuring the formation of a logical zero level at their outputs, that is, at the inputs of the asynchronous unit in the zero state of the trigger and counters. After the capacitor is charged, the unit value at the first inputs of elements 6, 7 remains unchanged.

After the end of the transient process associated with turning on the power source, the counters and the trigger go to the zero state, forming: the level of logical zero at the overflow output of counter 1, at the outputs Oo-Oz, at the output of element 10, the signal value at which is equal to the logical sum of signals from the outputs C, C», Oz (1-01 m O» m Oz), at the output of element 11, which is connected to the input of element 7, which provides a logical zero level at the inputs B of the asynchronous unit to the zero state of the counters and at the end of the transient process associated with the charge of capacitor 18. While the mode of asynchronous setting of the counters to the zero state has priority over all the last modes, as long as the logic zero level is maintained at the inputs of element 11, when clock pulses arrive, the zero state of the first and second counters will remain unchanged, that is, the zero value at the outputs of the shaper will also remain unchanged.

During the arrival of the trigger pulse (5iagp) at the input 5 of the flip-flop 5, the flip-flop goes into a single state, forming the level of a logical unit at its output (0-1), the output of element 11, and therefore at the input and output of element 7, which provides a level of logical unit on the inputs A of the first 1 and second counters, removing the blocking of the zero state. Since at the entrance | counter 1 has a level of logical zero, and the input I of the second counter has a level of logical one, then until the arrival of the next clock pulse, counter 1 is in the loading readiness mode, and the second counter is in the transition prohibition mode.

During the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at its parallel loading inputs

O3020100-1010. Counter 1 goes to the state О3020:00-1010-10 (ten), which leads to the formation of a single value at the overflow output of counter 1, a single value at the output of elements 12, 13, at the input I of counter 1, i.e. the prohibition of loading counters, enabling the mode counts (subtraction) of counter 1. During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of the second counter will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 12, 13. As a result, the first counter 1 again switches to the download mode, and the second - to the transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals at their inputs ЮОз0201О0-0011. Counter 1 goes into state Oz020100-0011-3. The second counter will go to the next state Oz3020100-0001-1, starting the formation of the first pulse at the output of K1. Pulses at the output of the CI are formed in states 001, 011, 111. At the same time, as soon as the content of counter 1 becomes equal to 111, a zero value is formed at the output of the inverter 16 and input A of the trigger 5, which leads to the transition of the trigger to the zero state (0-0). In the future, the processes are similar, that is, every time, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 12, 13. As a result, the first counter 1 goes into the loading mode, and the second - into the transition mode to the next state. Pulses at the output of K2 are formed in state 110. Pulses at the output of KZ are formed in state 100.

In the future, again, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 12, 13, the second counter goes into the transition permission mode. And then during the onset of the next clock pulse, the transition of the second counter to the zero state occurs, forming a zero value at the output of elements 11,7, which will lead to the transition to the zero state of the first counter, and therefore to the termination of the formation process. With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the transition graph of the shaper consisting of five rings, the upper (first) ring is the transition graph of counter 1, the second is the transition graph of the second counter, the third is the value of the signals at the output of KI, the fourth is the value of the signals at the output of K2, p' yate - the value of the signals at the output of the short circuit, with a common peak corresponding to the zero state of the counters, and in Fig. C shows the graphs that explain the work for a given configuration option (Vo Shchi Ra ri-1, OYU2-0, Oz-R.a) for the formation of a three-channel series with adjustable duration, the number of pulses in the channels and the delay of the start of formation relative to the starting pulse. Since the start pulses are asynchronous relative to the clock pulses, the duration of the delay of the start of formation is in the range: 10Т«из«11Тт.

In contrast to the known, the proposed former has a simplified internal structure and expanded functionality.

Claims (1)

USEFUL MODEL FORMULA A three-channel series generator with adjustable number and duration of pulses in the channels and a delay of the start of the formation relative to the start pulse, containing two counters, the first reversible binary counter configured for subtraction mode, has a synchronization pulse supply input, a synchronous parallel loading enable input and supply inputs data during download, the input of the digital mode enable, the input of the asynchronous installation in the zero state (at the same time, the active signal at the input of the synchronous parallel loading permission has priority over the active signal at the input of the digital mode enable, and the active signal at the input of the asynchronous installation in the zero state has priority relative to the active signal at the synchronous parallel loading enable input and at the digital mode enable input), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one states, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; HOV element; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the first counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of the second element AND is connected to the input of the asynchronous counter installation in the zero state; the inverse overflow output of the counter is connected to the input of the first inverter; with the first inputs of the third, fourth and fifth elements AND, the output of the XOV element is connected, the second input of which forms the input of adjusting the shaper for the given duration of pulses, which differs in that a three-input OR element is introduced, the inputs of which are connected 60 with the outputs of the second , the third and fourth digits of the first counter, output - 3 input of the permission to load the first counter and the first input of the second OR element; the second counter is a three-bit cyclic device with a sequence of transitions 000-001-011-111-110-100, made on three synchronous SW flip-flops with inputs for supplying clock pulses, an input for allowing synchronous loading (transition), inputs for asynchronous setting to the zero state, inputs loading, input of asynchronous setting of zero; the load input of the first O-flip-flop is connected to the inverse output of the third U-flip-flop, the load input of the second O-flip-flop is connected to the direct output of the first U-flip-flop, the load input of the third U-flip-flop is connected to the direct output of the second O-flip-flop ; the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input of the second counter; the output of the third digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element AND, the loading inputs of the first counter are connected to its inverse or direct overflow output or to the level of logic zero or one; the output of the third element AND forms the output of the first CI channel; the output of the fourth element I forms the output of the second channel Kg; the output of the fifth element I forms the output of the third short-circuit channel; if the number of pulses of the first channel is nine, the number of pulses of the second and third channels is three with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, the first input of the synchronous parallel loading of the first counter is connected to the inverse overflow output of the first of the counter, the second - with a level of logical one, the third - with a level of logical zero, the fourth - with a direct overflow output (with the output of the first inverter); the second input of the third element 1 is connected to the direct output of the first digit of the second counter; the second and third inputs of the fourth element AND! connected to the direct output of the second and the inverse output of the first digit of the second counter; the second and third inputs of the fifth element AND are connected to the direct output of the third and the inverse output of the second digit of the second counter. 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