UA127948U - DUAL-PHASE PULSE CONVERTER WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

The two-phase pulse generator with reconfigured time parameters contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has a pulse input pulse output, overflow output, synchronous parallel load resolution input and digital input inputs asynchronous setting input to zero state (thus, the active signal at the input of the synchronous parallel load resolution has priority over the active signal and the entrance permit counting mode and active asynchronous signal at the input settings in the zero state has priority with respect to the active input signal permits simultaneous parallel load and inlet mode permits counting); a starter device comprising a trigger with zero input asynchronous installation and a circuit consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements I; the first and second elements OR. Additionally introduced the third and fourth elements And, the startup device is made on an asynchronous RS-trigger, and instead of the second four-digit counter introduced a two-bit subtraction counter with a sequence of transitions 00-11-10-01-00, made on two JK-triggers with input zero setting; the first JK trigger has inverted inputs J and K; the second JK-flip-flop has inverted and direct inputs J and K, which are combined along I; the inverse inputs of the JK triggers are connected to the output of the second element OR and the input of the synchronous parallel load of the first counter; the direct inputs J and K of the second JK trigger are connected to the inverse output of the first JK trigger; the direct output of the first JK trigger is connected to the first inputs of the third and fourth elements I, with the second input of the first element OR, with the third input of the loading of the first counter; the direct output of the second JK trigger is connected to the second input of the fourth element I, the third input of the first element OR; the first load input of the first counter is connected to the logic unit level, the fourth load inputs of the first counter are connected to the inverse output of the first JK trigger, the second load input is connected to the logic zero level; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second element OR; the clock inputs of the first and second counters form the input of the shaper - the input of the filing of a periodic pulse sequence from the output of an external generator; the input of the asynchronous installation in a single state of the RS-trigger forms the input of the pulse startup; the output of the third element I forms the output of the first phase (F1), and the output of the fourth element I forms the output of the second phase (F2) of the pulses.

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a two-phase sequence of pulses with reconfigurable time parameters.

There are known shapers that contain a quartz reference generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Osnovyi! digital technology. - M.: "MIR", 2001 - Fig. 5.13-5.181.

The disadvantage of known devices is the complexity of the internal structure.

Known generators of a periodic multiphase sequence of pulses with reconfigurable time parameters (Ukraine patents for the invention Mo Mo 87081, 89240, 106091, 106395, 10807, 106867, 10888, 106091, 1070281.

The disadvantage of the devices is the complexity of the structure, due to the need to use two multi-bit binary counters, decoders.

The closest analog in terms of technical essence and the result achieved is the selected two-phase pulse sequence generator with reconfigurable time parameters (Ukraine patent for utility model 63193), which contains two binary counters, the first of which is reversible, configured for subtraction mode, which has a pulse supply input synchronization, synchronous parallel download permission input and data feed inputs during download, digit mode permission input, asynchronous installation input to zero state, overflow output; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; first and second elements

OR, while the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the first AND element; the output of the first element is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of this device is the complexity of the generator circuit, which is due to the construction of a start-stop device on a synchronous O-trigger and the use of a second four-digit counter and, as a result, high power consumption and high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that the generator of a two-phase sequence of pulses with reconfigurable time parameters, containing two binary counters, the first of which is reversible, configured for the subtraction mode, having an input for supplying synchronization pulses, an overflow output, an input for enabling synchronous parallel loading and inputs for data supply during loading, the enable input of the digital mode, the input of the asynchronous installation in the zero state (in this case, the active signal on the enable input of the synchronous parallel loading has priority in relation to the active signal on the enable input of the digital mode, and the active signal on the input of the asynchronous installation in the zero state has priority in relation to the active signal at the synchronous parallel download enable input and at the digital mode enable input); a start-stop device containing a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and capacitor connected to a power source; the first and second elements of I; the first and second OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the second input of the first element forms the input of the supply of pulses to stop the formation of output pulses; the output of the first element is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the second AND element; output of the second element I! connected to the inputs of the asynchronous installation in the zero state of the first and second counters, according to the useful model, the third and fourth elements of I are introduced, while the start-stop device is made on an asynchronous H5 flip-flop, and instead of the second four-digit counter, a two-digit subtractive counter with a sequence of transitions 00 is introduced -11-10-01-00, executed on two OK-triggers with the input of the asynchronous installation in the zero state; the first CC-trigger has inverse inputs .// and K; the second UC-trigger has inverse and direct inputs y and K, which are connected by I; the inverse inputs of the CC-triggers are connected to the output of the second OR element and the input of allowing synchronous parallel loading of the first OR counter; the direct inputs / and K of the second OK-trigger are connected to the inverse output of the first UkK-

trigger; the direct output of the first OK-trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the third input of loading the first counter; the direct output of the second CC-trigger is connected to the second input of the fourth element AND, the third input of the first OR element; the first loading input of the first counter is connected to the logical unit level, the fourth loading input of the first counter is connected to the inverse output of the first CC flip-flop, the second loading input is connected to the logical zero level; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the H5-trigger forms the input of the supply of start pulses; the output of the third element I forms the output of the first phase (ET), and the output of the fourth element forms the output of the second phase (E2) of pulses.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for debugging the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and data input inputs О0о-Оз, an input for enabling the digit mode Е, input of asynchronous installation to zero state B; the first (2) and the second (3) CC-triggers with the transition permission input (inverse CC inputs) and the inputs of the asynchronous installation in the zero state B; But-trigger 4; the first (5), second (6), third (7) and fourth (8) elements of I!; the first (9) and second (10) OR elements; resistor 11 and capacitor (12) connected in series, connected to the same power source.

The common point of the series-connected resistor 11 and capacitor 12 is connected to the first inputs of the elements 5, 6. The second input of the element 5 forms the input of the supply of stop pulses (or) of the formation of output pulses. The output of element 5 is connected to the input (YAN) of the installation in the zero state of the A5-trigger. The second input of element 6 is connected to the output of element 9. The output of element 6 is connected to the inputs of the asynchronous unit in the zero state of the counter 1 and UV-triggers (2, 3).

The inverse inputs of the UC flip-flops, which form the transition enable input of the second counter, are connected to the output of element 10 and the enable input of synchronous parallel loading (I) of counter 1, the direct inputs ./ and K of the trigger Z are connected to the inverse output (1) UV trigger 2.

The direct output of trigger 2 is connected to the first inputs of elements 7, 8, to the second input of element 9 and to the third (O2) load inputs of counter 1, the first (Oo) load input is connected to the level of a logical unit, the fourth input (Yuz) the load is connected to the inverse output (1) of the first UOK flip-flop, the second (01) input of the load is connected to the logical zero level. The direct output of trigger C is connected to the second input of element 8 and the third input of element 9. Outputs

C5 of the second (Cx), third (Sg) and fourth (Oz) digits of counter 1 are connected to the inputs of element 10. The clock inputs (C) of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator. The input of the asynchronous unit (5) in the single state of the H5-trigger forms the input of the supply of start pulses (5iap). The output of element 7 forms the output of the first phase (E1), and the output of element 8 forms the output of the second phase (E2) of pulses.

We will consider the function analysis for the setting option for the formation of a two-phase sequence, the duration of the pulses is equal to 8T, and the pauses between adjacent phases are equal to 4T, provided by the value of the signals generated at the inputs of the parallel load of the counter 1. The presence of a chain consisting of a resistor 11 and a capacitor 12 connected in series, connected to the bus of the supply voltage ZHE, when the power source is turned on for a certain period of time forms a logical zero level at the inputs of elements 5 and 6, ensuring the formation of a logical zero level at their outputs, that is, at the inputs of the asynchronous installation in the zero state (NC) of triggers 2, C , 4 and counter 1. After the capacitor is charged, the single value at the first input of element 6 remains unchanged.

After the end of the transient process associated with turning on the power supply, counter 1 and flip-flops go to the zero state, forming: a logical zero level at the outputs

Fo-Oz counter 1; at the output of element 10, the value of the signal on which is equal to the logical sum of the signals from the outputs Sn, 2, Oz (I-O m С m Oz); on the direct outputs of triggers 2, 3; at the input of allowing synchronous loading of counter 1 and at the inverse inputs of y and K-triggers 2, З (at the input of allowing synchronous transition of the second counter); at the output of element 9, which is connected to the input of element 6, which provides a logical zero level at the inputs B of the asynchronous unit to the zero state of the counter 1 and triggers 2, C and after the transition process associated with the charge of the capacitor 12.

Since the mode of asynchronous setting of the counter 1 and triggers 2, Z to the zero state has 60 priority in relation to all the last modes, as long as the logic zero level is maintained at the inputs of element 9, when clock pulses arrive, the zero state of the counter 1 and triggers 2 , Z will remain unchanged, that is, the zero value at the outputs of the shaper (Е1-01.02, г2-01.02 ) will remain unchanged.

During the arrival of the trigger pulse (5iap) at the input 5 of the flip-flop 4, the flip-flop goes into a single state, forming a level of a logical unit at its output (0-1), at the input and output of element 9, which provides a level of a logical unit at the inputs of the CC of the counter 1 and triggers 2, 3, removing the blocking. Since at the entrances | of counter 1 and triggers 2, C level of logical zero, then until the arrival of the next clock pulse, the first counter is in the mode of readiness for loading, and the second counter is in the mode of readiness for transition to the first next state. And then during the introduction of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at the inputs 01-02-0, bo-Oz-C-1. Counter 1 goes to state ОзО201О0-1001-1, the second counter goes to the next state (02-01-1), which leads to the formation of a single value at the output of element 10, at inputs I of counter 1, at inverse inputs. and K-triggers 2, 3, that is, before the prohibition of loading counter 1 and transition of the second counter, allowing the counting (subtraction) mode of counter 1.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, while the state of the second counter remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10. As a result, counter 1 will again go into download mode, and the second counter will go into transition mode. During the arrival of the next clock pulse, counter 1 is loaded in parallel with the values of the signals generated at inputs 0-0, 02-031-1, О0-1, Оз-СИ-0, Counter 1 goes into state Оз020100-0101-5, the second counter - to the next state (02-1, 01-0),

In the future, the processes are similar, that is, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10, counter 1 again switches to loading mode, and the second counter to transition mode. Counter 1 is loaded in parallel with the values of the signals at the inputs YuOo-Yuz. Counter 1 again goes to state 1001-9, and the second counter goes to the next one according to its transition graph, at the outputs of the second counter (at the outputs of triggers 2, 3) values are formed according to the state, which determine the values of the signals at the outputs of elements 7, 8 (at outputs of the shaper RI, E2).

In fig. 2 shows the transition graph of the shaper, consisting of four rings (the upper ring is the transition graph of counter 1, the second ring is the transition graph of the second counter, the third ring is the value of the signals at the output EI1, the fourth ring is the value of the signals at the output E2 with a common peak corresponding to the zero state counters, and Fig. C shows graphs illustrating the work for the option of setting ЮОо-1, 0-0, 02-01, ЮОз-СІ, for the formation of a two-phase sequence, the duration of which pulses is equal to 9T, and the pause between adjacent phases is equal to 5T .

Stopping the process of forming the output sequence of pulses is carried out by applying a pulse corresponding to the level of a logical unit to the stop input (5ior), which forms an active signal level at the AB input of the HA5-trigger asynchronous unit, which leads to its transition to the zero state (0-0). The pulse or, as a rule, is asynchronous in relation to the pulses of the external generator and to the state of the counters.

If the second counter (triggers 2, 3) is in the zero state at the time of the arrival of the pulse 2ior, then when the trigger 4 goes to the zero state, a logical 0 level will be formed at the inputs of element 9 and its output, causing a logical zero level at the input and output of element 6 , which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of forming pulses at the outputs E1, E2.

If at the moment of the arrival of the pulse 5ior the second counter is in a state other than zero, then the output of element 9 connected to the input of element 6 will have a level of logical unit. Since the second input of element 6 also has the level of a logical unit, determined by the unit value on the capacitor, then the output of element 6 (at inputs B of the counter and triggers 2, 3) will have a level of logical unit. It follows from this that at the moment of the introduction of the Bohr pulse, the termination of the formation will not occur, thereby preventing the distortion of the last pulse in the original sequence. And only with the introduction of further clock pulses, when the transition of the second counter to the zero state will occur at the inputs of element 9 and its output, a level of logical 0 will be formed, causing the level of logical zero at the input and output of element b, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of formation.

With the arrival of the next start pulse, all processes are repeated.

In contrast to the known device, the simplification of the structure of the start-stop device and the second counter, made on two UV-triggers, made it possible to simplify the manufacturing technology of the former, reduce the power consumption and cost.

Claims (1)

UTILITY MODEL FORMULA A two-phase pulse train generator with reconfigurable timing parameters, containing two binary counters, the first of which is reversible, configured for subtraction mode, having a sync pulse supply input, an overflow output, a synchronous parallel load enable input and load data inputs, digit mode enable input, asynchronous device input to the zero state (at the same time, the active signal at the synchronous parallel download enable input has priority in relation to the active signal at the digit mode enable input, and the active signal at the asynchronous device input to the zero state has priority in relation to to the active signal at the synchronous parallel download enable input and at the digital mode enable input); a start-stop device containing a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and capacitor connected to a power source; first and second elements AND first and second elements OR; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements I/; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first element is ORed to the first input of the second element !; the output of the second element I is connected to the inputs of the asynchronous unit in the zero state of the first and second counters, which differs in that the third and fourth elements I are introduced, at the same time, the start-stop device is made on an asynchronous B5 flip-flop, and instead of the second four-digit counter, a two-digit one is introduced subtractive counter with the sequence of transitions 00-11-10-01-00, made on two 9OK flip-flops with the input of the asynchronous unit in the zero state; the first .K-flip-flop has inverse inputs. and K; the second Uk trigger has inverse and direct inputs ./ and К, which are combined by И; the inverse inputs of the K-triggers are connected to the output of the second OR element and the input of allowing synchronous parallel loading of the first counter; direct inputs U and K of the second UV-trigger are connected to the inverse output of the first UV-trigger; the direct output of the first UOK trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the third input of loading the first counter; the direct output of the second CC-trigger is connected to the second input of the fourth element AND, the third input of the first OR element; the first loading input of the first counter is connected to the logical unit level, the fourth loading input of the first counter is connected to the inverse output of the first )OK-trigger, the second loading input is connected to the logical zero level; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous installation to the single state of the No-trigger forms the input of the supply of start pulses; the output of the third element I forms the output of the first phase (E1), and the output of the fourth element I forms the output of the second phase (E2) of pulses.