UA127841U - DUAL-PHASE PULSE CONVERTER WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

The two-phase pulse generator with reconfigured time parameters contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has a pulse input pulse output, overflow output, synchronous parallel load resolution input and digital input inputs input of the asynchronous installation to the zero, startup device containing the trigger with the input of the asynchronous installation to the zero state and a chain consisting of a series connection They resistor and capacitor connected to the power source; the first and second elements I; the first and second elements OR. Introduced the third element OR, the third and fourth elements And, the startup device is made on an asynchronous RS-trigger, and instead of the second four-digit counter introduced a two-bit subtractive counter with a sequence of transitions 00-11-10-01-00, made in two synchronous DL triggers, with transition entry input and zero asynchronous input.

Description

The useful model belongs to pulse, computing and measuring technology, designed for the formation of a two-phase sequence of pulses with reconfigurable time parameters.

There are known shapers that contain a quartz reference generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Osnovyi! digital technology. - M.""MIR", 2001. - Fig. 5.13-5.181.

The disadvantage of known devices is the complexity of the internal structure.

Known generators of a periodic multiphase sequence of pulses with reconfigurable time parameters (Ukraine patents for the invention Mo Mo 87081, 89240, 106091, 106395, 10807, 106867, 10888, 106091, 1070281.

The disadvantage of the devices is the complexity of the structure, due to the need to use two multi-bit binary counters, decoders.

The closest analogue is a two-phase pulse sequence generator with reconfigurable time parameters (Ukrainian utility model patent 63193), which contains two binary counters, the first of which is reversible, configured for subtraction mode, having an input for supplying synchronization pulses, an input for enabling synchronous parallel loading, and inputs data submission during loading, the input of the permission of the counting mode, the input of the asynchronous installation in the zero state, the overflow output; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; the first and second OR elements, while the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the first AND element; output of the first element I! connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of the known device is the complexity of the shaper circuit, which is due to the construction

From the start-stop device on the synchronous O-trigger and the use of the second four-digit counter and, as a result, high power consumption, high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The problem is solved by the fact that the generator of a two-phase sequence of pulses with reconfigurable time parameters, containing two binary counters, the first of which is reversible, configured for the subtraction mode, having an input for supplying synchronization pulses, an overflow output, an input for enabling synchronous parallel loading and input inputs data during download, the input of the digital mode enable, the input of the asynchronous installation in the zero state (in this case, the active signal at the input of the permission of synchronous parallel loading has priority in relation to the active signal at the input of the enable of the digital mode, and the active signal at the input of the asynchronous installation in the zero state has priority in relation to the active signal at the synchronous parallel download enable input and at the digital mode enable input); a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; the first and second OR elements, while the first input of the first OR element is connected to the output of the trigger; the output of the first element OR is connected to the first input of the first element Y, according to the useful model, the third element OR, the third and fourth elements AND are introduced, while the start-stop device is made on an asynchronous B5 flip-flop, and instead of the second four-digit counter, a two-digit subtraction counter is introduced with the sequence of transitions 00-11-10-01-00, performed on two synchronous Oi-triggers, with the transition permission input and the input of the asynchronous installation in the zero state, the inverse output of each trigger is connected to its OI input; the direct output of the first OiI trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the first input of the second OR element; the direct output of the second AND trigger is connected to the second input of the third AND element and the third input of the first OR element; the inverse output of the second I-trigger is connected to the second input of the fourth element I!; the outputs of the third and fourth elements AND form the outputs of the shaper; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element, the output of which is connected to the input of enabling synchronous 60 parallel loading of the first counter, the input of enabling the transition of the first and -

trigger and the second input of the second OR element; the output of the second OR element is connected to the transition enable input of the second OiI-trigger; a chain consisting of a capacitor and a resistor connected in series is connected to a power source, the common point of which is connected to the first inputs of the first and second elements C; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element I is connected to the input of the asynchronous unit in the zero state of the H5 flip-flop; the second input of the second element is connected to the output of the first OR element; output of the second element | connected to the inputs of the asynchronous installation in the zero state of the first and second counters; tuning for the formation of a two-phase sequence, the duration of pulses and pauses between phases, which is equal to

ZT, provided by the value of the signals at the inputs of loading counter 1: 0o-0.-1, p2-Oz-0; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the No-trigger forms the input of the supply of start pulses.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses С, an input for configuring the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and data input inputs 0o-ХО3, an input for enabling the counting mode Ро, input of asynchronous installation in the zero state

IN; synchronous I-triggers 2, З with the input of the permission of the transition of ГИ and the input of the asynchronous installation in the zero state B; B5o-trigger 4; the first (5), second (6), third (7) and fourth (8) elements |; the first (9), second (10), third (10) and fourth (11) elements OR; resistor 12 and capacitor (13) are connected in series, connected to the JHE power source.

The common point of the series-connected resistor 12 and capacitor 13 is connected to the first inputs of the elements 5, 6. The second input of the element 5 forms the input of the supply of stop pulses (or) of the formation of output pulses. The output of element 5 is connected to the input of the asynchronous unit in the zero state of the No-trigger.

The second input of element 6 is connected to the output of element 9. The output of element 6 is connected to the inputs of the asynchronous unit in the zero state of the counter and 0-triggers.

The inverse output of each trigger is connected to its Y input. The direct output (01) of trigger 2 is connected to the first inputs of elements 7, 8, to the second input of element 9, to the first input of element 10. The direct output (02) of trigger C is connected to is connected to the second input of element 7 and the third input of element 9. The inverse output of trigger Z is connected to the second input of element 8. The outputs of the second (0), third (O2) and fourth (Oz) digits of counter 1 are connected to the inputs of element 11, the output of which is connected to the enable input of synchronous parallel loading of the counter 1, the enable input of the transition (I) of the flip-flop 2 and the second input of the element 10. The output of the element 10 is connected to the enable input of the transition (I) of the flip-flop 3. The output of the element 7 forms the output of the first phase (E1), and the output of element 8 forms the output of the second phase (E2) of pulses. The clock inputs of the first and second counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external quartz generator. The input of the asynchronous installation to the single state of the H5-trigger forms the input of the supply of start pulses (eiapy).

We will consider the analysis of functioning for the option of setting up the formation of a two-phase sequence, the duration of pulses and pauses between phases, which is equal to ЗТ, which is provided by the value of the signals set at the inputs of loading counter 1: Юо-01-1, О2-ЮОз3-0.

The presence of a circuit consisting of a series-connected resistor 12 and a capacitor 13 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 5 and 6, ensuring the formation of a logical zero level at their outputs , that is, at the inputs of the asynchronous installation to the zero state (PE) of triggers 2, 3, 4 and counter 1. After the capacitor is charged, the single value at the first input of element 6 remains unchanged.

After the end of the transient process associated with turning on the power supply, counter 1 and flip-flops go to the zero state, forming: a logical zero level at the outputs

Фоо-Оз counter 1: at the output of element 11, the value of the signal on which is equal to the logical sum of the signals from the outputs Сн, О2, Сз (I-01 m О» m Оз); on the first input of element 10; on the input of enabling the synchronous loading of counter 1 and on the inputs of enabling the transition of trigger 2: the level of logical zero on the direct outputs of triggers 2, З and on the output of element 9, which is connected to the input of element b, which ensures the level of logical zero on the inputs P of the asynchronous installation to the zero state of the counter 1 and triggers 2, C and after the end of the transition process associated with the charge of the capacitor 13.

Since the mode of asynchronous setting of the counter 1 and triggers 2, Z to the zero state has 60 priority in relation to all the last modes, as long as the logic zero level is maintained at the inputs of element 9, when clock pulses arrive, the zero state of the counter 1 and triggers 2, C will remain unchanged, that is, the zero value at the outputs of the shaper (Е1-01.02, г2-01.02) will remain unchanged.

During the arrival of the trigger pulse (5iap) at the input 5 of the flip-flop 4, the flip-flop goes into a single state, forming a level of a logical unit at its output (0-1), at the input and output of element 9, which provides a level of a logical unit at the inputs of the CC of the counter 1 and triggers 2, 3, removing the blocking. Since at the entrances | counter 1 and triggers 2,3 have a logical zero level, then by the time of the arrival of the next clock pulse, the first counter is in the mode of readiness for loading, and the second counter is in the mode of readiness for transition to the first next state. 1, then during the entry of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the signal values set at inputs Oo-01-1, 02-Oz320. Counter 1 goes to the state Oz020100-0011-3, the second counter goes to the next state (02-01-1), which leads to the formation of a single value at the output of element 11, at the inputs Y of counter 1, triggers 2, 3, until the loading is prohibited of counter 1 and the transition of the second counter, enabling the counting (subtraction) mode of counter 1. During the entry of further clock pulses, the content of counter 1 will decrease, and the state of the second counter remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 11. As a result, counter 1 will again go into download mode, and the second counter will go into transition mode. During the arrival of subsequent clock pulses, the processes are similar, that is, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 11, counter 1 goes into loading mode, and the second counter goes into transition mode. Counter 1 is again loaded in parallel with the values of the signals at the Oo-Yuz inputs. Counter 1 again goes to state 0011-3, and the second counter goes to the next one according to its transition graph, at the outputs of the second counter (at the outputs of triggers 2, 3) values are formed according to the state, which determine the values of the signals at the outputs of elements 7, 8 (at outputs of the shaper H1, Eg).

In fig. 2 shows the transition graph of the shaper, consisting of four rings (the upper ring is the transition graph of counter 1, the second ring is the transition graph of the second counter, the third ring is the value of the signals at the output EI1, the fourth ring is the value of the signals at the output E2 with a common peak corresponding to the zero state counters, and Fig. C shows graphs illustrating the operation for the setting option (О0о-01-1, Ю2-О3-0) of the shaper for the duration of pulses and the pause between the first and second phases, which is equal to ЗТ.

The process of forming the output sequence of pulses is stopped by applying a pulse corresponding to the level of a logical unit to the stop input (5ior), which forms an active signal level at the input B of the asynchronous unit B 5 - the trigger, which leads to its transition to the zero state (0-0) . The boron pulse is, as a rule, asynchronous in relation to the pulses of the external generator and to the state of the counters.

If at the moment of the arrival of the pulse 5ior the second counter will be in the zero state, then when the U-trigger 4 transitions to the zero state at the inputs of element 9 and its output, a level of logic 0 will be formed, causing a level of logic zero at the input and output of element 6, which will lead to transition of counter 1 to the zero state, and therefore to the termination of the generation process.

If at the moment of the arrival of the pulse 2ior the second counter is in a state other than zero, then the output of element 9, connected to the input of element 6, will have a level of logical unit. Since the second input of element 6 also has the level of a logical unit determined by the single value at the output of element 9, the output of element 6 (at the inputs B of the counter and triggers 2, 3) will have a level of logical unit. It follows from this that at the moment of the introduction of the Bohr pulse, the cessation of generation will not occur, thereby preventing the distortion of the last pulse in the output sequence. | only with the introduction of further clock pulses, when the transition of the second counter to the zero state will occur at the inputs of element 9 and the level of logic 0 will be formed at its output, causing the level of logic zero at the input and output of element b, which will lead to the transition of counter 1 to the zero state, and therefore, before the termination of the generation process.

With the arrival of the next start pulse, all processes are repeated. Unlike the known device, the simplification of the structure of the start-stop device and the second counter, made on two synchronous Oi-triggers, made it possible to simplify the manufacturing technology of the former, reduce the power consumption and cost.

Claims (1)

UTILITY MODEL FORMULA A two-phase pulse train generator with reconfigurable timing parameters, containing two binary counters, the first of which is reversible, configured for subtraction mode, having a sync pulse supply input, an overflow output, a synchronous parallel load enable input and load data inputs, count mode enable input, asynchronous reset input, with an active signal at the synchronous parallel load enable input having priority over an active signal at the count mode enable input, and an active signal at the asynchronous reset input having priority over of the active signal at the synchronous parallel download permission input and at the digital mode permission input; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; the first and second OR elements, while the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the first AND element, which differs in that the third OR element, the third and fourth AND elements are introduced, while the start-stop device is made on an asynchronous No-trigger, and instead of the second four-digit counter, a two-digit subtraction counter is introduced with the sequence of transitions 00-11-10-01-00, performed on two synchronous bi-triggers, with the input of the transition permission and the input of the asynchronous installation in the zero state, the inverse output of each trigger is connected to its OO input; the direct output of the first Oi-trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the first input of the second OR element; the direct output of the second OiI-trigger is connected to the second input of the third element AND and the third input of the first OR element; the inverse output of the second O-trigger is connected to the second input of the fourth element I; outputs of the third and fourth elements | form the outputs of the former; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the third OR element, the output of which is connected to the enable input of the synchronous parallel loading of the first counter, the enable input of the transition of the first Obi flip-flop and the second input of the second OR element; the output of the second OR element is connected to the transition enable input of the second 0-trigger; a chain consisting of a capacitor and a resistor connected in series is connected to a power source, the common point of which is connected to the first inputs of the first and second elements C; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element I is connected to the input of the asynchronous unit in the zero state of the H5 flip-flop; the second input of the second AND element is connected to the output of the first OR element; the output of the second element is connected to the inputs of the asynchronous unit in the zero state of the first and second counters; setting for the formation of a two-phase sequence, the duration of pulses and pauses between phases, which is equal to ZT, is provided by the value of the signals at the inputs of counter loading 1: Yubo-01-I, 02-ЮОз3-0; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the No-trigger forms the input of the supply of start pulses.