UA136268U - TRIKANAL SERIES FORMER WITH ADJUSTABLE DURATION AND NUMBER OF PULSES IN CHANNELS AND DELAY OF BEGINNING OF RELATIONSHIP RELATIONSHIP - Google Patents

Abstract

The shaper of the three-channel series with reconfigurable duration and number of pulses in the channels and the delay of the beginning of formation relative to the starting pulse contains the first and second binary counters, the first of which is a reversible four-bit, tuned to subtraction mode, 0111-1111-1110-1100-1000; a starting device comprising an asynchronous RS trigger and a circuit consisting of a resistor and a capacitor connected in series; five elements I; three OR elements; two inverters; element XOR, the first input of which is connected to the input of the shaper C, and the second to the input of setting the shaper for a given pulse duration V, the output of the element XOR is connected to the inputs of three elements I, signals at the outputs of which determine the output functions K1, K2 , K3. When adjusting the shaper to form a three-channel series of pulses, the number of the first and third channels which is equal to six (n1 = n3 = 6), the number of pulses of the second two (n2 = 2), with a delay of formation relative to the starting pulse equal to ten clock pulses (t3 = 10T).

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a three-channel series with adjustable duration and number of pulses in the channels and the delay of the start of formation relative to the starting pulse.

There are well-known shapers that contain a quartz reference generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input |Novikov Y.V. Fundamentals of digital technology, M. "MIR" 2001, Fig. 5.13-5.181I.

The disadvantage of known devices is the complexity of the internal structure.

A well-known generator containing two typical reversible binary counters configured for the subtraction mode, a two-digit counter made on UV flip-flops, a start-stop device made on a synchronous O-flip-flop (Ukraine patent for utility model Mob52511.

The disadvantage of the known device is the complexity of the structure and limited functionality.

The closest in terms of technical essence and the result achieved is a three-channel series generator with adjustable number and duration of pulses in the channels and delay of the start of formation relative to the start pulse (Ukrainian patent for a useful model Mob652761 | containing two reversible binary counters configured for subtraction mode , each of which has a sync pulse supply input, a synchronous parallel load enable input, and a load data supply input, a count mode enable input, an asynchronous reset input to the zero state (while the active signal at the synchronous parallel load enable input has priority over the active signal on enable input of the digital mode, and the active signal at the input of the asynchronous installation in the zero state has priority over the active signal at the enable input of the synchronous parallel loading and at the enable input of the digital mode), discharge outputs, overflow output; a start-stop device that contains a trigger with an ladies of the asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; the HOK element, the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the setpoints

From the parameters of the output pulses; the clock inputs of the first counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first element OR is connected to the input of the second element AND!; output of the second element I! connected to the input of the asynchronous installation of the first counter in the zero state; the inverse overflow output of the first counter is connected to the input of the first inverter; the first entry of the element

The HOK is connected to the input of the shaper, the second input of the HOK element forms the input for adjusting the shaper for the given duration of pulses, the output of the HOK element is connected to the first inputs of the third, fourth and fifth elements of I.

The disadvantage of this device is the complexity of the internal structure and limited functionality.

The useful model is based on the task of expanding the functionality and simplifying the internal structure of the former.

The problem is solved by the fact that in a three-channel series generator with adjustable number and duration of pulses in the channels and a delay of the start of formation relative to the start pulse, which contains two counters, the first reversible binary counter is configured for subtraction mode, has an input for supplying synchronization pulses, an input for enabling synchronous parallel download and data input inputs during download, digit mode enable input, asynchronous device input to zero state (at the same time, the active signal at the synchronous parallel download enable input has priority over the active signal at the digital mode enable input, and the active signal at the asynchronous device input in the zero state has priority over the active signal at the synchronous parallel loading enable input and at the digit mode enable input), discharge outputs, overflow output; a start-stop device, which contains a trigger with inputs of an asynchronous installation in the zero and one state, a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; the HOK element, the inputs of parallel loading of the counter form the tuning inputs of the generator for the given parameters of the output pulses; clock inputs of the counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of the second element is connected to the input of the asynchronous installation of the counter in the zero state; the inverse overflow output of the counter is connected to the input of the first inverter; to the first inputs of the third, fourth, and fifth elements AND, the output of the XOK element is connected, the second input of which forms the input of adjusting the shaper for the given duration of pulses, according to the useful model, a three-input OR element is introduced, the inputs of which are connected to the outputs of the second, the third and fourth digits of the first counter, the output - with the input of the permission to load the first counter and the first input of the second OR element; the second counter is a four-bit cyclic device with a transition sequence of 0000-0001-0011-0111-1111-1110-4100-1000, a synchronous load enable input (transition), a load input of the first bit connected to the inverse output of the fourth bit, an asynchronous setup input of zero, performed on four synchronous U-flip-flops with a synchronous transition enable input, the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input of the second counter; the output of the fourth digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element

And the loading inputs of the first counter are connected to its inverse or direct overflow output or to the logical zero or one level; the output of the third element AND forms the output of the first CI channel; the output of the fourth element I forms the output of the second channel K2; the output of the fifth element I forms the output of the third short-circuit channel; if the number of pulses of the first and third channels is equal to six, the number of pulses of the second channel is two, with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, , the first and third inputs of the synchronous parallel loading of the first counter are connected to the logic zero level , the second load input is connected to the logic unit level, the fourth load input is connected to the direct overflow output (to the output of the first inverter); the second and third inputs of the third element 1 are connected respectively to the direct output of the first and

With the inverse output of the fourth digits of the second counter; the second and third inputs of the fourth element And are connected, respectively, to the direct outputs of the first and fourth digits of the second counter; the second and third inputs of the fifth element AND are connected correspondingly/ to the direct output of the fourth and the inverse output of the first digits of the second counter.

In fig. 1 shows a diagram of the former, in fig. 2 - graph of transitions of the shaper, in fig. C - graphs illustrating the work for a given configuration option (O00-0, 0-1, O2-0, Yuz-Ra).

The generator contains the first 1 and the second 2 counters, the counter 1 is a reversible four-bit, configured for the subtraction mode, which has an input for supplying synchronization pulses C, an input for enabling synchronous parallel loading I! and inputs of data supply during loading (Оо-ЖОз), the input of enabling the counting mode E, the input of the asynchronous installation in the zero state K, the outputs of the digits (Оо-Оз), the overflow output Re, the second four-bit counter 2 with the sequence of transitions 0000-0001-0011- 0111-1111-1110-1100-1000 (Johnson's counter), performed on four synchronous U-flip-flops, input I to enable synchronous loading (transition), input to load the first bit of Uo and input of asynchronous installation in the zero state K; K5-trigger 3; the first 4, the second 5, the third 6, the fourth 7 and the fifth 8 elements Y; the first 9 and the second 11 two-input OR elements; three-input element OR 10; element HOK 14; the first 12 and the second 13 inverters; resistor 15 and capacitor 16 are connected in series to the same power source.

The common point of the series-connected resistor 15 and capacitor 16 is connected to the first inputs of elements 4, 5. The second input of element 4 is connected to the output of the inverter 12. The output of element 4 is connected to the input of the installation in the zero state of the K5 flip-flop 3. The second the input of element 5 is connected to the output of element 8, the first input of which is connected to the output of Ko5-trigger 3, and the second - to the output of the fourth digit C) of counter 2. The output of element 5 is connected to input K of setting the counters to zero state. The inputs of element 9 are connected to the outputs of the second 01, the third C; and the fourth Oz of counter 1 digits; the overflow output of the counter 1 P is connected to its input allowing the loading mode and the input of the inverter 11, the output of which is connected to the first input of the element 10; the second input of element 10 is connected to the output of element 9. The output of element 10 is connected to the enable input of the GI transition mode. counter 2. The output Oz of the fourth digit of counter 2 is connected to the input of the inverter 13, the output of which is connected to the second input of element 4.

The clock inputs C of the counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator. Inputs K of the counters form the input of the asynchronous device of the generator in the zero state.

Tuning the shaper to form a single three-channel series with given parameters (pulse duration, the number of pulses of the first, second and third channels and the duration of the delay of the start of formation relative to the start pulse) is ensured by connecting the loading inputs of the first counter with its inverse or direct overflow output, or with the level logical zero or one depending on the set values of these parameters. When setting the shaper to form a single three-channel series, the pulse duration of which is equal to the duration of the clock pulses, the control input M of the element

HOK 14 is connected to the level of logic 0. If the duration of the pulses is equal to the duration of the pause between clock pulses, the control input M of the element HOK 14 is connected to the level of a logical unit. If the number of pulses of the first and third channels is equal to six (n1i-pz-6) clock pulses fed to the input of the shaper from the output of the external generator, the number of pulses of the second channel is equal to two (n2-2), with a delay in the start of formation relative to the start pulse, which is equal to ten periods (iz-10T), the first input Оо and the third ХОг2 inputs of the synchronous parallel loading of the counter 1 are connected to the level of logical zero, the second input Юй loading is connected to the level of logical unit, the fourth input Юз loading is connected to output of the first inverter (О0о-02-0, 0-1, ХОз-Ра). The output of element 6 forms the output of the first channel of the unit series: k1-osa so (Me) . The output of element 7 forms the output of the second channel of the unit series: Kg - 35 00 (M in C) The output of element 8 forms the output of the third channel of the unit series: kz-sora sova)

The presence of a chain consisting of a series-connected resistor 15 and a capacitor 16 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs , that is, at the inputs of the asynchronous installation in the zero state K of the trigger and counters. At the end of the capacitor charge, the unit value at the first inputs of elements 4, 5 remains unchanged.

After the end of the transient process associated with turning on the power source,

From the counters and the trigger go to the zero state, forming: the logical zero level at the overflow output of counter 1, at the outputs О0о-Оз, at the output of element 10, the value of the signal at which is equal to the logical sum of the signals from the outputs О:, О2, Оз (I- 031 m O» m Oz), at the output of the element 9, which is connected to the input of the element 5, which provides a logical zero level at the inputs of the LCD of the asynchronous unit to the zero state of the counters and after the transition process associated with the charge of the capacitor 16. As long as the mode of asynchronous setting of the counters to the zero state has priority over all the last modes, until then the logic zero level will be maintained at the inputs of element 9, when the clock pulses arrive, the zero state of the first and second counters will remain unchanged, that is, the zero value will also remain unchanged at the outputs of the shaper.

During the arrival of the trigger pulse (5iag) at the input 5 of the flip-flop C, the flip-flop goes into a single state, forming a level of a logical unit at its output (0-1), the output of element 9, and therefore at the input and output of element 5, which provides a level of logical unit on inputs K of the first 1 and second counters, removing the zero state blocking. Since there is a logical zero level at input Y of counter 1, and a level of logical one at input I. of the second counter, then until the arrival of the next clock pulse, counter 1 is in the mode of readiness for loading, and the second counter is in the mode of transition prohibition.

During the entry of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at its inputs of parallel loading 5О О3020100-1010. Counter 1 goes to the state О3020:00-1010-10 (ten), which leads to the formation of a single value at the overflow output of counter 1, a single value at the output of elements 10, 11, at the input I. of counter 1, i.e. the prohibition of loading counters, permission counting (subtraction) mode of counter 1. During the arrival of further clock pulses, the content of counter 1 will decrease, and the zero state of the second counter will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 10, 11. As a result, the first counter 1 again switches to the download mode, and the second - to the transition mode. And then, during the arrival of the next clock pulse along its edge, counter 1 is loaded in parallel with the values of the signals at their inputs ЮОз020100-0010. Counter 1 goes into state Oz020100-0010-2. The second counter will go to the next state О3020:100-0001-1, starting the formation of the first pulse at the output of K1. In the future, the processes are similar, that is, every time, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 10, 11. As a result, the first counter 1 goes into the loading mode, and the second - into the transition mode to the next state. Pulses at the output of K2 are formed in the states: 0011, 0111, 1111. At the same time, as soon as the content of counter 1 becomes equal to 1111, a zero value is formed at the output of the inverter 13 and the input K of the trigger Z, which leads to the transition of the trigger to the zero state (0-0 ). Pulses at the output of the short circuit are formed in the state: 1110, 1100, 1000. In the future, again, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the outputs of elements 10, 11, the second counter goes into the transition enable mode. | then during the arrival of the next clock pulse, the transition of the second counter to the zero state occurs, forming a zero value at the output of elements 8, 5, which will lead to the transition to the zero state of the first counter, and therefore to the termination of the formation process.

With the arrival of the next start pulse, all processes are repeated.

Since the start pulses are asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range: 10 « из « 1 IT.

In contrast to the known, the proposed former has a simplified internal structure and expanded functionality.

Claims (1)

USEFUL MODEL FORMULA A three-channel series generator with adjustable duration and number of pulses in the channels and a delay of the start of the formation relative to the start pulse, containing two counters, the first reversible binary counter configured for subtraction mode, has a synchronization pulse supply input, a synchronous parallel loading enable input and supply inputs data during download, the input of the digital mode enable, the input of the asynchronous installation in the zero state (at the same time, the active signal at the input of the synchronous parallel download permission has priority over the active signal at the input of the digital mode enable, and the active signal at the input of the asynchronous installation in the zero state has priority over of the active signal at input Zo of the permission of synchronous parallel loading and at the input of the permission of the digital mode), discharge outputs, overflow output; a start-stop device, which contains a trigger with an input of an asynchronous installation to zero; a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first, second, third, fourth and fifth elements of I; the first and second OR elements; first and second inverters; HOV element; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given parameters of the output pulses; the clock inputs of the first counter form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; at the same time, the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the input of the second AND element; the output of which is connected to the input of the asynchronous installation of the counter in the zero state; the inverse overflow output of the first counter is connected to the input of the first inverter; with the first inputs of the third, fourth and fifth elements | the output of the XOV element is connected, the second input of which forms the input of setting the shaper for the given duration of pulses, which differs in that a three-input OR element is introduced, the inputs of which are connected to the outputs of the second, third and fourth digits of the first counter, output - 3 is the enable input loading the first counter and the first input of the second OR element; the second counter is a four-bit cyclic device with a sequence of transitions 0000-0001-0011- 0111-1111-4110-414100-1000, a synchronous loading enable input (transition), a loading input of the first bit connected to the inverse output of the fourth bit, an asynchronous setup input of zero, performed on four synchronous U-flip-flops with a synchronous transition enable input, the second input of the second OR element is connected to the output of the first inverter; the output of the second OR element is connected to the transition enable input of the second counter; the output of the fourth digit of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the first element I; the loading inputs of the first counter are connected to its inverse or direct overflow output or to the logical zero or one level; the output of the third element I forms the output of the first channel Kt; the output of the fourth element I forms the output of the second channel Kg; the output of the fifth element I forms the output of the third short-circuit channel; if the number of pulses of the first and third channels is equal to six, the number of pulses of the second channel is two, with a delay of the start of formation relative to the start pulse, which is equal to ten periods of clock pulses, the first and third inputs of the synchronous parallel loading of the first counter are connected to the logic zero level, the second loading input is connected to the logic unit level, the fourth loading input is connected to the direct overflow output (to the output of the first inverter); the second and third inputs of the third element AND! connected, respectively, to the direct output of the first and inverse output of the fourth digits of the second counter; the fourth - with direct outputs of the first and fourth digits of the second counter; the fifth - with the direct output of the fourth and the inverse output of the first digits of the second counter. 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