UA139826U - PERIODIC SEQUENCE PULSE FORMER WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

The shaper of the periodic sequence of pulses with the adjusted time parameters contains: the common power supply (± E); reversible binary counter set to subtraction mode, with input of synchronous parallel loading permission and inputs of loading of loaded variables (providing adjustment of the shaper to the set time parameters of output pulses), input of permission of mode of counting and input of asynchronous setting to zero output; inverter; trigger with the input of the asynchronous installation to zero; the first and second elements of I; two-input element OR; a circuit consisting of a series-connected resistor and a capacitor connected to a power supply, the common point of which is connected to the first inputs of the first and second elements And, the output of the first element And is connected to the input of the asynchronous trigger to zero, the second the input of the second element AND is connected to the output of the two-input element OR, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous counter zero; the input of the inverter is connected to the overflow output of the meter, and the output - to its input resolution of the count mode, the clock input of the meter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of the external quartz oscillator.

Description

The shaper belongs to pulse technology and is designed to form a periodic sequence of pulses with a set duration of pulses, a period of passage and a delay of the start of formation relative to the starting pulse, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of an external quartz generator.

There are known generators that contain a set crystal oscillator operating in continuous mode, a synchronizing device and an output device that ensures the formation of the necessary series of pulses, the time parameters of which are determined by the time parameters of the pulses fed to the input of the clock generator. A.S. USSR Mo307502. - B.V. Mo20, 1971;

Clock generator. A.S. USSR Meo354544. - B.V. Me30, 19721.

The disadvantage of known devices is limited functionality due to setting the time parameters of the output sequence of pulses to a fixed mode.

There are well-known generators of a periodic sequence of pulses with a programmable duration and fixed spacing (patents of Ukraine for utility model 62517, 62519, 62520, 62522, 62525, The disadvantage of these devices is the complexity of their manufacture and, as a result, high power consumption, high cost, which are due to the need to use two reversible counters.

The closest in terms of technical essence and the achieved result is the generator of a periodic sequence of pulses with adjusted time parameters (a patent for a utility model

Ukraine Mo 61886, Bul. Mo14, 20111, which contains: common power source (PSU); reversible binary counter configured for the subtraction mode, with the input of enabling synchronous parallel loading and the input of supplying variables to be loaded (provide the adjustment of the shaper to the given time parameters of the output pulses), the input of enabling the counting mode and the input of asynchronous installation in the zero state, the overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input element OR; a chain consisting of a resistor and a capacitor connected in series, connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second the input of the second element AND is connected to the output of the first element OR, the first input of which is connected to the output of the flip-flop, the output of the second element | connected to the input of the asynchronous setting of the counter in the zero state; the inverter input is connected to the overflow output of the counter, and the output is connected to its count mode enable input, the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of an external crystal oscillator.

The disadvantage of the known device is limited functionality.

The basis of the useful model is the task of expanding the functionality of the periodic pulse sequence generator.

The task is solved by the fact that the generator of a periodic sequence of pulses with adjusted time parameters, which contains: a common power source (E); reversible binary counter configured for the subtraction mode, with an input for enabling synchronous parallel loading and inputs for supplying loaded variables (which ensure setting the shaper to the given time parameters of the output pulses), an input for enabling the counting mode and an input for asynchronous installation in the zero state, an overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input element OR; a chain consisting of a resistor and a capacitor connected in series, connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second the input of the second element is connected to the output of the two-input OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous setting of the counter in the zero state; the inverter input is connected to the overflow output of the counter, and the output is connected to its count mode enable input, the clock input of the counter forms the input of a shaper, which receives a continuous periodic sequence of pulses from the output of an external crystal oscillator, according to a useful model, the input of the asynchronous unit of the first the trigger in the single state; the second trigger with the inputs of the asynchronous installation in the zero and one state; four-bit digital comparator; the third and fourth elements |I; four-input element OR; second inverter; the first and second buttons that work for shorting: the second, third and fourth resistors, the first outputs of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output 60 of the third resistor is connected to the input of the asynchronous installation of the first trigger in the single state and the first contact of the first button; the second output of the fourth resistor is connected to the second input of the first element I and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the outputs of the second, third and fourth digits of the counter are connected to the last inputs of the four-input OR element; the output of a four-input element

OR connected to the first input of the third element AND, to the input of the unit in the single state of the second trigger; the second input of the third element And is connected to the input of the installation in the zero state of the second trigger and the overflow output of the counter; the direct output of the second trigger is connected to the first input of the fourth element AND, the second input of which is connected to the output A»B of the comparator and to the second input of the first OR element, the output of the fourth element AND forms the output of the shaper; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; when setting the shaper to form a periodic sequence, the duration of pulses in which is equal to three periods of clock pulses, the period of passage is equal to nine periods of clock pulses, and the start of formation is delayed relative to the start pulse by ten periods, the first input of parallel loading of the counter is connected to the direct output of the second trigger, the second input is connected to the inverse output of the second trigger; the third input is connected to the logical zero level; the fourth input is connected to the level of a logical unit, the first and fourth inputs of the second group of comparator inputs are connected to the logical zero level, the second and third inputs of the second group of comparator inputs are connected to the level of a logical unit; the first and third control inputs of the comparator are connected to the logical zero level, the second control input is connected to the logical unit level.

In fig. 1 shows the scheme of the former.

The generator contains: a reversible binary counter (1), which has an input for supplying clock pulses С, an input for setting the summation/subtraction mode Ш, an input for enabling synchronous parallel loading И and inputs for supplying data when loading бо, О:, ХО2, Оз, an enable input of the EE counting mode, the input of the asynchronous unit to the zero state B, the overflow output Ra; the first (2) and second (3) triggers with the inputs of the asynchronous setting of zero KE and unit 5; four-bit digital comparator (4), which has the first group of inputs Ao, An, Ag,

Az, the second group of inputs Vo, Vi, V», Vz; and the first, second, third control inputs I; the first (5), second (6), third (7/7) and fourth (8) two-input elements AND: two-input element OR (9); four-input element OR (10); first (11) and second (12) inverters; the first NO (13), the second

B2 (14), third VZ (15) and fourth VA (16) resistors; buttons ap (17) and Bir (18), which work for closing; capacitor C1 (19). The first outputs of the resistors are connected to the plus of the power source ("7E), the second output of the resistor 14 forms the output of the logical unit level "1". The second output of the resistor 15 is connected to the input of the asynchronous installation of the trigger 2 in the unit state and the first contact of the button 5iap. The second output of the resistor 16 is connected to the input of the element 5 and the first contact of the button bor. The second contacts of the buttons are connected to the common point of the power source (-

IS). The input of the inverter 12 is connected to the output of the first (Oo) digit of the counter, and its output is connected to the first input of the element 10. The outputs C: O2 Oz of the counter are connected to the last inputs of the element 10. The output of the element 10 is connected to the input of element 7 and input 5 of flip-flop 3. The second input of element 7 is connected to input B of flip-flop C and the overflow output of the counter. The input O0 of the parallel load of the counter is connected to the direct output (02) of the flip-flop C with the first input of the element 8, the second input of which is connected to the output A»B of the comparator and to the second input of the element 9, the output of the element 8 forms the output of the shaper PE. Input 0: connected to the inverse output (9 2) of flip-flop 3. Input O» is connected to the logical zero level "0". Input Yuz is connected to the level of logic unit "1". The first group of comparator inputs (Ao At A"; Az) is connected to the outputs of the corresponding digits (o С 02 Oz) of the counter. The first Vo and the fourth Vz inputs of the second group of comparator inputs are connected to the logical zero level "0" (with the minus of the power source), the second V". and the third Vg2 - to the logical unit level (with the second terminal "1" of resistor 14 (VzV2ViVo -0110).

The first and third control inputs (I) of the comparator are connected to the level of logical zero "0, the second control input is connected to the level of logical unit "1".

The former works in the following sequence.

The presence of a chain consisting of a resistor 13 and a capacitor 19 connected in series, connected to the supply voltage bus -E, when the power source is turned on for a certain period of time (determined by the time constant of the H:C:i circuit) forms a logical zero level at the inputs of elements 5, 6, ensuring the formation of a logical zero level at their outputs connected to the input of the asynchronous installation in the zero state of trigger Z and counter 1. After the end of the transient process associated with turning on the power source, trigger Z and the counter go to zero state, forming the level of logical zero, respectively: at the output

A" of the comparator, at the output of the trigger Z and at the output of the overflow of the counter 1, which leads to the formation of a logical zero level at the input EB of the trigger 4 (ensuring its zero state), at the output of elements 9, b (at the input A of the counter) and after the end of the transient the process associated with the charge of the capacitor 19, when the voltage on it will exceed the logical zero level.

Since the signal input at input A has priority in relation to all other control signals at the inputs of the counter, as long as the logic zero level is maintained at the inputs of elements 9, 6 (and therefore at their outputs), then upon arrival of clock pulses the zero state of the counter, triggers and the zero value of the signal at the output of the shaper will remain unchanged.

When the button 5iagi is pressed, a level of logical zero is formed at input 5 of trigger 2, which leads to its transition to a single state (01-11), forming a level of logical one at the output of element 9, and therefore at the input and output of element 6 (at the input of the AC counter ), removes the blocking of the zero state, and then a zero value at the enable input of the synchronous parallel loading of the counter prepares it to receive information from its inputs of synchronous parallel loading (Оз ЮО2 О0и ЮБо-1010).

Then, upon arrival of the first (after the end of the transient process associated with the start) clock pulse C along its front, parallel loading occurs.

The counter goes to the state (О30201000-1010. As a result of this transition, a single value is formed at the overflow output of the counter and at the output of element 7, and at the output of inverter 11 (at the input E of the counter) - a zero value, which leads to the prohibition of parallel loading and the permission of the counter counting mode . The zero state of the flip-flop C remains unchanged, which ensures that the zero value of the signal at the output of the counter decreases. At the same time, as long as the content of the counter will exceed the unit value, the unit value at the outputs of element 9 remains unchanged, which ensures the invariance of the zero value at the direct output as soon as the content of the counter becomes equal to 0001, a logical zero level is formed at the output of element 9, which leads to the formation of a logical zero level at the input of element 7 (at the enable input of the counter loading) and at input 5 of flip-flop 3, which leads to its transition to a unit state.And then upon arrival of the next clock pulse

From, the counter goes into state Oz020100-1001, due to the value of the signals generated at its inputs of parallel loading (Oz O2 01 Oo-1001). At the outputs of the comparator А»В (at the outputs Е of the shaper) the formation of a single value begins, since the value of the signals at the outputs of the Oz302010o counter exceeds the value of the signals at the inputs of the second group of signals ВзВ2ВИВ of the comparator. When the following clock pulses arrive, the content of the counter decreases. At the same time, as long as its content exceeds the value set at the inputs of the second comparator group (VzV2ViVo-0110), the value of the signal at the output of the generator will remain equal to 1. As soon as the content of the counter becomes equal to 0110, the value of the signal at the output of the comparator will become is equal to 0. When the following clock pulses arrive, the content of the counter continues to decrease, and the value of the signal at the output remains equal to 0 until the content of the counter becomes equal to 0001. As soon as the counter enters the state 0001, at the output of elements 10, 7 and at the input a logical zero level is formed when the load (I) of the counter is allowed to be loaded. When the next clock pulse arrives, the counter again goes to state 1001, starting a new cycle of forming a single value at the output of the generator. When subsequent clock pulses arrive, the processes are repeated.

Thus, after the end of the transient process associated with the start-up, when entering the input of the generator of a periodic sequence of pulses (with a period equal to T), a periodic sequence of pulses is generated at the output of the generator, a multiple of the period of clock pulses, the time parameters of which are: pulse duration yin - ZT, the duration of the pause -6T, the duration of the delay of the start of formation relative to the starting impulse of the drive -10T, the period of passage of Te - 9T.

The output sequence formation mode is stopped by pressing the bor button, which forms a logical zero level at input A of trigger 7, which leads to its transition to the zero state (01-00). The moment of pressing is asynchronous in relation to the pulses of the clock generator and to the state of the counter and triggers.

If at the moment of pressing the button 5ior the content of the counter is less than or equal to 0110, the value of the signal at the outputs of the comparator А»В is equal to 0, then when the trigger 2 goes to the zero state at the inputs of the element 9 and at its output, a level of logical zero will be formed, determining the level of zero at at the input and at the output of element 6 (at input B of the counter), which will lead to the transition of the counter to the zero state, and therefore to the termination of the generation mode.

If at the moment of pressing the eior button the content of the counter is greater than 0110, then when 60 trigger 2 goes to the zero state, the single value at the output of element 8 will remain unchanged,

because the outputs of the comparator A»B have the level of a logical unit. It follows from this that in this case, at the moment of pressing the button, the termination of the generation will not occur, thereby preventing the distortion of the last pulse in the generated output sequence.

When each successive pulse arrives at the input of the shaper C, the counter will transition according to the algorithm until its content becomes equal to 0110, causing a zero level at the input and output and the outputs of elements 10, 6, which will lead to the transition of the counter to the zero state , and therefore to the termination of the generation mode. The next time you press the ba button, all processes are repeated.

In fig. 2 shows the transition graph of the shaper consisting of three rings, the upper (first) ring is the transition graph of trigger 3, the second ring is the value of the signal at the output of the shaper, the third ring is the transition graph of the counter with a common vertex corresponding to the zero state of the counter and triggers. In fig. From are graphs illustrating the operation for a given variant of the formation of a periodic sequence with the adjusted duration of pulses, the period of passage and the delay of the start of formation relative to the starting pulse, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of an external quartz generator.

Since pressing the 5bia button is asynchronous with respect to the clock pulses, the duration of the start of formation delay is in the range: 1085-11.

Unlike the known device, the claimed former has a new composition of elements and a new organization of communication between them, which provide new technical properties.

The technical result is the simplification of the structure of the former, as well as the expansion of its functional capabilities and field of use by ensuring the delay of the start of formation relative to the start signal.

Claims (1)

USEFUL MODEL FORMULA A generator of a periodic sequence of pulses with adjusted time parameters, which contains: a common power source (JE); inverting binary counter configured for subtraction mode with synchronous parallel load enable input and feed inputs From the loaded variables (which ensure the setting of the shaper to the given time parameters of the output pulses), the input of the permission of the counting mode and the input of the asynchronous installation in the zero state, the overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input element OR; a chain consisting of a resistor and a capacitor connected in series, connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second the input of the second element AND is connected to the output of the two-input element OR, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous setting of the counter in the zero state; the inverter input is connected to the overflow output of the counter and the output to its count mode enable input, the clock input of the counter forms the input of a shaper which receives a continuous periodic train of pulses from the output of an external crystal oscillator, which differs in that introduced: the input of the asynchronous unit the first trigger to a single state; the second trigger with the inputs of the asynchronous installation in the zero and one state; four-bit digital comparator; the third and fourth elements of I; four-input element OR; second inverter; the first and second buttons that work for shorting: the second, third and fourth resistors, the first outputs of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output of the third resistor is connected to the input of the asynchronous installation of the first trigger in the single state and the first contact of the first button; the second output of the fourth resistor is connected to the second input of the first element I and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the outputs of the second, third and fourth digits of the counter are connected to the last inputs of the four-input OR element; the output of a four-input element OR connected to the first input of the third element AND, to the input of the unit in the single state of the second trigger; the second input of the third element And is connected to the input of the installation in the zero state of the second trigger and the overflow output of the counter; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; the AB output of the digital comparator, which forms the output of the shaper, is connected to the second input of the first OR element; when setting up the generator to form a periodic sequence, the duration of which pulses is equal to three periods of clock pulses, the period of passage is equal to nine periods of clock pulses, and the start of formation is delayed relative to the start pulse by ten periods, the first input of parallel loading of the counter is connected to the direct output of the second trigger, the second input of the counter parallel loading is connected to the inverse output of the second trigger, the third input is connected to the logic zero level, the fourth input is connected to the logic one level; the first and fourth inputs of the second group of comparator inputs are connected to the logical zero level, the second and third inputs of the second group of comparator inputs are connected to the logical unit level; the first and third control inputs of the comparator are connected to the logical zero level, the second control input is connected to the logical unit level. ; ! And Iv; B I she men t h i sha ny NIS m. BT 2 in YN E za i IC ti i i » i i U vini Y s i s te pe c ! ! Kk Ba «E E nn Y BUT y i - 1 yaru E y Not a thing a Em Z A 1 I Vl SHY xx shsh- p : but AH p. z zi. and CUBES IN | : ! ; write: ni shk rogu pen! ! | from the magma of SHI. : vo ) ooasofravovayuy Z. pdy and E E Z re which SHO Her KA Dy she she | me too at In 4th from EX. and. V E V so Y KE Fig. 1