UA137613U - PERIODIC SEQUENCE PULSE FORMER WITH ADJUSTABLE TIME PARAMETERS - Google Patents

Abstract

The periodic pulse generator with reconfigured time parameters includes a reversible binary counter having a clock input input C, a summation / subtraction mode setting input U, a synchronous parallel loading permission input L, and a data input input when loading, input, asynchronous setting to zero state R, overflow output P4; the first and second triggers with the inputs of the asynchronous zero zero R and one S; a four-bit digital comparator having a first group of inputs, a second group of inputs and a first, second, third control inputs I; the first, second, third two-input elements I; two-input element OR; four-input element OR; first and second inverters; first, second, third and fourth resistors; Start and Stop buttons that work on the circuit; capacitor.

Description

The shaper belongs to the pulse technology and is designed for the formation of a periodic sequence with a programmable duration of pulses, a period of passage and a delay of the start of formation relative to the starting pulse, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of an external quartz generator.

There are well-known generators that contain a set crystal oscillator operating in continuous mode, a synchronization device and an output device that ensures the formation of the necessary series of pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Clock generator. A.S. USSR Mo 307502. - B.V. May 20, 1971;

Clock generator. AS USSR Mo 354544. - BV Mo 30, 1972).

The disadvantage of known devices is limited functionality due to setting the time parameters of the output sequence of pulses to a fixed mode.

Known generators of a periodic sequence of pulses with programmable duration and fixed spacing (Ukraine patents for utility model 62517, 62519, 62520, 62522, 62525). The disadvantage of these devices is the complexity of their manufacture and, as a result, high power consumption and high cost, which are due to the need to use two reversible counters.

The closest in terms of technical essence and the achieved result is a pulse generator (patent for a utility model of Ukraine Mo 61886, Bull. Mo 14, 2011), which contains a common power source (E); reversible binary counter configured for the subtraction mode, with the input of enabling synchronous parallel loading and the inputs of supplying variables to be loaded (provide the adjustment of the shaper to the given time parameters of the output pulses), the input of enabling the counting mode and the input of asynchronous installation in the zero state, the overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; first and second AND elements: a two-input OR element consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to the first inputs of the first and second AND elements, the output of the first AND element is connected to the input asynchronous setting of the trigger to the zero state, the second input of the second element AND is connected to the output of the first OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous setting of the counter to the zero state; the inverter input is connected to the overflow output of the counter, and the output is connected to its count mode enable input, the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of an external crystal oscillator.

The disadvantage of the known device is limited functionality.

The basis of the useful model is the task of expanding the functionality of the periodic pulse sequence generator.

The task is solved by the fact that in the pulse generator, which contains a common power source (PE); reversible binary counter configured for the subtraction mode, with an input for enabling synchronous parallel loading and inputs for supplying loaded variables (which ensure the setting of the shaper to the given time parameters of the output pulses), an input for enabling the counting mode and an input for asynchronous installation in the zero state, an overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input element OR; a chain consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second the input of the second element AND is connected to the output of the first OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous setting of the counter in the zero state; the inverter input is connected to the overflow output of the counter, and the output is connected to its count mode enable input, the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of an external crystal oscillator, according to the utility model, the input of the first flip-flop asynchronous setup is introduced in a single state; the second trigger with the inputs of the asynchronous installation in the zero and one state; four-bit digital comparator; the third element I; four-input element OR; second inverter; the first and second buttons that work for closing; the second, third and fourth resistors, the first terminals of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output of the third resistor is connected to the input of the asynchronous trigger unit in the single state and the first contact of the first button; the second output of the fourth resistor is connected to the second input of the first element AND! and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the outputs of the second, third and fourth digits of the counter are connected to the last inputs of the four-input OR element; the output of which is connected to the first input of the third element I, with the input of the unit in the single state of the second trigger; the second input of the third element And is connected to the input of the installation in the zero state of the second trigger and the overflow output of the counter; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; the output A»B of the digital comparator, which forms the output of the shaper, is connected to the second input of the first OR element; when setting the shaper to form a periodic sequence, the pulse duration of which is equal to three periods of clock pulses, the period of passage is equal to nine periods of clock pulses, and the start of formation is delayed relative to the start pulse by five periods, the first input of parallel loading of the counter is connected to the level logical unit, the second input is connected to the logical zero level, the third input is connected to the inverse output of the second flip-flop; the fourth input is connected to the direct output of the second trigger; the second and third inputs of the second group of comparator inputs are connected to the logic unit level; the first and third control inputs of the comparator are connected to the logical zero level, the second control input is connected to the logical unit level.

In Fig. 1 shows the scheme of the former. In Fig. 2 shows the graph of transitions of the shaper, consisting of three rings, the upper (first) ring is the graph of transitions of trigger 2, the second ring is the value of the signals at the output of the shaper, the third ring is the graph of transitions of the counter with a common vertex corresponding to the zero state of the counter and triggers, and in Fig. . From are shown graphs illustrating the work for a given configuration option.

The generator contains a reversible binary counter 1, which has an input for supplying clock pulses C, an input for setting the summation/subtraction mode Ш, an input for enabling synchronous parallel loading И and inputs for supplying data when loading бо, О:, ХО2, Оз, an input for enabling the counting mode EE , the input of the asynchronous installation to the zero state B, the overflow output Py; the first 2 and the second Z triggers with the inputs of the asynchronous setting of zero NC and unit 5; four-bit digital comparator 4, which has the first group of inputs Ao, Ach, A», Az, the second group of inputs Vo, Vi, B2, Vz; the first, second, third control inputs I; the first 5, the second 6 and the third 7 two-input elements I; two-input element OR 8; four-input element OR 9; the first 10 and the second 11 inverters; the first NI1 12, the second Na2 13, the third VAZ 14 and the fourth NA 15 resistors; buttons stage 16 and or 17, working for closing; capacitor C1 18.

The first outputs of the resistors are connected to the plus of the power source (-7E), the second output of the resistor 13 forms the output of the level of the logical unit "1". The second output of the resistor 14 is connected to the input of the asynchronous installation of the trigger 2 in the single state and the first contact of the button ia. The second output of the resistor 15 is connected to the input of the element 5 and the first contact of the bor button. The second contacts of the buttons are connected to the common point of the power source (-E). The input of the inverter 11 is connected to the output of the first (Fo) digit of the counter, and its output is connected to the first input of element 9.

The outputs C 002 Oz of the counter are connected to the last inputs of the element 9. The output of the element 9 is connected to the input of the element 7 and the input 5 of the trigger 3. The second input of the element 7 is connected to the input B of the trigger C and the overflow output of the counter 1.

Input bo, parallel loading counter 1 is connected to the level of the logical unit. "17. . schu . (oh)

OO input: connected to logic zero level "0". The input ХО»2 is connected to the inverse output of trigger 3. The input Oz is connected to the direct output (O2) of trigger 3.

The first group of comparator inputs (Ao, At, Ag, Az) is connected to the outputs of the corresponding digits (up to C: 2 Oz) of the counter. The output AB of the comparator is connected to the second input of element 8, the first

Vo and the fourth Vz inputs of the second group of comparator inputs are connected to the logical zero level "0" (with the minus of the power source), the second V. and the third V»e - to the logical unit level (with the second terminal "1" of resistor 13 (VzV2V :Vo-0110).The first and third control inputs (I) of the comparator are connected to the logic zero level "0", the second control input is connected to the logic one level "1".

The former works in the following sequence.

The presence of a circuit consisting of a resistor 12 connected in series and a capacitor 18 connected to the XE supply voltage bus, when the power source is turned on for a certain period of time (determined by the time constant of the circuit EB: Si) forms a logic zero level at the inputs of elements 5, b, ensuring the formation of a logical zero level at their outputs connected to the input of the asynchronous installation in the zero state of trigger 2 and counter 1. After the transition process associated with turning on the power source, trigger 2 and counter 1 go to the zero state, forming a logical zero level respectively: at the exit

A" of the comparator, at the output of trigger Z and at the overflow outputs of counter 1, which leads to the formation of a logical zero level at the input EB of trigger 4 (ensuring its zero state), at the output of element 8, which ensures confirmation (blocking) of the logical zero level on at its output and at the end of the transition process associated with the charge of capacitor 18, when the voltage on it will exceed the level of logical zero, which ensures the level of logical zero at input A of counter 1. Since the mode of asynchronous setting of the counter to the zero state has priority in relation to all other modes, then as long as the logical zero level remains at the inputs of element 8 (and, therefore, at its output), the zero state of counter 1 and triggers 2, C will remain unchanged.

When the trigger pulse (siap) arrives at input 5 of flip-flop Z, its transition to a single state (0-1) occurs, forming the level of a logical unit at the output of element 9, and therefore at the input and output of element b, forming the level of a logical unit at the input of the counter 1, unlocks the zero state, and then a zero value on the synchronous parallel load enable input of counter 1 prepares it to receive information from its inputs

Oz020100-0101-5.

Upon arrival of the first (after the end of the transient process associated with the start) clock pulse C, parallel loading occurs along its front, counter 1 goes into state Oz0020100-0101-5. As a result of this transition, a single value is formed at the overflow output of counter 1 and the output of element 7, and a zero value is formed at the output of inverter 11 (at input E of counter 1), which leads to the prohibition of parallel loading and the permission of the counting mode of counter 1. Initial (zero) state trigger 2 and the zero value of the signal at the output of the shaper remains unchanged.

When the following clock pulses arrive, the content of counter 1 decreases. At the same time, as long as the content of counter 1 exceeds a single value, the zero value at the output of element 10 and at the direct output of trigger 2 will remain unchanged, which ensures the invariance of the zero value at the outputs of the shaper.

As soon as the content of counter 1 becomes equal to 0001, a logical zero level is formed at the output of element 10, which leads to the formation of a logical zero level at the input of element 7 (at the enable input of counter 1 and at input 5 of trigger 3, which leads to its transition to a single state, And then upon arrival of the next (seventh) clock pulse, counter 1 goes into the state determined by the value of the signals generated at its inputs

From parallel loading (O3020100-1001), which leads to the beginning of the formation of a single value at the output of the generator.

When the following clock pulses arrive, the content of counter 1 decreases. At the same time, as long as its content exceeds the value set at the inputs of the second comparator group (VzV2V1Vo-0110), the value of the signal at the output of the generator will remain equal to 1. As soon as the content of counter 1 becomes equal to 0110, the value of the signal at the output of the generator will become equal to 0. When the next clock pulses arrive, the content of counter 1 continues to decrease, and the value of the signal at the output will remain equal to 0 until the content of the counter becomes equal to 0001. As soon as counter 1 goes to the state 0001, at the output of elements 10, 7 and a logical zero level is formed at the load enable input of counter 1. When the next clock pulse arrives, counter 1 again goes to state 1001, forming a single value at the output. When subsequent clock pulses arrive, the processes are repeated.

Thus, after the end of the transient process associated with the start-up, when entering the input of the generator of a periodic sequence of pulses (with a period equal to T), a periodic sequence of pulses is generated at the output of the generator, a multiple of the period of clock pulses, the time parameters of which are the duration of the pulse З3Т, duration of pause 1-67, duration of the delay of the start of formation relative to the starting pulse Х-5тТ, period of passing Те-9т.

The output sequence formation mode is stopped by pressing the bor button, which forms a logical zero level at input A of trigger 2, which leads to its transition to the zero state (01-00). The moment of pressing is asynchronous in relation to the pulses of the clock generator and to the state of counter 1 and triggers 2, 3. If at the moment of pressing the content of counter 1 is less than or equal to 0110, then when the trigger goes to the zero state, a level will be formed at the inputs of element 9 and at its output of logic zero, causing the level of zero at the input and output of element 6, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the generation mode.

If at the moment of pressing the button 5 and the content of the counter 1 is greater than 0110, then when the trigger 2 goes to the zero state, the unit value at the output of element 9 will remain unchanged, since the output of comparator 4 is the level of a logical unit. It follows from this that in this case, at the moment of arrival of clock pulses, the termination of generation will not occur, thereby preventing the distortion of the last pulse in the generated output sequence.

When each successive pulse arrives at the input of the shaper C, the transition of counter 1 will take place according to the algorithm until its content becomes equal to 0110, causing a zero level at the input and output of element 6, which will lead to the transition of counter 1 to the zero state, and therefore, before the termination of the generation mode. With the arrival of the next pulse that triggers the bat, all processes are repeated.

Since the moment of pressing the button 5iagi is asynchronous with respect to the clock pulses, the duration of the delay of the start of formation is in the range: 5T "56.

The technical result is the simplification of the structure of the former, as well as the expansion of its functional capabilities and scope of use by providing a delay in the start of formation relative to the start signal.

Claims (1)

USEFUL MODEL FORMULA A periodic pulse sequence generator with adjustable time parameters, which contains a common power source (SP); reversible binary counter configured for subtraction mode, with synchronous parallel loading enable input and loading variable supply inputs, count mode enable input and asynchronous set-to-zero input, overflow output; inverter; trigger with the input of the asynchronous installation in the zero state; the first and second elements of I; two-input element OR; a chain consisting of a series-connected resistor and a capacitor connected to a power source, the common point of which is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the input of the asynchronous installation of the trigger in the zero state, the second the input of the second element AND is connected to the output of the first OR element, the first input of which is connected to the output of the trigger, the output of the second element AND is connected to the input of the asynchronous setting of the counter in the zero state; the inverter input is connected to the overflow output of the counter, and the output to its count mode enable input, the clock input of the counter forms the input of the shaper, which receives a continuous periodic sequence of pulses from the output of an external crystal oscillator, which differs in that the input of the asynchronous unit of the first the trigger in the single state; the second trigger with the inputs of the asynchronous installation in Zo zero and one state; four-bit digital comparator; the third element I; four-input element OR; second inverter; the first and second buttons that work for closing; the second, third and fourth resistors, the first terminals of which are connected to the plus of the power source; the second output of the second resistor forms the output of the logical unit level; the second output of the third resistor is connected to the input of the asynchronous trigger unit in the single state and the first contact of the first button; the second output of the fourth resistor is connected to the second input of the first element I and the first contact of the second button; the second contacts of the buttons are connected to the common point (minus) of the power source; the input of the second inverter is connected to the output of the first (junior) digit of the counter, and its output is connected to the first input of the four-input OR element; the outputs of the second, third and fourth digits of the counter are connected to the last inputs of the four-input OR element; the output of the four-input element OR is connected to the first input of the third element AND, with the input of the unit in the single state of the second trigger; the second input of the third element AND! connected to the input of the installation in the zero state of the second trigger and the overflow output of the counter; the first group of comparator inputs is connected to the outputs of the corresponding counter digits; the AB output of the digital comparator, which forms the output of the shaper, is connected to the second input of the first OR element; when setting the shaper to form a periodic sequence, the pulse duration of which is equal to three periods of clock pulses, the period of passage is equal to nine periods of clock pulses, and the start of formation is delayed relative to the start pulse by five periods, the first input of parallel loading of the counter is connected to the level logical unit, the second input is connected to the logical zero level, the third input is connected to the inverse output of the second flip-flop; the fourth input is connected to the direct output of the second trigger; the second and third inputs of the second group of comparator inputs are connected to the logic unit level; the first and third control inputs of the comparator are connected to the logical zero level, the second control input is connected to the logical unit level. vch A g I, nn od feny); - | not ЕЯ and Е and: У ЯК nya Щ and sredi |: g shke у. in Z Ko TD dh SHE SN sh - 16 ma 1 ! What a dream! 4 me! х и выш з шо ИЙ з E ХСХ см тес у шк ие КД Ше ЯК; p hi | what sat | ! axes ) Fig. 1 pk vnOu dosia proukr" what; 0 C non nnokOonKoE non ONKO StT Fig. 2 soch "you NEW THERE GAVE THIS LAT. 11 11111101 11 11021111: EMAASANH ZAZNA NN ZNA NINI ZAV NICNN NI NI ZLE VN PAZAMI Z. Z SIGNS NN WE KNOW ni nn nn nn don nn V she: 11111111 for etude in EDEM ME MDE DE VENI YOU A V KE NI M VE EE UZ z znen m zn osvi ni nn Z pi i pi ni pis mi yy ni mir m ni malo ETO u z MNE V OV NI EE VE NE MEN ENN V NI MEN PENYA EK Ve KE HE RECOGNIZE THE FASASZNEIEIK WIFE K nyvy mi r o i o v ME VE nyny nnnyny nyny shi shishen WE SNEKEKENSNY KOSI DESIRABLE KA: MEN MEDY ME Mk NO MNN S si o Z si NN Fig. WITH