TWM641162U - Pin and lead frame - Google Patents
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- TWM641162U TWM641162U TW111207803U TW111207803U TWM641162U TW M641162 U TWM641162 U TW M641162U TW 111207803 U TW111207803 U TW 111207803U TW 111207803 U TW111207803 U TW 111207803U TW M641162 U TWM641162 U TW M641162U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
- Insulation, Fastening Of Motor, Generator Windings (AREA)
Abstract
本公開實施例提供一種引腳及引線框架,所述引腳包括:內引腳部,所述內引腳部適於與晶片連接;外引腳部,所述外引腳部適於與電路板連接;所述內引腳部和所述外引腳部之間通過彎折部連接;所述引腳包括使用時遠離電路板的第一側和與所述第一側相對的第二側;其中,所述內引腳部與所述彎折部的連接處在所述第一側包括第一臺階,所述第一臺階包括第一縱向壁和與所述第一縱向壁連接的第一橫向面,所述第一縱向壁與所述內引腳部相鄰接,所述第一縱向壁與所述內引腳部的第一側的夾角範圍為70°~90°。包括所述引腳的引線框架在封裝過程中,可以為所述內引腳部與晶片的鍵合提供更大的引線鍵合區面積,方便鍵合。 An embodiment of the present disclosure provides a lead and a lead frame, the lead includes: an inner lead part, the inner lead part is suitable for connecting with a chip; an outer lead part, the outer lead part is suitable for connecting with a circuit board connection; the inner pin part and the outer pin part are connected through a bending part; the pin includes a first side away from the circuit board and a second side opposite to the first side when in use ; Wherein, the connection between the inner pin portion and the bent portion includes a first step on the first side, and the first step includes a first longitudinal wall and a first longitudinal wall connected to the first longitudinal wall On a transverse plane, the first longitudinal wall is adjacent to the inner pin portion, and the included angle between the first longitudinal wall and the first side of the inner pin portion is 70°-90°. During the packaging process of the lead frame including the pins, a larger area of the wire bonding area can be provided for the bonding of the inner pin part and the chip, so as to facilitate bonding.
Description
本公開涉及半導體封裝技術領域,具體涉及一種引腳及引線框架。 The present disclosure relates to the technical field of semiconductor packaging, in particular to a pin and a lead frame.
本創作要求於2021年07月20日提交中國專利局、申請號為202121660220.9、新型名稱為“一種引腳及引線框架”的中國專利申請的優先權,其全部內容通過引用結合在本申請中。 This creation claims the priority of the Chinese patent application with the application number 202121660220.9 and the new name "a pin and lead frame" submitted to the China Patent Office on July 20, 2021, the entire contents of which are incorporated in this application by reference.
近年來,隨著電子技術的高速發展,對半導體封裝中可靠性的要求日益增加。雙邊扁平無引腳封裝(Dual Flat No-lead Package,DFN封裝)是一種用於表面貼裝的無引腳封裝技術,用DFN封裝的產品具有體積小、重量輕、適合可擕式應用的特點,且封裝後的結構具有優異的電性能和熱性能。所以,DFN封裝在少引腳類型的封裝中被廣泛採用。 In recent years, with the rapid development of electronic technology, the requirements for reliability in semiconductor packaging have been increasing. Dual Flat No-lead Package (DFN package) is a leadless package technology for surface mount. The products packaged with DFN have the characteristics of small size, light weight and suitable for portable applications. , and the packaged structure has excellent electrical and thermal properties. Therefore, the DFN package is widely used in the package with few pins.
DFN封裝體包括引線框架,引線框架上設有引腳。在封裝過程中,需將引線框架的內引腳部和晶片連接。然而,當前DFN封裝所用的引線框架的引腳部的引線鍵合區面積過小。 The DFN package includes a lead frame on which pins are arranged. In the packaging process, it is necessary to connect the inner lead part of the lead frame to the chip. However, the area of the wire bonding area of the lead portion of the lead frame used in the current DFN package is too small.
為了解決現有技術中存在的問題,本公開實施例提供一種引腳及引線框架,能夠在晶片封裝時提供充足的引線鍵合區面積。 In order to solve the problems existing in the prior art, an embodiment of the present disclosure provides a pin and a lead frame, which can provide a sufficient area of the wire bonding area during chip packaging.
為解決上述技術問題,本公開實施例提供一種引腳,包括:內引腳部,所述內引腳部適於與晶片連接;外引腳部,所述外引腳部適於與電路板連接;所述內引腳部和所述外引腳部之間通過彎折部連接;所述引腳包括使用時遠離電路板的第一側和與所述第一側相對的第二側;其中,所述內引腳部與所述彎折部的連接處在所述第一側包括第一臺階,所述第一臺階包括第一縱向壁和與所述第一縱向壁連接的第一橫向面,所述第一縱向壁與所述內引腳部相鄰接,所述第一縱向壁與所述內引腳部的第一側的夾角範圍為70°~90°。 In order to solve the above technical problems, an embodiment of the present disclosure provides a pin, including: an inner pin part, the inner pin part is suitable for connecting with a chip; an outer pin part, and the outer pin part is suitable for connecting with a circuit board connection; the inner pin part and the outer pin part are connected through a bending part; the pin includes a first side away from the circuit board and a second side opposite to the first side when in use; Wherein, the connection between the inner pin portion and the bent portion includes a first step on the first side, and the first step includes a first longitudinal wall and a first vertical wall connected to the first longitudinal wall. In the transverse plane, the first longitudinal wall is adjacent to the inner pin portion, and the included angle between the first longitudinal wall and the first side of the inner pin portion is 70°-90°.
在一些實施例中,所述第一縱向壁的高度為0.03mm~0.20mm;所述第一縱向壁與所述第一橫向面之間的夾角範圍為90°~110°。 In some embodiments, the height of the first longitudinal wall ranges from 0.03mm to 0.20mm; the angle between the first longitudinal wall and the first transverse surface ranges from 90° to 110°.
在一些實施例中,所述第一橫向面的長度不超過0.1mm。 In some embodiments, the length of the first transverse face does not exceed 0.1 mm.
在一些實施例中,所述第一橫向面與所述彎折部在所述第一側通過第一圓弧連接。 In some embodiments, the first transverse surface and the bent portion are connected at the first side by a first arc.
在一些實施例中,所述第一圓弧的曲率半徑不超過所述引腳的厚度。 In some embodiments, the radius of curvature of the first arc does not exceed the thickness of the pin.
在一些實施例中,所述外引腳部與所述彎折部的連接處在所述第二側包括第二臺階,所述第二臺階包括第二縱向壁和與所述第二縱向壁連接的第二橫向面,所述第二縱向壁與所述外引腳部相鄰接,所述第二縱向壁與所述外引腳部的第二側的夾角範圍為70°~90°。 In some embodiments, the junction of the outer pin portion and the bent portion includes a second step on the second side, and the second step includes a second longitudinal wall and a second longitudinal wall. The connected second transverse surface, the second longitudinal wall is adjacent to the outer pin part, and the included angle between the second longitudinal wall and the second side of the outer pin part is 70°~90° .
在一些實施例中,所述第二縱向壁的高度為0.03mm~0.20mm;所述第二縱向壁與所述第二橫向面之間的夾角範圍為90°~110°。 In some embodiments, the height of the second longitudinal wall is 0.03mm-0.20mm; the angle between the second longitudinal wall and the second transverse surface is in the range of 90°-110°.
在一些實施例中,所述第二橫向面的長度不超過0.1mm。 In some embodiments, the length of the second transverse face does not exceed 0.1 mm.
在一些實施例中,所述第二橫向面與所述彎折部在所述第二側通過第二圓弧連接。 In some embodiments, the second transverse surface and the bent portion are connected at the second side by a second arc.
在一些實施例中,所述第二圓弧的曲率半徑不超過所述引腳的厚度。 In some embodiments, the radius of curvature of the second arc does not exceed the thickness of the pin.
進一步的,本公開實施例還提供一種引線框架,包括如上任一實施例所述的引腳。 Further, an embodiment of the present disclosure also provides a lead frame, including the pin as described in any one of the above embodiments.
與現有技術相比,本公開實施例的技術方案具有以下有益效果:本公開實施例提供了一種引腳及引線框架,所述引腳通過在內引腳部與彎折部之間設置第一臺階,可以避免由於引線框架成型工藝而導致的彎折部曲率半徑過大,從而可以提供更大的引線鍵合區面積,方便引線框架內引腳部與晶片的鍵合。 Compared with the prior art, the technical solutions of the embodiments of the present disclosure have the following beneficial effects: The embodiments of the present disclosure provide a pin and a lead frame, and the pin is arranged between the inner pin part and the bending part by first The steps can avoid the excessively large curvature radius of the bending part caused by the lead frame molding process, thereby providing a larger area of the wire bonding area and facilitating the bonding of the lead part in the lead frame and the chip.
進一步地,本公開實施例,在外引腳部與彎折部之間設置第二臺階,可以避免現有技術中外引腳部與彎折部的連接處在注塑過程中產生溢膠的風險。 Further, in the embodiment of the present disclosure, the second step is provided between the outer pin portion and the bending portion, which can avoid the risk of glue overflow at the connection between the outer pin portion and the bending portion in the prior art during the injection molding process.
10:引線框架 10: Lead frame
12:基島 12: Key Island
13:導線 13: wire
14:晶片 14: Wafer
15:框架基板 15: Frame substrate
16:基島連筋 16: Jijima Connected Ribs
17:基島臺階 17: Base Island Steps
18:V型槽 18: V-groove
20:引腳 20: Pin
201:內引腳部 201: Inner pin part
202:外引腳部 202: External pin part
203:彎折部 203: bending part
204:第一臺階 204: The first step
2041:第一縱向壁 2041: First longitudinal wall
2042:第一橫向面 2042: first transverse plane
2043:第一圓弧 2043: The first arc
205:第二臺階 205: The second step
2051:第二縱向壁 2051: Second longitudinal wall
2052:第二橫向面 2052: second transverse plane
2053:第二圓弧 2053: Second arc
206:電路板的第一側 206: First side of circuit board
207:電路板的第二側 207: Second side of the board
31:上模件 31: upper module
32:下模件 32: Lower module
本創作的其它特徵以及優點將通過以下結合圖式詳細描述的可選實施方式更好地理解,圖式中相同的標記表示相同或相似的部件,其中:圖1為現有技術中一種引腳形成的過程示意圖;圖2為現有技術中一種引線框架與晶片相連的結構示意圖; 圖3為本公開一實施例的引腳結構示意圖;圖4為圖3所示實施例中引腳的第一臺階處的局部放大結構示意圖;圖5為本公開又一實施例的引腳結構示意圖;圖6為圖5所示實施例中引腳的第二臺階處的局部放大結構示意圖;圖7為本公開另一實施例的引線框架的結構示意圖;圖8為圖7所示實施例的A-A剖面示意圖。 Other features and advantages of this creation will be better understood through the following optional embodiments described in detail in conjunction with the drawings, the same symbols in the drawings represent the same or similar components, wherein: Figure 1 is a pin formation in the prior art The schematic diagram of the process; Fig. 2 is the structural schematic diagram that a kind of lead frame is connected with chip in the prior art; Fig. 3 is a schematic diagram of the pin structure of an embodiment of the present disclosure; Fig. 4 is a schematic diagram of a partially enlarged structure of the first step of the pin in the embodiment shown in Fig. 3; Fig. 5 is a schematic diagram of the pin structure of another embodiment of the present disclosure Schematic diagram; FIG. 6 is a partially enlarged structural schematic diagram of the second step of the pin in the embodiment shown in FIG. 5; FIG. 7 is a schematic structural diagram of a lead frame according to another embodiment of the present disclosure; FIG. 8 is a schematic diagram of the embodiment shown in FIG. 7 A-A cross-sectional schematic diagram.
目前在製備引線框架過程中,需要將其引腳彎折成3D形狀,具體請參照圖1,引線框架的內引腳部與外引腳部之間的彎折部是通過在上模件31和下模件32之間擠壓成型的。由於引線框架為金屬材料,在成型過程中會發生塑性變形,彎折部會形成圓弧狀。
At present, in the process of preparing the lead frame, the pins need to be bent into a 3D shape. Please refer to FIG. 1 for details. Extruded between the
然後,當通過導線13將引線框架10和晶片14封裝在一起時,如圖2所示,由於引腳20彎折部的圓弧區域過大,會導致內引腳部的引線鍵合區面積過小,不方便鍵合。
Then, when the
因此,本公開實施例提供了一種引腳及引線框架,在晶片封裝過程中,可以為引線框架的內引腳部與晶片的連接提供充足的引線鍵合區面積。 Therefore, the embodiments of the present disclosure provide a pin and a lead frame, which can provide a sufficient area of the wire bonding area for the connection between the inner pin portion of the lead frame and the chip during the chip packaging process.
為使本公開的目的、技術方案及效果更加清楚、明確,以下參照圖式並結合優選的實施例對本公開進一步詳細說明。應當理解,此處所描述的具體實施例僅用以解釋本公開,並不用於限定本公開的保護範圍。 In order to make the purpose, technical solutions and effects of the present disclosure clearer and more specific, the present disclosure will be further described in detail below with reference to the drawings and in combination with preferred embodiments. It should be understood that the specific embodiments described here are only used to explain the present disclosure, and are not intended to limit the protection scope of the present disclosure.
本公開實施例提供了一種引腳,所述引腳是引線框架的一部分,用於將晶片與電路板進行電學連接。由於所述晶片與所述電路板不在同一平面上,所以需要對所述引線框架的引腳進行3D彎折。 An embodiment of the present disclosure provides a lead, which is a part of a lead frame, and is used for electrically connecting a chip to a circuit board. Since the wafer and the circuit board are not on the same plane, it is necessary to perform 3D bending on the leads of the lead frame.
具體請參照圖3,所述引腳20包括:內引腳部201,所述內引腳部201適於與晶片連接;外引腳部202,所述外引腳部202適於與電路板連接;所述內引腳部201和所述外引腳部202之間通過彎折部203連接;所述引腳20包括使用時遠離電路板的第一側206和與所述第一側206相對的第二側207。
Please refer to Fig. 3 for details, the
在一些實施例中,所述引腳的厚度範圍為0.10mm~0.40mm,所述引腳的材質可以為銅合金。例如,C194銅材或C7025銅材等。 In some embodiments, the thickness of the pins ranges from 0.10 mm to 0.40 mm, and the material of the pins may be copper alloy. For example, C194 copper or C7025 copper, etc.
在圖3所示的實施例中,所述內引腳部201與所述彎折部203的連接處在所述第一側206包括第一臺階204。
In the embodiment shown in FIG. 3 , the connection between the
所述第一臺階204的局部放大結構示意圖,即圖3中虛線框內部分的結構示意圖如圖4所示,所述第一臺階204包括第一縱向壁2041和與所述第一縱向壁2041連接的第一橫向面2042,所述第一縱向壁2041與所述內引腳部201相鄰接,所述第一橫向面2042與所述彎折部203相鄰接。
The partially enlarged structural schematic diagram of the
在上述實施例中,所述內引腳部201的第一臺階204可以保證在所述內引腳部201與彎折部203之間的彎折程度不發生改變的前提下,增加引線鍵合區的面積,方便所述內引腳部201與晶片的鍵合。
In the above embodiment, the
在一些實施例中,所述第一縱向壁的高度可以為0.03mm~0.20mm,所述第一縱向壁與所述內引腳部的第一側之間的夾角範圍可以為70°~90°。 In some embodiments, the height of the first longitudinal wall may be 0.03 mm to 0.20 mm, and the angle between the first longitudinal wall and the first side of the inner pin portion may range from 70° to 90°. °.
在一些實施例中,所述第一橫向面的長度不超過0.1mm,所述第一縱向壁與所述第一橫向面之間的夾角範圍可以為90°~110°。 In some embodiments, the length of the first transverse plane is no more than 0.1 mm, and the angle between the first longitudinal wall and the first transverse plane may range from 90° to 110°.
在圖4所示的實施例中,所述第一橫向面2042與所述彎折部203在第一側206通過第一圓弧2043連接。
In the embodiment shown in FIG. 4 , the first transverse surface 2042 is connected to the
在一些實施例中,所述第一圓弧的曲率半徑不超過所述引腳的厚度。 In some embodiments, the radius of curvature of the first arc does not exceed the thickness of the pin.
在一些實施例中,具體請參照圖5,所述外引腳部202與所述彎折部203的連接處在所述第二側207包括第二臺階205。
In some embodiments, referring to FIG. 5 for details, the connection between the
所述第二臺階205的局部結構示意圖,即圖5中虛線框內部分的結構示意圖如圖6所示,包括第二縱向壁2051和與所述第二縱向壁2051連接的第二橫向面2052,所述第二縱向壁2051與所述外引腳部202相鄰接,所述第二橫向面2052與所述彎折部203相鄰接。
The partial structural schematic diagram of the
在上述實施例中,所述外引腳部202的第二臺階205可以在不改變所述外引腳部202與彎折部203之間彎折程度的前提下,使所述引線框架靠近電路板的一側,即第二側207非常接近為平面,在密封注塑時,所述外引腳部202可以與注塑下模面緊密貼合,以降低密封樹脂的滲漏風險。
In the above embodiment, the
在一些實施例中,所述第二縱向壁的高度為0.03mm~0.20mm,所述第二縱向壁與所述外引腳部的第二側之間的夾角範圍可以為70°~90°。 In some embodiments, the height of the second longitudinal wall is 0.03mm~0.20mm, and the angle range between the second longitudinal wall and the second side of the outer pin part can be 70°~90° .
在一些實施例中,所述第二橫向面的長度不超過0.1mm,所述第二縱向壁與所述第二橫向面之間的夾角範圍可以為90°~110°。 In some embodiments, the length of the second transverse plane is no more than 0.1 mm, and the angle between the second longitudinal wall and the second transverse plane may range from 90° to 110°.
在圖6所示的實施例中,所述第二橫向面2052與所述彎折部203在第二側207通過第二圓弧2053連接。
In the embodiment shown in FIG. 6 , the second
在一些實施例中,所述第二圓弧的曲率半徑不超過所述引腳的厚度。 In some embodiments, the radius of curvature of the second arc does not exceed the thickness of the pin.
本公開還提供了一種引線框架,包括前述任一實施例所述的引腳。 The present disclosure also provides a lead frame, including the pin described in any one of the foregoing embodiments.
作為一個具體的實施例,如圖7所示,所述引線框架10包括引腳20,適於為晶片和電路板提供電學通路;以及基島12,適於為晶片提供機械支撐。具體的,所述基島12為凸台結構,通過在所述基島12遠離晶片的一側設置基島臺階17,使得所述基島12遠離電路板一側的面積大於所述基島12靠近電路板一側的面積,所述基島臺階17適於在密封時避免密封樹脂溢出並覆蓋所述基島12靠近電路板的一側;在所述基島12上還設有V型槽18,所述V型槽18適於避免晶片焊料溢出並爬往所述基島12的靠近電路板的一側,所述基島12通過兩根基島連筋16與框架基板15相連。所述引線框架10的引腳20又包括內引腳部和外引腳部,所述內引腳部適於在晶片封裝時通過導線與晶片連接;所述外引腳部適於將完成封裝工藝的封裝體與電路板通過焊料連接。
As a specific embodiment, as shown in FIG. 7 , the
其中,所述內引腳部201處設有第一臺階204,所述外引腳部202設有第二臺階205,具體請參照圖8,圖8示出了圖7所示的實施例中A-A剖面的結構示意圖,即第一臺階204及第二臺階205的結構示意圖。
Wherein, the
以上所述各實施例已揭示本公開的技術內容及技術特點,其描述較為具體和詳細,但上述實施方式的描述是示例性的不是限制性的,在本公開的構思下,本領域的普通技術人員可以對上述公開的構思作各種變化和改進,但都屬於本公開的保護範圍,因此,本公開的保護範圍由請求項所確定。 The above-mentioned embodiments have disclosed the technical content and technical characteristics of the present disclosure, and the descriptions are more specific and detailed, but the descriptions of the above-mentioned embodiments are illustrative and not restrictive. Under the concept of the present disclosure, ordinary people in the field Skilled persons can make various changes and improvements to the above-mentioned disclosed ideas, but all of them belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure is determined by the claims.
20:引腳 20: Pin
201:內引腳部 201: Inner pin part
202:外引腳部 202: External pin part
203:彎折部 203: bending part
204:第一臺階 204: The first step
206:電路板的第一側 206: First side of circuit board
207:電路板的第二側 207: Second side of the board
Claims (11)
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CN202121660220.9 | 2021-07-20 | ||
CN202121660220.9U CN215451396U (en) | 2021-07-20 | 2021-07-20 | Pin and lead frame |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN116613131A (en) * | 2023-06-02 | 2023-08-18 | 上海类比半导体技术有限公司 | Integrated circuit package frame |
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2021
- 2021-07-20 CN CN202121660220.9U patent/CN215451396U/en active Active
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CN116613131A (en) * | 2023-06-02 | 2023-08-18 | 上海类比半导体技术有限公司 | Integrated circuit package frame |
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