TWM611036U - Pixel structure - Google Patents

Abstract

A pixel structure having a transmitting region and a reflecting region and including a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a planarization layer, a pixel electrode and a fourth metal layer is provided. The first metal layer is disposed on the substrate and includes a plurality of first patterned areas and a first storage electrode. The first insulating layer is disposed on the substrate and covers the first metal layer. The second metal layer is disposed on the first insulating layer and includes a plurality of second patterned areas and a second storage electrode. The second insulating layer is disposed on the first insulating layer and covers the second metal layer. The planarization layer is disposed on the second insulating layer. The pixel electrode is electrically connected to the second metal layer by a contact window penetrating the second insulating layer and the planarization layer. The reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned areas. The third patterned areas substantially correspond an area which is an overlapped area of the first patterned areas and the second patterned areas in a normal direction of the substrate, so that the transmitting region is defined.

Description

Pixel structure

This new creation is about a pixel structure, and especially about a pixel structure used for a half-through display panel.

In the conventional semi-transmissive display panel, the way to define the penetration area is to select a specific area so that the reflective electrode, the first metal layer, and the second metal layer are removed in the specific area; however, , The first metal layer used to form the first storage electrode and the second metal layer used to form the second storage electrode will be removed by this way of defining the penetration area, resulting in a reduction in their area. Therefore, the way of defining the penetrating area will cause the storage capacitance in a pixel structure of the display panel to be reduced, thereby reducing the voltage stability of the display panel.

The present invention provides a pixel structure, which has a storage capacitor that can be upgraded to store a larger voltage, thereby having good electrical properties.

The pixel structure of an embodiment of the present invention has a penetration area and a reflection area, and includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a flat layer, and a pixel electrode And the reflective electrode. The first metal layer is disposed on the substrate and includes a plurality of first patterned regions and first storage electrodes. The first insulating layer is disposed on the substrate and covers the first metal layer. The second metal layer is disposed on the first insulating layer and includes a plurality of second patterned regions and second storage electrodes. The second insulating layer is disposed on the first insulating layer and covers the second metal layer. The flat layer is disposed on the second insulating layer. The pixel electrode is disposed on the flat layer and is electrically connected to the second metal layer through a contact window penetrating the second insulating layer and the flat layer. The reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned regions. The plurality of third patterned portions substantially correspond to the overlapping regions of the plurality of first patterned regions and the plurality of second patterned regions in the normal direction of the substrate, so as to define a penetration region.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the reflective electrode.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the first metal layer.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the second metal layer.

In an embodiment of the present invention, the above-mentioned pixel structure further includes a third metal layer disposed between the second insulating layer and the flat layer, wherein the penetration area is defined by the third metal layer.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the reflective electrode and the first metal layer.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the reflective electrode and the second metal layer.

In an embodiment of the present invention, the above-mentioned penetrating area is defined by the reflective electrode, the first metal layer, the second metal layer, and the third metal layer.

In an embodiment of the present invention, the above-mentioned pixel structure has a first gray-scale display area and a second gray-scale display area, the first gray-scale display area includes a first display area, and the second gray-scale display area The area includes two second display areas.

In an embodiment of the present invention, no other areas of the first metal layer used as the first storage electrode are removed when a plurality of first patterned regions are defined, and a plurality of second patterned regions are defined. No other areas of the second metal layer used as the second storage electrode are removed when the area is patterned.

Based on the above, the pixel structure created by the present invention prevents other areas of the first metal layer used as the first storage electrode from being removed when defining multiple first patterned areas, and defines multiple first patterned areas. In the second patterning area, the second metal layer used as the second storage electrode is not removed from other areas. The pixel structure created by the present invention does not reduce the first metal layer used to form the first storage electrode and the first metal layer used to form the second storage electrode. The area of the second metal layer of the two storage electrodes serves as a penetration area. In this case, the storage capacitor in one pixel structure of the display panel created by the present invention can be increased to store a larger voltage, thereby having good electrical properties.

The following will describe the creation of the new type more comprehensively with reference to the drawings of this embodiment. However, the new creation can also be embodied in a variety of different forms, and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, for example: up, down, left, right, front or back, etc., are only directions for referring to the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the creation of the new model.

FIG. 1A is a schematic top view of the pixel structure of the first embodiment of the new creation. Fig. 1B is a schematic cross-sectional view of the section line A-A' in Fig. 1A. FIG. 1C is a schematic diagram of the penetration area and the reflection area of the pixel structure of the first embodiment of the new creation.

1A, 1B and 1C, the pixel structure 10 of this embodiment includes a substrate SB, a first metal layer M1, a first insulating layer IL1, a second metal layer M2, a second insulating layer IL2, and pixels Electrode PE and reflective electrode RE. The substrate SB is, for example, a flexible substrate, which can be a polymer substrate or a plastic substrate, but the invention is not limited to this. In other embodiments, the substrate SB may also be, for example, a rigid substrate, which may be a glass substrate, a quartz substrate, or a silicon substrate.

The first metal layer M1 is provided on the substrate SB, for example. The first metal layer M1 is formed by, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a photolithographic etching process. For example, a first metal material layer (not shown) can be formed on the substrate SB by using a physical vapor deposition method or a metal chemical vapor deposition method. Then, a patterned photoresist layer (not shown) is formed on the first metal material layer. Afterwards, using the patterned photoresist layer as a mask, an etching process is performed on the first metal material layer to form the first metal layer M1.

The first metal layer M1 may, for example, include a gate electrode G, a scan line SL, a common electrode line CVL, and a first storage electrode SE1. The scan line SL and the common electrode line CVL extend in the first direction e1, for example. The gate G, for example, is electrically connected to the corresponding scan line SL to receive the corresponding gate signal. The first storage electrode SE1 can, for example, form a storage capacitor Cst1 with the second metal layer M2 described later and the first insulating layer IL1 between the two. The common electrode line CVL can be used to supply a common voltage, for example. The storage capacitor Cst1 may be electrically connected to the common electrode line CVL, and receive the common voltage supplied through the common electrode line CVL.

In this embodiment, the first metal layer M1 undergoes a lithographic etching process during the formation process, so the formed first metal layer M1 will include a plurality of first patterned portions P1. The plurality of first patterned portions P1 here means the portion where the first metal material layer is etched away, that is, no one of the gate G, the scan line SL, the common electrode line CVL, and the first storage electrode SE1 is provided Area. It is worth mentioning that when a plurality of first patterned portions P1 are defined, no other regions of the first metal layer M1 used as the first storage electrode SE1 are removed. This is because the subsequent reflective electrode RE has The patterned portion will partially correspond to the plurality of first patterned portions P1 of the first metal layer M1, so that this embodiment does not need to deliberately remove other regions of the first metal layer M1 used as the first storage electrode SE1 .

The first insulating layer IL1 is, for example, disposed on the substrate SB and covers the first metal layer M1. That is, the first insulating layer IL1 may cover the gate electrode G, the scan line SL, the common electrode line CVL, and the first storage electrode SE1. The method of forming the first insulating layer IL1 is, for example, by using a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the first insulating layer IL1 can be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (for example: polyimide) Resin, epoxy resin or acrylic resin) or a combination of the above, but the invention is not limited to this. The first insulating layer IL1 may have a single-layer structure, but the invention is not limited to this. In other embodiments, the first insulating layer IL1 may also have a multilayer structure.

The second metal layer M2 is, for example, disposed on the first insulating layer IL1. The method for forming the second metal layer M2 is, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a second metal material layer (not shown) on the first insulating layer IL1. Then, a patterned photoresist layer (not shown) is formed on the second metal material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the second metal material layer to form the second metal layer M2.

The second metal layer M2 may, for example, include a data line DL, a source electrode S, a drain electrode D, and a second storage electrode SE2. The data line DL extends, for example, in a second direction e2 orthogonal to the first direction e1. The source S is, for example, electrically connected to the corresponding data line DL to receive the corresponding data signal. The second storage electrode SE2, for example, the first storage electrode SE1 and the first insulating layer IL1 located between the first storage electrode SE1 and the second storage electrode SE2 form a storage capacitor Cst1. The storage capacitor Cst1 can be used to store voltage, and the magnitude of the stored voltage can affect the deflection state of the liquid crystal molecules (not shown).

In this embodiment, the second metal layer M2 undergoes a lithographic etching process during the formation process, so the formed second metal layer M2 will include a plurality of second patterned portions P2. The plurality of second patterned portions P2 here means the portion where the second metal material layer is etched away, that is, the portion that is not provided with any one of the data line DL, the source electrode S, the drain electrode D, and the second storage electrode SE2 area. It is worth mentioning that when a plurality of second patterned portions P2 are defined, no other regions of the second metal layer M2 used as the second storage electrode SE2 are removed. This is because the subsequent reflective electrode RE has The patterned portion will partially correspond to the plurality of second patterned portions P2 of the second metal layer M2, so that this embodiment does not need to deliberately remove other regions of the second metal layer M2 used as the second storage electrode SE2 .

In an embodiment, the pixel structure 10 may further include a semiconductor layer CH. The semiconductor layer CH may be formed, for example, after forming the first insulating layer IL1. That is, the semiconductor layer CH is disposed on the first insulating layer IL1, for example.

The method for forming the semiconductor layer CH is, for example, using a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a semiconductor material layer (not shown) on the first insulating layer IL1. Next, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the semiconductor material layer to form the semiconductor layer CH. The material of the semiconductor layer CH can be, for example, amorphous silicon, but the invention is not limited to this. The material of the semiconductor layer CH can also be, for example, polycrystalline silicon, microcrystalline silicon, single crystal silicon, nanocrystalline silicon, or other semiconductor materials or metal oxide semiconductor materials with different lattice arrangements.

In this embodiment, the gate electrode G, the source electrode S, the drain electrode D, and the semiconductor layer CH can constitute the active device T. The semiconductor layer CH may be provided corresponding to the gate electrode G, and partially covered by the source electrode S and the drain electrode D, for example. The semiconductor layer CH that is not covered by the source electrode S and the drain electrode D can be used as the channel layer of the active device T. The active device T is, for example, any bottom gate type thin film transistor well known to those skilled in the art. However, although this embodiment takes the bottom gate type thin film transistor as an example, the invention of the present invention is not limited to this. In other embodiments, the active device T is, for example, a top gate type thin film transistor or other suitable types of thin film transistors.

The second insulating layer IL2 is, for example, disposed on the first insulating layer IL1 and covers the second metal layer M2. That is, the second insulating layer IL2 can cover the data line DL, the source S, the drain D, and the second storage electrode SE2. The method for forming the second insulating layer IL2 is, for example, by using a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the second insulating layer IL2 can be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials), an organic material (for example: polyimide) Resin, epoxy resin or acrylic resin) or a combination of the above, but the invention is not limited to this. The second insulating layer IL2 may have a single-layer structure, but the invention is not limited to this. In other embodiments, the second insulating layer IL2 may also have a multilayer structure.

The flat layer PL is provided on the second insulating layer IL2, for example. The method of forming the flat layer PL is, for example, by using a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the flat layer PL can be inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials), organic materials (for example: polyimide resin , Epoxy resin or acrylic resin) or a combination of the above, but the invention is not limited to this. The flat layer PL may have a single-layer structure, but the invention is not limited to this. In other embodiments, the flat layer PL may also have a multilayer structure. The flat layer PL can make the film layer subsequently formed thereon have good stability.

The pixel electrode PE is provided on the flat layer PL, for example. The pixel electrode PE is formed by, for example, using a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a pixel electrode material layer (not shown) on the flat layer PL. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the pixel electrode material layer to form the pixel electrode PE. The material of the pixel electrode PE may be, for example, a metal oxide conductive material (for example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In one embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through the contact window H penetrating the second insulating layer IL2 and the flat layer PL. In detail, the pixel electrode PE is electrically connected to the drain D of the active device T, for example.

The reflective electrode RE is provided on the pixel electrode PE, for example. The method for forming the reflective electrode RE is, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a reflective electrode material layer (not shown) on the pixel electrode PE. Then, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the reflective electrode material layer to form the reflective electrode RE.

The reflective electrode RE can be formed of, for example, a metal material with a reflectivity of ≥90%. In this embodiment, the material of the reflective electrode RE is aluminum, silver or an alloy thereof, but the invention is not limited to this. The reflective electrode RE is used, for example, to reflect external ambient light or light emitted by a backlight.

In this embodiment, the reflective electrode RE includes a plurality of third patterned portions P3, wherein the plurality of third patterned portions P3 are not provided with any metal layer (including at least the first metal layer M1 and the second metal layer). The area of M2) is defined, that is, it is defined by the area P12 where the plurality of first patterned areas P1 and the plurality of second patterned areas P2 overlap. In other words, the area P12 where the plurality of third patterned portions P3 of the reflective electrode RE overlaps the plurality of first patterned areas P1 and the plurality of second patterned areas P2 in the normal direction n of the substrate SB is substantially Correspondingly, to define the penetration area TR. For example, the plurality of third patterned portions P3 of the reflective electrode RE only correspond to the first insulating layer IL1, the second insulating layer IL2, and the flat layer PL in the normal direction n of the substrate SB. Therefore, the plurality of third patterned portions P3 of the reflective electrode RE can be used as the penetration area TR, and the reflective electrode RE itself can be used as the reflective area RR. From another perspective, for example, only an insulating layer (including at least the first insulating layer IL1, the second insulating layer IL2, and the flat layer PL) or a transparent electrode (including at least the pixel electrode PE) is provided in the penetration region TR. Allows ambient light or backlight from outside to pass through. In general, the placement position of the reflective electrode RE can define the reflective area RR and the penetrating area TR.

Based on this, the pixel structure 10 of this embodiment substantially corresponds to the area where no metal layer is provided in the normal direction n of the substrate SB by arranging a plurality of patterned portions P of the reflective electrode RE in the pixel structure 10 of the present embodiment. The areas of the first metal layer M1 for forming the first storage electrode SE1 and the second metal layer M2 for forming the second storage electrode SE2 may not be reduced as the penetration region TR. In this case, the storage capacitor in one pixel structure of the display panel created by the present invention can be increased to store a larger voltage, thereby having good electrical properties.

2A is a schematic top view of the pixel structure of the second embodiment of the new creation. 2B is a schematic diagram of the penetration area and the reflection area of the pixel structure of the second embodiment of the new creation. It must be noted here that the embodiments shown in FIGS. 2A and 2B respectively use the element numbers and part of the content of the embodiments in FIGS. 1A and 1C, wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the descriptions and effects of the foregoing embodiments. The following embodiments will not be repeated, and at least part of the descriptions not omitted in the embodiments shown in FIG. 2A and FIG. 2B can be referred to the subsequent content.

Please refer to FIGS. 2A and 2B at the same time. In the embodiment shown in FIGS. 2A and 2B, the pixel structure 20 has a first gray-scale display area GS1 and a second gray-scale display area GS2. Applying a voltage to the first grayscale display area GS1 or the second grayscale display area GS2 can drive the liquid crystal molecules (not shown) located on the first grayscale display area GS1 or the second grayscale display area GS2 to rotate. In detail, for example, whether a voltage is applied to the first gray-scale display area GS1 or the second gray-scale display area GS2 can be used to determine the liquid crystals corresponding to the first gray-scale display area GS1 and the second gray-scale display area GS2. The molecule assumes a bright state (ie, allows light to pass through) or assumes a dark state (ie, blocks light from passing through). Since the pixel structure 20 of this embodiment has a first gray-scale display area GS1 and a second gray-scale display area GS2, the pixel structure 20 includes a first active device T1 and a second active device T2. In some embodiments, the first active device T1 is located on the substrate SB and includes a first gate G1, a first source S1, a first drain D1, and a first semiconductor layer SE1, and the second active device T2 is also located on the substrate SB There is a second gate electrode G2, a second source electrode S2, a second drain electrode D2, and a second semiconductor layer SE2. In some embodiments, the size of the first active element T1 may be larger than the size of the second active element T2, but the invention is not limited to this.

3A is a schematic top view of the pixel structure of the third embodiment of the new creation. FIG. 3B is a schematic diagram of the penetration area and the reflection area of the pixel structure of the third embodiment of the new creation. It must be noted here that the embodiments shown in FIGS. 3A and 3B respectively use the element numbers and part of the content of the embodiments in FIGS. 2A and 2B, wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the descriptions and effects of the foregoing embodiments. The following embodiments will not be repeated. For at least part of the descriptions not omitted in the embodiments shown in FIG. 3A and FIG. 3B, please refer to the subsequent content.

Referring to FIGS. 3A and 3B at the same time, the pixel structure 30 of the present invention has a first gray-scale display area GS1 that includes a first display area GS11, and a second gray-scale display area GS2 includes two second display areas. GS21 and GS22 make the pixel structure 30 have three display areas. The operation method of the pixel structure 30 of this embodiment is as follows. When the first active element T1 and the second active element T2 are turned on at the same time, three display areas (one first display area GS11 and two second display areas) can be enabled. Blocks GS21, GS22) are in the bright state. When the first active device T1 is turned off and the second active device T2 is turned on, the two display blocks (two second display blocks GS21, GS22) can be in the bright state. When the first active device T1 is turned on and the second active device T2 is turned off, one display area (a first display area GS11) can be made bright, and when the first active device T1 and the second active device T2 are turned off, The above three display blocks can be darkened.

Fig. 4A is a schematic cross-sectional view of the first embodiment taken along the line B-B' in Fig. 3B. Fig. 4B is a schematic cross-sectional view of the second embodiment taken along the line B-B' in Fig. 3B. Fig. 4C is a schematic cross-sectional view of the third embodiment taken along the line B-B' in Fig. 3B. Fig. 4D is a schematic cross-sectional view of the fourth embodiment taken along the line B-B' in Fig. 3B.

In the embodiment of the present invention, the pixel structures 10, 20, and 30 have multiple patterned portions P3 of the reflective electrode RE in the normal direction n of the substrate SB and the area not provided with any metal layer. It is substantially correspondingly arranged to define the penetration area TR without reducing the area of the first storage electrode SE1 and the second storage electrode SE2. However, the fact that the multiple patterned parts P of the reflective electrode RE are arranged substantially corresponding to the area where no metal layer is provided does not exactly mean that the multiple patterned parts P3 of the reflective electrode RE are not provided with any metal layer. The area corresponds completely. That is, in some embodiments, the penetration area TR may be defined by a specific metal layer due to the design of the pixel structures 10, 20, and 30, wherein FIGS. 4A to 4D illustrate the penetration area TR in more detail. Which metal layer is defined. In FIG. 4A, the penetration area TR is defined by the reflective electrode RE. In FIG. 4B, the penetration area TR is defined by the first metal layer M1. In FIG. 4C, the penetration area TR is defined by the second metal layer M2. In FIG. 4D, the penetration area TR is defined by the third metal layer M3.

FIG. 5A is an enlarged schematic diagram of the first embodiment of the area X in FIG. 3B. FIG. 5B is an enlarged schematic diagram of the second embodiment of the area X in FIG. 3B. FIG. 5C is an enlarged schematic diagram of the third embodiment of the area X in FIG. 3B. FIG. 5D is an enlarged schematic diagram of the fourth embodiment of the area X in FIG. 3B.

Please refer to the foregoing embodiment, the penetration area TR can be defined by a specific metal layer due to the design of the pixel structures 10, 20, 30, and FIGS. 5A to 5D show in more detail where the penetration area TR is located. One or which metal layers are defined. In FIG. 5A, the penetration area TR is defined by the reflective electrode RE. In FIG. 5B, the penetration area TR is defined by the reflective electrode RE and the first metal layer M1. In FIG. 5C, the penetration area TR is defined by the reflective electrode RE and the second metal layer M2. In FIG. 5D, the penetration area TR is defined by the reflective electrode RE, the first metal layer M1, the second metal layer M2, and the third metal layer M3.

To sum up, the pixel structure created by the present invention defines the third patterned portion of the reflective electrode by the area that is not provided with any metal layer (including at least the first metal layer and the second metal layer). That is, it is defined by the overlapping area of the plurality of first patterned areas and the plurality of second patterned areas. In other words, the multiple third patterned portions of the reflective electrode substantially correspond to the overlapping areas of the multiple first patterned areas and the multiple second patterned areas in the normal direction of the substrate, so as to define the penetration Area. Based on this, the pixel structure of the present invention does not reduce the area of the first metal layer for forming the first storage electrode and the area of the second metal layer for forming the second storage electrode as the penetration area. In this case, the storage capacitor in one pixel structure of the display panel created by the present invention can be increased to store a larger voltage, thereby having good electrical properties.

10, 20, 30: pixel structure A-A’, B-B’: Sectional line CH: semiconductor layer Cst1: storage capacitor CVL: Common electrode line D: Dip pole e1: first direction e2: second direction DL: Data line G: Gate GS1: The first grayscale display area GS11: The first display block GS2: The second grayscale display area GS21, GS22: the second display block H: Contact window IL1: first insulating layer IL2: second insulating layer M1: The first metal layer M2: second metal layer M3: third metal layer n: normal direction P1: The first patterning part P12: overlapping area P2: The second patterning part P3: The third patterning part PE: pixel electrode PL: Flat layer RE: reflective electrode RR: reflection zone S: source SB: Substrate SE1: first storage electrode SE2: second storage electrode SL: scan line T: Active component T1: The first active component T2: second active component TR: penetration zone X: area

FIG. 1A is a schematic top view of the pixel structure of the first embodiment of the new creation. Fig. 1B is a schematic cross-sectional view of the section line A-A' in Fig. 1A. FIG. 1C is a schematic diagram of the penetration area and the reflection area of the pixel structure of the first embodiment of the new creation. 2A is a schematic top view of the pixel structure of the second embodiment of the new creation. 2B is a schematic diagram of the penetration area and the reflection area of the pixel structure of the second embodiment of the new creation. 3A is a schematic top view of the pixel structure of the third embodiment of the new creation. FIG. 3B is a schematic diagram of the penetration area and the reflection area of the pixel structure of the third embodiment of the new creation. Fig. 4A is a schematic cross-sectional view of the first embodiment taken along the line B-B' in Fig. 3B. Fig. 4B is a schematic cross-sectional view of the second embodiment taken along the line B-B' in Fig. 3B. Fig. 4C is a schematic cross-sectional view of the third embodiment taken along the line B-B' in Fig. 3B. Fig. 4D is a schematic cross-sectional view of the fourth embodiment taken along the line B-B' in Fig. 3B. FIG. 5A is an enlarged schematic diagram of the first embodiment of the area X in FIG. 3B. FIG. 5B is an enlarged schematic diagram of the second embodiment of the area X in FIG. 3B. FIG. 5C is an enlarged schematic diagram of the third embodiment of the area X in FIG. 3B. FIG. 5D is an enlarged schematic diagram of the fourth embodiment of the area X in FIG. 3B.

A-A’: Sectional line

CH: semiconductor layer

CVL: Common electrode line

D: Dip pole

e1: first direction

e2: second direction

DL: Data line

G: Gate

H: Contact window

M1: The first metal layer

M2: second metal layer

n: normal direction

P1: The first patterning part

P12: overlapping area

P2: The second patterning part

P3: The third patterning part

PE: pixel electrode

RE: reflective electrode

S: source

SE1: first storage electrode

SE2: second storage electrode

SL: scan line

T: Active component

Claims (10)

A pixel structure with a penetration area and a reflection area, including: Substrate The first metal layer is disposed on the substrate and includes a plurality of first patterned regions and first storage electrodes; A first insulating layer disposed on the substrate and covering the first metal layer; A second metal layer disposed on the first insulating layer and including a plurality of second patterned regions and second storage electrodes; A second insulating layer disposed on the first insulating layer and covering the second metal layer; A flat layer disposed on the second insulating layer; The pixel electrode is electrically connected to the second metal layer through a contact window penetrating the second insulating layer and the flat layer; and The reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned regions, Wherein the plurality of third patterned portions substantially correspond to the overlapping area of the plurality of first patterned regions and the plurality of second patterned regions in the normal direction of the substrate, so as to define the述puncture area. The pixel structure according to claim 1, wherein the penetration area is defined by the reflective electrode. The pixel structure according to claim 1, wherein the penetration area is defined by the first metal layer. The pixel structure according to claim 1, wherein the penetration area is defined by the second metal layer. The pixel structure according to claim 1, further comprising a third metal layer disposed between the second insulating layer and the flat layer, wherein the penetrating area is defined by the third metal layer Out. The pixel structure according to claim 1, wherein the penetration area is defined by the reflective electrode and the first metal layer. The pixel structure according to claim 1, wherein the penetration area is defined by the reflective electrode and the second metal layer. The pixel structure according to claim 5, wherein the penetration area is defined by the reflective electrode, the first metal layer, the second metal layer, and the third metal layer. The pixel structure according to claim 1, which has a first gray-scale display area and a second gray-scale display area, wherein the first gray-scale display area includes a first display area, and the second gray-scale display area The second display area includes two second display areas. The pixel structure according to claim 1, wherein no other areas of the first metal layer used as the first storage electrode are removed when the plurality of first patterned areas are defined, and When the plurality of second patterned regions are defined, no other regions of the second metal layer used as the second storage electrode are removed.

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