TWI755254B - Pixel structure - Google Patents

Abstract

A pixel structure having a transmitting region and a reflecting region and including a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a planarization layer, a pixel electrode and a fourth metal layer is provided. The first metal layer is disposed on the substrate and includes a plurality of first patterned areas and a first storage electrode. The first insulating layer is disposed on the substrate and covers the first metal layer. The second metal layer is disposed on the first insulating layer and includes a plurality of second patterned areas and a second storage electrode. The second insulating layer is disposed on the first insulating layer and covers the second metal layer. The planarization layer is disposed on the second insulating layer. The pixel electrode is electrically connected to the second metal layer by a contact window penetrating the second insulating layer and the planarization layer. The reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned areas. The third patterned areas substantially correspond an area which is an overlapped area of the first patterned areas and the second patterned areas in a normal direction of the substrate, so that the transmitting region is defined.

Description

pixel structure

The present invention relates to a pixel structure, and more particularly, to a pixel structure for a transflective display panel.

In the conventional transflective display panel, the way to define the penetration area is to select a specific area so that the reflective electrode, the first metal layer and the second metal layer are removed in the specific area; however, , the first metal layer used to form the first storage electrode and the second metal layer used to form the second storage electrode will be removed in such a way of defining the penetration region, resulting in a reduction in area. Therefore, the way of defining the penetration area will reduce the storage capacitance in a pixel structure of the display panel, thereby reducing the voltage stability of the display panel.

The present invention provides a pixel structure, the storage capacitance of which can be increased to store a larger voltage, thereby having good electrical properties.

The pixel structure of an embodiment of the present invention has a penetrating region and a reflective region, and includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a flat layer, a pixel electrode, and reflective electrode. The first metal layer is disposed on the substrate and includes a plurality of first patterned regions and a first storage electrode. The first insulating layer is disposed on the substrate and covers the first metal layer. The second metal layer is disposed on the first insulating layer and includes a plurality of second patterned regions and a second storage electrode. The second insulating layer is disposed on the first insulating layer and covers the second metal layer. The flat layer is disposed on the second insulating layer. The pixel electrode is disposed on the flat layer and is electrically connected to the second metal layer through a contact window penetrating the second insulating layer and the flat layer. The reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned regions. The plurality of third patterned portions substantially correspond to the overlapping regions of the plurality of first patterned regions and the plurality of second patterned regions in the normal direction of the substrate to define penetration regions.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the reflective electrode.

In an embodiment of the present invention, the above-mentioned penetration region is defined by the first metal layer.

In an embodiment of the present invention, the above-mentioned penetration region is defined by the second metal layer.

In an embodiment of the present invention, the above-mentioned pixel structure further includes a third metal layer disposed between the second insulating layer and the flat layer, wherein the penetration region is defined by the third metal layer.

In an embodiment of the present invention, the above-mentioned penetration region is defined by the reflective electrode and the first metal layer.

In an embodiment of the present invention, the above-mentioned penetration area is defined by the reflective electrode and the second metal layer.

In an embodiment of the present invention, the above-mentioned penetration region is defined by the reflective electrode, the first metal layer, the second metal layer and the third metal layer.

In an embodiment of the present invention, the above-mentioned pixel structure has a first grayscale display area and a second grayscale display area, the first grayscale display area includes a first display area, and the second grayscale display area Two second display blocks are included.

In an embodiment of the present invention, no other regions of the first metal layer used as the first storage electrode are removed when the plurality of first patterned regions are defined, and when the plurality of second patterns are defined No other area of the second metal layer used as the second storage electrode is removed when the area is being decomposed.

Based on the above, in the pixel structure of the present invention, no other regions of the first metal layer used as the first storage electrode are removed when a plurality of first patterned regions are defined, and when a plurality of second patterned regions are defined, no other regions are removed. No other regions of the second metal layer used as the second storage electrode are removed when the region is patterned, and the pixel structure of the present invention can not reduce the size of the first metal layer used to form the first storage electrode and the second storage electrode. The area of the second metal layer of the electrode is used as the penetration area. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased to store a larger voltage, thereby having good electrical properties.

The present invention will be more fully described below with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions will not be repeated in the following paragraphs. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front or rear, etc., only refer to the directions of the attached drawings. Accordingly, the directional terms used are illustrative and not limiting of the present invention.

FIG. 1A is a schematic top view of a pixel structure according to a first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along the line A-A' in Fig. 1A . 1C is a schematic diagram of a transmission area and a reflection area of the pixel structure according to the first embodiment of the present invention.

1A , 1B and 1C at the same time, the pixel structure 10 of this embodiment includes a substrate SB, a first metal layer M1 , a first insulating layer IL1 , a second metal layer M2 , a second insulating layer IL2 , and a pixel Electrode PE and reflective electrode RE. The substrate SB is, for example, a flexible substrate, which can be a polymer substrate or a plastic substrate, but the present invention is not limited thereto. In other embodiments, the substrate SB can also be, for example, a rigid substrate, which can be a glass substrate, a quartz substrate or a silicon substrate.

The first metal layer M1 is disposed on the substrate SB, for example. The first metal layer M1 is formed by, for example, using physical vapor deposition or metal chemical vapor deposition and then performing a lithography etching process. For example, a first metal material layer (not shown) may be formed on the substrate SB by a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the first metal material layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the first metal material layer to form a first metal layer M1.

The first metal layer M1 may include, for example, a gate electrode G, a scan line SL, a common electrode line CVL, and a first storage electrode SE1. The scan line SL and the common electrode line CVL extend, for example, in the first direction e1. For example, the gate electrode G is electrically connected to the corresponding scan line SL to receive the corresponding gate electrode signal. The first storage electrode SE1 may, for example, form a storage capacitor Cst1 with the second metal layer M2 to be described later and the first insulating layer IL1 interposed therebetween. The common electrode line CVL may be used, for example, to supply a common voltage. The storage capacitor Cst1 can be electrically connected to the common electrode line CVL to receive a common voltage supplied through the common electrode line CVL.

In this embodiment, the first metal layer M1 will undergo a lithography etching process during the formation process, so the formed first metal layer M1 will include a plurality of first patterned portions P1. The plurality of first patterned portions P1 here means portions where the first metal material layer is etched away, that is, no one of the gate electrode G, the scan line SL, the common electrode line CVL and the first storage electrode SE1 is provided Area. It is worth mentioning that when a plurality of first patterned portions P1 are defined, no other regions of the first metal layer M1 used as the first storage electrode SE1 are removed. This is because the subsequent reflective electrodes RE have The patterned portion will partially correspond to the plurality of first patterned portions P1 of the first metal layer M1, so that this embodiment does not need to intentionally remove other regions of the first metal layer M1 used as the first storage electrode SE1 .

The first insulating layer IL1 is, for example, disposed on the substrate SB and covers the first metal layer M1. That is, the first insulating layer IL1 may cover the gate electrode G, the scan line SL, the common electrode line CVL and the first storage electrode SE1. The formation method of the first insulating layer IL1 is formed by, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the first insulating layer IL1 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), an organic material (eg, polyimide) resin, epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited thereto. The first insulating layer IL1 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the first insulating layer IL1 can also be a multi-layer structure.

For example, the second metal layer M2 is disposed on the first insulating layer IL1. The formation method of the second metal layer M2 is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a second metal material layer (not shown) can be formed on the first insulating layer IL1 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the second metal material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the second metal material layer to form a second metal layer M2.

The second metal layer M2 may include, for example, a data line DL, a source electrode S, a drain electrode D, and a second storage electrode SE2. The data line DL extends, for example, in the second direction e2 orthogonal to the first direction e1. For example, the source electrode S is electrically connected to the corresponding data line DL to receive the corresponding data signal. For example, the second storage electrode SE2 forms a storage capacitor Cst1 with the first storage electrode SE1 and the first insulating layer IL1 between the first storage electrode SE1 and the second storage electrode SE2. The storage capacitor Cst1 can be used to store voltage, and the magnitude of the stored voltage can affect the deflection state of the liquid crystal molecules (not shown).

In this embodiment, the second metal layer M2 will undergo a lithography etching process during the formation process, so the formed second metal layer M2 will include a plurality of second patterned portions P2. The plurality of second patterned portions P2 here means the portions where the second metal material layer is etched away, that is, the portions not provided with any one of the data line DL, the source electrode S, the drain electrode D and the second storage electrode SE2 area. It is worth mentioning that when a plurality of second patterned portions P2 are defined, no other regions of the second metal layer M2 used as the second storage electrode SE2 are removed. This is because the subsequent reflective electrodes RE have The patterned portion will partially correspond to the plurality of second patterned portions P2 of the second metal layer M2, so that this embodiment does not need to intentionally remove other regions of the second metal layer M2 used as the second storage electrode SE2 .

In one embodiment, the pixel structure 10 may further include a semiconductor layer CH. The semiconductor layer CH may be formed, for example, after the first insulating layer IL1 is formed. That is, the semiconductor layer CH is provided on, for example, the first insulating layer IL1.

The formation method of the semiconductor layer CH is formed by, for example, a lithography etching process. For example, a semiconductor material layer (not shown) can be formed on the first insulating layer IL1 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the semiconductor material layer to form the semiconductor layer CH. The material of the semiconductor layer CH can be, for example, amorphous silicon, but the present invention is not limited thereto. The material of the semiconductor layer CH can also be, for example, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, nanocrystalline silicon, or other semiconductor materials or metal oxide semiconductor materials with different lattice arrangements.

In this embodiment, the gate electrode G, the source electrode S, the drain electrode D and the semiconductor layer CH can constitute the active element T. The semiconductor layer CH may be provided corresponding to the gate electrode G, for example, and is partially covered by the source electrode S and the drain electrode D. As shown in FIG. The semiconductor layer CH not covered by the source electrode S and the drain electrode D can be used as a channel layer of the active element T. The active element T is, for example, any bottom gate type thin film transistor known to those skilled in the art. However, although this embodiment takes the bottom gate type thin film transistor as an example, the present invention is not limited thereto. In other embodiments, the active element T is also, for example, a top gate type thin film transistor or other suitable types of thin film transistors.

For example, the second insulating layer IL2 is disposed on the first insulating layer IL1 and covers the second metal layer M2. That is, the second insulating layer IL2 may cover the data line DL, the source electrode S, the drain electrode D and the second storage electrode SE2. The formation method of the second insulating layer IL2 is formed by, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the second insulating layer IL2 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), an organic material (eg, polyimide) resin, epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited thereto. The second insulating layer IL2 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the second insulating layer IL2 can also be a multi-layer structure.

The flat layer PL is provided, for example, on the second insulating layer IL2. The formation method of the flat layer PL is formed by, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the flat layer PL can be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), an organic material (eg, a polyimide resin) , epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited thereto. The flat layer PL may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the planarization layer PL may also be a multi-layer structure. The flat layer PL can make the film layer formed thereon have good stability.

The pixel electrode PE is provided on, for example, the flat layer PL. The formation method of the pixel electrode PE is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a pixel electrode material layer (not shown) can be formed on the flat layer PL by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the pixel electrode material layer to form the pixel electrode PE. The material of the pixel electrode PE can be, for example, a metal oxide conductive material (eg, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In one embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through the contact window H penetrating the second insulating layer IL2 and the flat layer PL. Specifically, the pixel electrode PE is electrically connected to the drain electrode D of the active element T, for example.

The reflective electrode RE is provided on, for example, the pixel electrode PE. The forming method of the reflective electrode RE is, for example, using physical vapor deposition method or metal chemical vapor deposition method and then performing a lithography etching process. For example, a reflective electrode material layer (not shown) can be formed on the pixel electrode PE by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. Then, using the patterned photoresist layer as a mask, the reflective electrode material layer is etched to form the reflective electrode RE.

The reflective electrode RE can be formed, for example, by selecting a metal material with a reflectivity of ≥90%. In this embodiment, the material of the reflective electrode RE is aluminum, silver or an alloy thereof, but the present invention is not limited thereto. For example, the reflective electrode RE is used to reflect external ambient light or light emitted by a backlight source.

In this embodiment, the reflective electrode RE includes a plurality of third patterned portions P3, wherein the plurality of third patterned portions P3 are not provided with any metal layer (at least including the first metal layer M1 and the second metal layer M2) is defined, that is, it is defined by a region P12 in which a plurality of first patterned regions P1 and a plurality of second patterned regions P2 overlap. In other words, the plurality of third patterned portions P3 of the reflective electrode RE are substantially overlapped with the plurality of first patterned regions P1 and the plurality of second patterned regions P2 in the normal direction n of the substrate SB in the region P12 Correspondingly, to define the penetration region TR. For example, the plurality of third patterned portions P3 of the reflective electrode RE only correspond to the first insulating layer IL1 , the second insulating layer IL2 and the flat layer PL in the normal direction n of the substrate SB. Therefore, the plurality of third patterned portions P3 of the reflective electrode RE can serve as the penetration region TR, and the reflective electrode RE itself serves as the reflective region RR. From another point of view, for example, only insulating layers (including at least the first insulating layer IL1 , the second insulating layer IL2 and the flat layer PL) or transparent electrodes (including at least the pixel electrodes PE) are disposed in the penetration region TR. Therefore, Allows ambient light or backlight from the outside to pass through. In general, the arrangement position of the reflective electrode RE can define the reflective region RR and the penetrating region TR.

Based on this, in the pixel structure 10 of the present embodiment, a plurality of patterned portions P of the reflective electrode RE are arranged in the normal direction n of the substrate SB to substantially correspond to the region without any metal layer, so The areas of the first metal layer M1 for forming the first storage electrode SE1 and the second metal layer M2 for forming the second storage electrode SE2 may not be reduced as the penetration region TR. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased to store a larger voltage, thereby having good electrical properties.

2A is a schematic top view of a pixel structure according to a second embodiment of the present invention. FIG. 2B is a schematic diagram of the transmission area and the reflection area of the pixel structure according to the second embodiment of the present invention. It must be noted here that the embodiments shown in FIG. 2A and FIG. 2B respectively use the element numbers and part of the content of the embodiment in FIG. 1A and FIG. 1C , wherein the same or similar reference numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the descriptions and effects of the foregoing embodiments, and the following embodiments will not be repeated.

Please refer to FIG. 2A and FIG. 2B at the same time. In the embodiment shown in FIG. 2A and FIG. 2B , the pixel structure 20 has a first gray-scale display area GS1 and a second gray-scale display area GS2 . Applying a voltage to the first gray-scale display area GS1 or the second gray-scale display area GS2 can drive the liquid crystal molecules (not shown) on the first gray-scale display area GS1 or the second gray-scale display area GS2 to rotate. Specifically, the liquid crystals corresponding to the first gray-scale display area GS1 and the second gray-scale display area GS2 can be determined by, for example, whether or not a voltage is applied to the first gray-scale display area GS1 or the second gray-scale display area GS2 Molecules exhibit either a bright state (ie, allowing light to pass) or a dark state (ie, blocking light from passing). Since the pixel structure 20 of this embodiment has the first grayscale display area GS1 and the second grayscale display area GS2 , the pixel structure 20 includes the first active element T1 and the second active element T2 . In some embodiments, the first active element T1 is located on the substrate SB and includes a first gate G1, a first source S1, a first drain D1 and a first semiconductor layer SE1, and the second active element T2 is also located on the substrate SB and includes a second gate electrode G2, a second source electrode S2, a second drain electrode D2 and a second semiconductor layer SE2. In some embodiments, the size of the first active element T1 may be larger than that of the second active element T2, but the invention is not limited thereto.

3A is a schematic top view of a pixel structure according to a third embodiment of the present invention. 3B is a schematic diagram of a transmission area and a reflection area of the pixel structure according to the third embodiment of the present invention. It must be noted here that the embodiments shown in FIG. 3A and FIG. 3B respectively use the element numbers and part of the contents of the embodiment in FIG. 2A and FIG. 2B , wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted part, reference may be made to the descriptions and effects of the foregoing embodiments, and the following embodiments will not be repeated.

3A and 3B at the same time, the pixel structure 30 of the present invention has a first gray-scale display area GS1 including a first display area GS11 and a second gray-scale display area GS2 includes two second display areas GS21 , GS22, so that the pixel structure 30 has three display blocks. The operation of the pixel structure 30 in this embodiment is as follows. When the first active element T1 and the second active element T2 are turned on at the same time, three display blocks (one first display block GS11 and two second display blocks) can be enabled. The blocks GS21, GS22) are in a bright state. When the first active element T1 is turned off and the second active element T2 is turned on, the two display blocks (the two second display blocks GS21 and GS22) can be in a bright state. When the first active element T1 is turned on and the second active element T2 is turned off, one display block (a first display block GS11 ) can be in a bright state, and when the first active element T1 and the second active element T2 are turned off, The above-mentioned three display blocks can be in a dark state.

Fig. 4A is a schematic cross-sectional view of the first embodiment along the line B-B' in Fig. 3B . FIG. 4B is a schematic cross-sectional view of the second embodiment along the line B-B' in FIG. 3B . Fig. 4C is a schematic cross-sectional view of the third embodiment along the line B-B' in Fig. 3B . FIG. 4D is a schematic cross-sectional view of the fourth embodiment along the line B-B' in FIG. 3B .

In the embodiment of the present invention, the pixel structures 10 , 20 , and 30 are substantially formed by patterning the plurality of patterned portions P3 of the reflective electrode RE in the normal direction n of the substrate SB and the region without any metal layer. Correspondingly, the penetration region TR is defined without reducing the area of the first storage electrode SE1 and the second storage electrode SE2. However, the fact that the plurality of patterned portions P of the reflective electrode RE substantially correspond to the regions not provided with any metal layer does not exactly mean that the plurality of patterned portions P3 of the reflective electrode RE is not provided with any metal layer. area corresponds completely. That is, in some embodiments, the penetration region TR may be defined by a specific metal layer due to the design of the pixel structures 10 , 20 , 30 , wherein FIGS. 4A to 4D illustrate the penetration region TR in more detail by Which metal layer defines. In FIG. 4A, the penetration region TR is defined by the reflective electrode RE. In FIG. 4B, the penetration region TR is defined by the first metal layer M1. In FIG. 4C, the penetration region TR is defined by the second metal layer M2. In FIG. 4D, the penetration region TR is defined by the third metal layer M3.

FIG. 5A is an enlarged schematic view of the first embodiment of the region X in FIG. 3B . FIG. 5B is an enlarged schematic view of the second embodiment of the region X in FIG. 3B . FIG. 5C is an enlarged schematic view of the third embodiment of the region X in FIG. 3B . FIG. 5D is an enlarged schematic view of the fourth embodiment of the region X in FIG. 3B .

Please refer to the aforementioned embodiments, the penetration region TR may be defined by a specific metal layer according to the design of the pixel structures 10 , 20 , 30 , wherein FIG. 5A to FIG. 5D illustrate in more detail where the penetration region TR is One or which metal layers are defined. In FIG. 5A, the penetration region TR is defined by the reflective electrode RE. In FIG. 5B, the penetration region TR is defined by the reflective electrode RE and the first metal layer M1. In FIG. 5C, the penetration region TR is defined by the reflective electrode RE and the second metal layer M2. In FIG. 5D, the penetration region TR is defined by the reflective electrode RE, the first metal layer M1, the second metal layer M2 and the third metal layer M3.

To sum up, the pixel structure of the present invention is defined by defining a plurality of third patterned portions of the reflective electrode from regions without any metal layer (at least including the first metal layer and the second metal layer). , that is, it is defined by a region where a plurality of first patterned regions and a plurality of second patterned regions overlap. In other words, the plurality of third patterned portions of the reflective electrode substantially correspond to the overlapping regions of the plurality of first patterned regions and the plurality of second patterned regions in the normal direction of the substrate, so as to define the penetration Area. Based on this, the pixel structure of the present invention can not reduce the areas of the first metal layer for forming the first storage electrode and the second metal layer for forming the second storage electrode as the penetration region. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased to store a larger voltage, thereby having good electrical properties.

10, 20, 30: pixel structure A-A', B-B': section line CH: semiconductor layer Cst1: storage capacitor CVL: Common electrode line D: drain e1: first direction e2: the second direction DL: data line G: gate GS1: The first grayscale display area GS11: The first display block GS2: Second grayscale display area GS21, GS22: Second display block H: Contact window IL1: first insulating layer IL2: Second insulating layer M1: first metal layer M2: Second metal layer M3: third metal layer n: normal direction P1: The first patterned part P12: Overlapping area P2: The second patterned part P3: The third patterning part PE: pixel electrode PL: flat layer RE: Reflective electrode RR: Reflective area S: source SB: Substrate SE1: first storage electrode SE2: Second storage electrode SL: scan line T: Active element T1: The first active element T2: The second active element TR: penetration zone X: area

FIG. 1A is a schematic top view of a pixel structure according to a first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along the line A-A' in Fig. 1A . 1C is a schematic diagram of a transmission area and a reflection area of the pixel structure according to the first embodiment of the present invention. 2A is a schematic top view of a pixel structure according to a second embodiment of the present invention. FIG. 2B is a schematic diagram of the transmission area and the reflection area of the pixel structure according to the second embodiment of the present invention. 3A is a schematic top view of a pixel structure according to a third embodiment of the present invention. 3B is a schematic diagram of a transmission area and a reflection area of the pixel structure according to the third embodiment of the present invention. Fig. 4A is a schematic cross-sectional view of the first embodiment along the line B-B' in Fig. 3B . FIG. 4B is a schematic cross-sectional view of the second embodiment along the line B-B' in FIG. 3B . Fig. 4C is a schematic cross-sectional view of the third embodiment along the line B-B' in Fig. 3B . FIG. 4D is a schematic cross-sectional view of the fourth embodiment along the line B-B' in FIG. 3B . FIG. 5A is an enlarged schematic view of the first embodiment of the region X in FIG. 3B . FIG. 5B is an enlarged schematic view of the second embodiment of the region X in FIG. 3B . FIG. 5C is an enlarged schematic view of the third embodiment of the region X in FIG. 3B . FIG. 5D is an enlarged schematic view of the fourth embodiment of the region X in FIG. 3B .

A-A': section line

CH: semiconductor layer

CVL: Common electrode line

D: drain

e1: first direction

e2: the second direction

DL: data line

G: gate

H: Contact window

M1: first metal layer

M2: Second metal layer

n: normal direction

P1: The first patterned part

P12: Overlapping area

P2: The second patterned part

P3: The third patterning part

PE: pixel electrode

RE: Reflective electrode

S: source

SE1: first storage electrode

SE2: Second storage electrode

SL: scan line

T: Active element

Claims (9)

A pixel structure has a penetrating area and a reflective area, comprising: a substrate; a first metal layer, disposed on the substrate and including a plurality of first patterned areas and a first storage electrode; a first insulating layer, disposed on on the substrate and covering the first metal layer; the second metal layer is arranged on the first insulating layer and includes a plurality of second patterned regions and a second storage electrode; the second insulating layer is arranged on the first insulating layer on the first insulating layer and covering the second metal layer; a flat layer, disposed on the second insulating layer; a pixel electrode, through the contact window passing through the second insulating layer and the flat layer and the second metal layer is electrically connected; and a reflective electrode is disposed on the pixel electrode and includes a plurality of third patterned regions, wherein the plurality of third patterned regions are in the normal direction of the substrate The overlapping area substantially corresponds to the plurality of first patterned areas and the plurality of second patterned areas to define the penetration area, wherein when defining the plurality of first patterned areas No other regions of the first metal layer serving as the first storage electrode are removed, and the second metal layer serving as the second storage electrode when the plurality of second patterned regions are defined No other areas of the metal layer are removed. The pixel structure of claim 1, wherein the penetration area is defined by the reflective electrode. The pixel structure of claim 1, wherein the penetration region is defined by the first metal layer. The pixel structure of claim 1, wherein the penetration region is defined by the second metal layer. The pixel structure of claim 1, further comprising a third metal layer disposed between the second insulating layer and the flat layer, wherein the penetration region is defined by the third metal layer out. The pixel structure of claim 1, wherein the penetration area is defined by the reflective electrode and the first metal layer. The pixel structure of claim 1, wherein the penetration area is defined by the reflective electrode and the second metal layer. The pixel structure of claim 5, wherein the penetration region is defined by the reflective electrode, the first metal layer, the second metal layer, and the third metal layer. The pixel structure according to claim 1, comprising a first grayscale display area and a second grayscale display area, wherein the first grayscale display area includes a first display area, and the second grayscale display area includes a first display area. The secondary display area includes two second display blocks.

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