TW202046498A - Pixel structure - Google Patents

Abstract

A pixel structure including a substrate, a scan line, a data line, an active component, a pixel electrode, a reflective electrode and a shield electrode is provided. The scan line and the data line are disposed on the substrate. The scan line is extended in a first direction, and the data line is extended in a second direction. The active component is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active component. The reflective electrode is disposed on the pixel electrode and is electrically connected to the pixel electrode. The shield electrode is disposed between the pixel electrode and the substrate. The shield electrode covers the scan line and the data line at least.

Description

Pixel structure

The present invention relates to a pixel structure.

When driving the pixel structure of the display panel, the scan lines and data lines will receive signals respectively, and the above signals will affect the pixel electrodes located above the scan lines and the data lines, so that the pixel electrodes are affected by the turning of the liquid crystal molecules. Interference, which in turn causes the light transmittance of the display panel to decrease.

The conventional method to solve the above problem is to provide an organic insulating layer between the pixel electrode and the scan line and the data line to block the signal from the scan line and the data line. However, the material used to form the organic insulating layer is expensive and Therefore, the manufacturing cost of the display panel is increased.

The invention provides a pixel structure, which does not affect the deflection of liquid crystal molecules during driving and has low cost.

The pixel structure of the present invention includes a substrate, scan lines, data lines, active components, pixel electrodes, reflective electrodes, and shielding electrodes. The scan line and the data line are arranged on the substrate. The scan line extends in the first direction, and the data line extends in the second direction. The active device is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active element. The reflective electrode is arranged on the pixel electrode and is electrically connected to the pixel electrode. The shielding electrode is arranged between the pixel electrode and the substrate. The shielding electrode covers at least the scan line and the data line.

In an embodiment of the present invention, the above-mentioned active device includes a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. The gate and the scan line are the same metal layer, and the source and drain and the data line are the same metal layer. The source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode. The source and drain partially cover the semiconductor layer.

In an embodiment of the present invention, the aforementioned pixel structure further includes a common electrode line extending in the first direction. The common electrode line and the scan line are the same metal layer.

In an embodiment of the present invention, the aforementioned shielding electrode exposes the semiconductor layer that is not covered by the source electrode and the drain electrode.

In an embodiment of the present invention, the horizontal distance between the aforementioned shielding electrode and the semiconductor layer not covered by the source and drain electrodes is 1 μm-10 μm.

In an embodiment of the present invention, the above-mentioned shielding electrode covers the active device.

In an embodiment of the present invention, the distance between the aforementioned data line and the shielding electrode is 0.15 μm to 1 μm.

In an embodiment of the present invention, the thickness of the aforementioned shielding electrode is 0.15 μm to 0.6 μm.

In an embodiment of the present invention, an insulating layer is provided between the aforementioned pixel electrode and the shielding electrode. The insulating layer covers the shielding electrode.

In an embodiment of the present invention, the thickness of the above-mentioned insulating layer is 1 μm-10 μm.

Based on the above, the pixel structure of the present invention includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scan line and the data line. The layout design can prevent the pixel structure from affecting the liquid crystal molecules during driving. The degree of deflection caused the display panel to have a problem of decreased light transmittance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, the present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, for example: up, down, left, right, front or back, etc., only refer to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate but not to limit the present invention.

FIG. 1A is a schematic top view of the pixel structure of the first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along the line A1-A1' in Fig. 1A. FIG. 1C is a schematic diagram of the transmission area and the reflection area of the pixel structure according to an embodiment of the present invention.

1A, 1B, and 1C, the pixel structure 10 of this embodiment includes a substrate 100, a first metal layer M1, a first insulating layer 120, a second metal layer M2, a second insulating layer 140, and a shielding electrode ME, the third insulating layer 150, the pixel electrode PE, and the reflective electrode RE. It should be noted here that, in order to simplify the drawing, the drawing of the pixel electrode PE and the reflective electrode RE is omitted in FIG. 1A.

The substrate 100 is, for example, a flexible substrate, which can be a polymer substrate or a plastic substrate, but the invention is not limited thereto. In other embodiments, the substrate 100 may also be, for example, a rigid substrate, which may be a glass substrate, a quartz substrate, or a silicon substrate.

The first metal layer M1 is provided on the substrate 100, for example. The method for forming the first metal layer M1 is, for example, by using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a photolithographic etching process. For example, a first metal material layer (not shown) can be formed on the substrate 100 by using a physical vapor deposition method or a metal chemical vapor deposition method. Then, a patterned photoresist layer (not shown) is formed on the first metal material layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the first metal material layer to form the first metal layer M1.

The first metal layer M1 may, for example, include a gate electrode G, a scan line SL, a common electrode line CVL, and a first storage electrode 110. The scan line SL and the common electrode line CVL extend in the first direction D1, for example. The gate G, for example, is electrically connected to the corresponding scan line SL to receive the corresponding gate signal. The first storage electrode 110 may, for example, form a storage capacitor Cst1 with the first insulating layer 120 and the second metal layer M2 which will be described later. The common electrode line CVL can be used, for example, to supply a common voltage. The storage capacitor Cst1 may be electrically connected to the common electrode line CVL, and receive the common voltage supplied through the common electrode line CVL.

In an embodiment, the first metal layer M1 may further include a common electrode line CVL. The common electrode line CVL, for example, also extends in the first direction D1. The common electrode line CVL can be used, for example, to supply a common voltage. The storage capacitor Cst1 may be electrically connected to the first common electrode line CVL and receive the common voltage supplied through the common electrode line CVL.

The first insulating layer 120 is, for example, disposed on the substrate 100 and covers the first metal layer M1. That is, the first insulating layer 120 may cover the gate electrode G, the scan line SL, the common electrode line CVL, and the first storage electrode 110. The method of forming the first insulating layer 120 is, for example, by using a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the first insulating layer 120 can be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials), an organic material (for example: polyimide) Resin, epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited to this. The first insulating layer 120 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the first insulating layer 120 may also have a multilayer structure.

The second metal layer M2 is disposed on the first insulating layer 120, for example. The method for forming the second metal layer M2 is, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a second metal material layer (not shown) can be formed on the first insulating layer 120 by using a physical vapor deposition method or a metal chemical vapor deposition method. Then, a patterned photoresist layer (not shown) is formed on the second metal material layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the second metal material layer to form the second metal layer M2.

The second metal layer M2 may, for example, include a data line DL, a source electrode S, a drain electrode D, and a second storage electrode 130. The data line DL extends, for example, in a second direction D2 orthogonal to the first direction D1. The source electrode S is, for example, electrically connected to the corresponding data line DL to receive the corresponding data signal. The second storage electrode 130, for example, the first storage electrode 110 and the first insulating layer 120 located between the first storage electrode 110 and the second storage electrode 130 form a storage capacitor Cst1. The storage capacitor Cst1 can be used to store voltage, and the stored voltage can affect the deflection state of the liquid crystal molecules (not shown).

In an embodiment, the pixel structure 10 may further include a semiconductor layer SE. The semiconductor layer SE may be formed, for example, after forming the first insulating layer 120. That is, the semiconductor layer SE is disposed on the first insulating layer 120, for example.

The semiconductor layer SE is formed by, for example, a photolithography process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a semiconductor material layer (not shown) on the first insulating layer 120 first. Next, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the semiconductor material layer to form the semiconductor layer SE. The material of the semiconductor layer SE can be, for example, amorphous silicon, but the invention is not limited to this. The material of the semiconductor layer SE can also be, for example, polycrystalline silicon, microcrystalline silicon, single crystal silicon, nanocrystalline silicon, or other semiconductor materials or metal oxide semiconductor materials with different lattice arrangements.

In this embodiment, the gate electrode G, the source electrode S, the drain electrode D and the semiconductor layer SE can constitute the active device T. The semiconductor layer SE may be provided corresponding to the gate electrode G, and partially covered by the source electrode S and the drain electrode D, for example. The semiconductor layer SE that is not covered by the source electrode S and the drain electrode D can be used as the channel layer CH of the active device T. The active device T is, for example, any bottom gate type thin film transistor well known to those skilled in the art. However, although this embodiment takes the bottom gate type thin film transistor as an example, the present invention is not limited to this. In other embodiments, the active device T is, for example, a top gate type thin film transistor or other suitable types of thin film transistors.

The second insulating layer 140 is, for example, disposed on the first insulating layer 120 and covers the second metal layer M2. That is, the second insulating layer 140 may cover the data line DL, the source S, the drain D, and the second storage electrode 130. The method for forming the second insulating layer 140 is, for example, by using a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the second insulating layer 140 can be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (for example, polyimide). Resin, epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited to this. The second insulating layer 140 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the second insulating layer 140 may also have a multilayer structure.

The shielding electrode ME is, for example, disposed on the second insulating layer 140. The formation method of the shielding electrode ME is, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a shielding metal material layer (not shown) on the second insulating layer 140 first. Next, a patterned photoresist layer (not shown) is formed on the shielding metal material layer. Afterwards, using the patterned photoresist layer as a mask, an etching process is performed on the shielding metal material layer to form the shielding electrode ME.

The shielding electrode ME may be electrically connected to another common electrode line (not shown) to receive a common voltage supplied through the common electrode line, or the shielding electrode ME may be grounded. In an embodiment, the thickness T1 of the shielding electrode ME is 0.15 μm to 0.6 μm. In a preferred embodiment, the thickness T1 of the shielding electrode ME is 0.2 μm to 0.4 μm.

In this embodiment, the shielding electrode ME is provided corresponding to the scan line SL and the data line DL. In detail, the shielding electrode ME covers the scan line SL and the data line DL. Based on this, when the pixel structure 10 is driven, the gate drive signal through the scan line SL and the source drive signal through the data line DL can be blocked by the shielding electrode ME without affecting the voltage received by the pixel electrode E, so that the picture The element electrode E can control the turning of the liquid crystal molecules (not shown) without hindrance, thereby avoiding affecting the transmittance and reflectance of the display panel (not shown).

There is a specific vertical distance d _p between the shielding electrode ME and the data line DL, which is substantially the thickness of the second insulating layer 140. In one embodiment, the vertical distance d _p between the shielding electrode ME and the data line DL is 0.15 μm to 1 μm. In this embodiment, the vertical distance d _p between the shielding electrode ME and the data line DL is 0.3 μm. When the vertical distance d _p between the shielding electrode ME and the data line DL is larger, it means that the thickness of the second insulating layer 140 is thicker, which makes the data line DL and the scan line SL have less influence on the pixel electrode PE.

In addition, the shielding electrode ME of this embodiment exposes the semiconductor layer SE (ie, the channel layer CH) that is not covered by the source electrode S and the drain electrode D. In detail, the shielding electrode ME has an opening O exposing the channel layer CH, but the opening O not only exposes the channel layer CH, it also exposes part of the source S and drain D, so that the shielding electrode ME and the channel layer CH There is a specific horizontal distance d _{h between them} , as shown in Figure 1A and Figure 1B. In an embodiment, the horizontal distance d _h between the shielding electrode ME and the channel layer CH is 1 μm-10 μm. In a preferred embodiment, the horizontal distance d _h between the shielding electrode ME and the channel layer CH is 1.5 μm-3 μm. In the case that there is a specific horizontal distance d _h between the shielding electrode ME and the channel layer CH, it prevents the active device T from being electrically offset due to the arrangement of the shielding electrode ME.

The third insulating layer 150 is, for example, disposed on the second insulating layer 140 and covers the shielding electrode ME. The third insulating layer 150 is formed by, for example, physical vapor deposition method or chemical vapor deposition method. In this embodiment, the material of the third insulating layer 150 can be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (for example, polyimide). Resin, epoxy resin or acrylic resin) or a combination of the above, but the present invention is not limited to this. The third insulating layer 150 may have a single-layer structure, but the present invention is not limited thereto. In other embodiments, the third insulating layer 150 may also have a multilayer structure.

The pixel electrode PE is disposed on the third insulating layer 150, for example. The pixel electrode PE is formed by, for example, physical vapor deposition or metal chemical vapor deposition followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a pixel electrode material layer (not shown) on the third insulating layer 150 first. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the pixel electrode material layer to form the pixel electrode PE. The material of the pixel electrode PE may be, for example, a metal oxide conductive material (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In an embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through a contact window H penetrating the second insulating layer 140 and the third insulating layer 150. In detail, the pixel electrode PE is electrically connected to the drain D of the active device T, for example.

The reflective electrode RE is provided on the pixel electrode PE, for example. The method for forming the reflective electrode RE is, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a photolithographic etching process. For example, a physical vapor deposition method or a metal chemical vapor deposition method may be used to form a reflective electrode material layer (not shown) on the pixel electrode PE. Next, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the reflective electrode material layer to form the reflective electrode RE.

The reflective electrode RE can be formed of, for example, a metal material with a reflectivity of ≥90%. In this embodiment, the material of the reflective electrode RE is aluminum, silver or an alloy thereof, but the present invention is not limited thereto.

In an embodiment, the pixel structure 10 includes a reflection area RR and a transmission area TR. The reflection area RR is located on one side of the transmission area TR, for example. The reflective electrode RE is, for example, disposed in the reflective area RR to reflect external ambient light or light emitted by the backlight. For example, only an insulating layer or a transparent electrode (not shown) is provided in the penetrating area TR so that ambient light or backlight from outside can pass through. In general, the placement position of the reflective electrode RE can define the reflective area RR and the penetration area TR.

In this embodiment, the pixel structure includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers the scan line and the data line. The layout design can make the signal of the scan line and the data line not affect the The pixel electrode above it allows the pixel electrode to control the turning of the liquid crystal molecules without hindrance, thereby improving the problem of the drop in light transmittance caused by the pixel structure of the present embodiment during driving.

In addition, there is a specific horizontal distance between the shielding electrode and the channel layer in this embodiment, which can avoid affecting the electrical properties of the active device.

2A is a schematic top view of the pixel structure of the second embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the line A2-A2' in Fig. 2A. It must be noted here that the embodiments shown in FIGS. 2A and 2B respectively use the element numbers and part of the content of the embodiments in FIGS. 1A and 1B, wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the description and effects of the foregoing embodiments. The following embodiments will not be repeated, and at least part of the descriptions not omitted in the embodiments shown in FIG. 2A and FIG. 2B can be referred to the subsequent content.

2A and 2B at the same time, in the embodiment depicted in FIGS. 2A and 2B, the shielding electrode ME of the pixel structure 20 may not only cover the scan line SL and the data line DL, but may only expose the channel layer CH and part of the source S and drain D on the semiconductor layer SE. Based on this, as shown in FIG. 2B, the shielding electrode ME of this embodiment may further include a third storage electrode 160. The third storage electrode 160, for example, the second storage electrode 130 and the second insulating layer 140 located between the third storage electrode 160 and the second storage electrode 130 form a storage capacitor Cst2. The storage capacitors Cst1 and Cst2 can be used to store voltage, and the magnitude of the stored voltage can affect the deflection state of the liquid crystal molecules.

3A is a schematic top view of the pixel structure of the third embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along the line A3-A3' in Fig. 3A. It must be noted here that the embodiments shown in FIGS. 3A and 3B respectively use the element numbers and part of the content of the embodiments in FIGS. 1A and 1B, wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the description and effects of the foregoing embodiments. The following embodiments will not be repeated, and at least part of the descriptions not omitted in the embodiments shown in FIG. 3A and FIG. 3B may refer to the subsequent content.

Please refer to FIGS. 3A and 3B at the same time. In the embodiments shown in FIGS. 3A and 3B, the shielding electrode ME of the pixel structure 30 can further cover the channel layer CH. Without requiring a specific horizontal distance d _h between the shielding electrode ME and the channel layer CH, it will be easier to manufacture in terms of manufacturing process.

4A is a schematic top view of the pixel structure of the fourth embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line A4-A4' in Fig. 4A. It must be noted here that the embodiments shown in FIGS. 4A and 4B respectively use the element numbers and part of the content of the embodiments in FIGS. 2A and 2B, wherein the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the description and effects of the foregoing embodiments. The following embodiments will not be repeated, and at least part of the descriptions not omitted in the embodiments shown in FIGS. 4A and 4B can be referred to the subsequent content.

Please refer to FIGS. 4A and 4B at the same time. In the embodiment shown in FIGS. 4A and 4B, the shielding electrode ME of the pixel structure 40 may further cover the channel layer CH and include the third storage electrode 160. Without requiring a specific horizontal distance d _h between the shielding electrode ME and the channel layer CH, it will be easier to manufacture in terms of manufacturing process.

5A is a schematic top view of the pixel structure of the fifth embodiment of the present invention. Fig. 5B is a schematic cross-sectional view taken along the line A5-A5' in Fig. 5A. It must be noted here that the embodiments shown in FIGS. 5A and 5B respectively use the element numbers and part of the content of the embodiments in FIGS. 1A and 1B, and the same or similar numbers are used to represent the same or similar elements, and The description of the same technical content is omitted. For the description of the omitted parts, please refer to the description and effects of the foregoing embodiments. The following embodiments will not be repeated. For at least part of the descriptions not omitted in the embodiments shown in FIG. 5A and FIG. 5B, please refer to the subsequent content.

Please refer to FIGS. 5A and 5B at the same time. In the embodiment shown in FIGS. 5A and 5B, the third insulating layer 150 in the pixel structure 50 is made of organic material, and has a thickness T2 of, for example, 1 μm~ 10μm. In a preferred embodiment, the third insulating layer 150 has a thickness T2 of 2 μm to 3 μm. When the third insulating layer 150 has a greater thickness, it increases the distance between the data line DL or the scan line SL and the pixel electrode E, and by combining the layout design of the shielding electrode ME, the data line DL and the scan line The influence of SL on the pixel electrode E is minimized.

To sum up, the pixel structure of the present invention includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scan line and the data line. The layout design can make the signal of the scan line and the data line The pixel electrode located above it is not affected, so that the pixel electrode can control the turning of the liquid crystal molecules without hindrance, thereby improving the problem of the drop in light transmittance and reflectance caused by the pixel structure during driving.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 20, 30, 40, 50: pixel structure 100: substrate 110: first storage electrode 120: first insulating layer 130: second storage electrode 140: second insulating layer 150: third insulating layer 160: third Storage electrodes A1-A1', A2-A2', A3-A3', A4-A4', A5-A5': cross section CH: channel layer Cst1, Cst2: storage capacitor CVL: common electrode line D: drain d _h : Horizontal distance d _p : vertical distance DL: data line D1: first direction D2: second direction G: gate H: contact window ME: shielding electrode M1: first metal layer M2: second metal layer O: opening PE : Pixel electrode RE: reflective electrode RR: reflective area S: source SE: semiconductor layer SL: scanning line T: active element T1, T2: thickness TR: penetration area

FIG. 1A is a schematic top view of the pixel structure of the first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along the line A1-A1' in Fig. 1A. FIG. 1C is a schematic diagram of the transmission area and the reflection area of the pixel structure according to an embodiment of the present invention. 2A is a schematic top view of the pixel structure of the second embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the line A2-A2' in Fig. 2A. 3A is a schematic top view of the pixel structure of the third embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along the line A3-A3' in Fig. 3A. 4A is a schematic top view of the pixel structure of the fourth embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line A4-A4' in Fig. 4A. 5A is a schematic top view of the pixel structure of the fifth embodiment of the present invention. Fig. 5B is a schematic cross-sectional view taken along the line A5-A5' in Fig. 5A.

100: substrate

110: The first storage electrode

120: first insulating layer

130: second storage electrode

140: second insulating layer

150: third insulating layer

A1-A1’: Cut line

CH: Channel layer

Cst1: storage capacitor

D: Dip pole

d _h : horizontal distance

d _p : vertical distance

G: Gate

H: Contact window

ME: shield electrode

M1: The first metal layer

M2: second metal layer

O: opening

PE: pixel electrode

RE: reflective electrode

RR: reflection area

S: source

SE: semiconductor layer

T: Active component

T1: thickness

TR: penetration zone

Claims (10)

A pixel structure, including: Substrate Scan lines and data lines are arranged on the substrate, wherein the scan lines extend in a first direction, and the data lines extend in a second direction; Active components are electrically connected to the corresponding scan lines and the corresponding data lines; The pixel electrode is electrically connected to the active element; The reflective electrode is arranged on the pixel electrode and is electrically connected to the pixel electrode; and The shielding electrode is arranged between the pixel electrode and the substrate, wherein the shielding electrode covers at least the scan line and the data line. The pixel structure according to the first item of the patent application, wherein the active element includes a gate, a source, a drain, and a semiconductor layer, the gate and the scan line are the same metal layer, and the source The electrode and the drain electrode are the same metal layer as the data line, the source electrode is electrically connected to the data line, the drain electrode is electrically connected to the pixel electrode, and the source electrode and The drain partially covers the semiconductor layer. The pixel structure described in claim 1 further includes a common electrode line extending in the first direction, and the common electrode line and the scan line are the same metal layer. The pixel structure according to the second item of the scope of patent application, wherein the shielding electrode exposes the semiconductor layer that is not covered by the source electrode and the drain electrode. In the pixel structure described in item 4 of the scope of patent application, the horizontal distance between the shielding electrode and the semiconductor layer not covered by the source and drain is 1 μm-10 μm. According to the pixel structure described in claim 1, wherein the shielding electrode covers the active element. According to the pixel structure described in item 1 of the scope of patent application, the vertical distance between the data line and the shielding electrode is 0.15 μm to 1 μm. In the pixel structure described in item 1 of the scope of patent application, the thickness of the shielding electrode is 0.15 μm to 0.6 μm. The pixel structure according to the first item of the scope of patent application, wherein an insulating layer is provided between the pixel electrode and the shielding electrode, and the insulating layer covers the shielding electrode. In the pixel structure described in item 9 of the scope of patent application, the thickness of the insulating layer is 1 μm-10 μm.

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