TWM584444U - Pixel structure - Google Patents

Abstract

A pixel structure including a substrate, a scan line, a data line, an active component, a pixel electrode, a reflective electrode and a shield electrode is provided. The scan line and the data line are disposed on the substrate. The scan line is extended in a first direction, and the data line is extended in a second direction. The active component is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active component. The reflective electrode is disposed on the pixel electrode and is electrically connected to the pixel electrode. The shield electrode is disposed between the pixel electrode and the substrate. The shield electrode covers the scan line and the data line at least.

Description

Pixel structure

This new creation is about a pixel structure.

When driving the pixel structure of the display panel, the scanning line and the data line will each receive a signal, and the above signals will affect the pixel electrodes located above the scanning line and the data line, so that the pixel electrode is subject to the driving of liquid crystal molecules. Interference, which in turn causes the light transmittance of the display panel to decrease.

A conventional method for solving the above problem is to provide an organic insulating layer between the pixel electrode and the scanning line and the data line to block signals from the scanning line and the data line. However, the material used to form the organic insulating layer is expensive and expensive. Therefore, the manufacturing cost of the display panel is increased.

The novel creation provides a pixel structure, which does not affect the deflection of liquid crystal molecules when driven, and has low cost.

The pixel structure of the novel creation includes a substrate, a scanning line, a data line, an active element, a pixel electrode, a reflective electrode, and a shielding electrode. The scanning lines and the data lines are disposed on the substrate. The scan lines extend in a first direction, and the data lines extend in a second direction. The active component is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active element. The reflective electrode is disposed on the pixel electrode and is electrically connected to the pixel electrode. The shielding electrode is disposed between the pixel electrode and the substrate. The shielding electrode covers at least the scanning line and the data line.

In an embodiment of the present invention, the active device includes a gate, a source, a drain, and a semiconductor layer. The gate and scan lines are the same metal layer, and the source and drain electrodes are the same metal layer as the data lines. The source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode. The source and drain portions partially cover the semiconductor layer.

In an embodiment of the present invention, the above pixel structure further includes a common electrode line extending in a first direction. The common electrode line is the same metal layer as the scan line.

In an embodiment of the present invention, the above-mentioned shielding electrode exposes a semiconductor layer that is not covered by the source and the drain.

In an embodiment of the present invention, the horizontal distance between the shielding electrode and the semiconductor layer not covered by the source and the drain is 1 μm to 10 μm.

In an embodiment of the present invention, the above-mentioned shielding electrode covers the active device.

In an embodiment of the present invention, a distance between the data line and the shielding electrode is 0.15 μm to 1 μm.

In an embodiment of the present invention, the thickness of the shielding electrode is 0.15 μm to 0.6 μm.

In an embodiment of the present invention, an insulating layer is provided between the pixel electrode and the shielding electrode. The insulating layer covers the shielding electrode.

In an embodiment of the present invention, the thickness of the insulation layer is 1 μm to 10 μm.

Based on the above, the pixel structure created by the new type includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scanning line and the data line. This layout design can avoid the pixel structure from affecting the liquid crystal during driving. The degree of molecular deflection causes a problem that the light transmittance of the display panel decreases.

In order to make the above-mentioned features and advantages of the novel creation more comprehensible, embodiments are described below in detail with the accompanying drawings as follows.

In the following, the novel creation will be explained more fully with reference to the drawings of this embodiment. However, the novel creation can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front, or rear, are only directions referring to the attached drawings. Therefore, the terminology used is used to explain and is not used to limit the novel creation.

FIG. 1A is a schematic top view of a pixel structure of a first embodiment of the novel creation. FIG. 1B is a schematic cross-sectional view taken along the line A1-A1 'in FIG. 1A. FIG. 1C is a schematic diagram of a penetrating region and a reflecting region of a pixel structure according to an embodiment of the novel creation.

Please refer to FIGS. 1A, 1B, and 1C at the same time. The pixel structure 10 of this embodiment includes a substrate 100, a first metal layer M1, a first insulating layer 120, a second metal layer M2, a second insulating layer 140, and a shielding electrode. The ME, the third insulating layer 150, the pixel electrode PE, and the reflective electrode RE. It should be particularly noted here that, for the sake of simplicity of the drawings, the pixel electrodes PE and the reflective electrodes RE are omitted in FIG. 1A.

The substrate 100 is, for example, a flexible substrate, which may be a polymer substrate or a plastic substrate, but the novel creation is not limited thereto. In other embodiments, the substrate 100 may also be, for example, a rigid substrate, which may be a glass substrate, a quartz substrate, or a silicon substrate.

The first metal layer M1 is provided on the substrate 100, for example. The method for forming the first metal layer M1 is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a first metal material layer (not shown) may be formed on the substrate 100 first by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the first metal material layer. Thereafter, the patterned photoresist layer is used as a mask, and an etching process is performed on the first metal material layer to form a first metal layer M1.

The first metal layer M1 may include, for example, a gate G, a scan line SL, a common electrode line CVL, and a first storage electrode 110. The scan lines SL and the common electrode lines CVL extend in the first direction D1, for example. The gate G is electrically connected to the corresponding scan line SL to receive the corresponding gate signal. The first storage electrode 110 may, for example, form a storage capacitor Cst1 with the first insulating layer 120 and the second metal layer M2 to be described later. The common electrode line CVL may be used to supply a common voltage, for example. The storage capacitor Cst1 can be electrically connected to the common electrode line CVL, and receives a common voltage supplied through the common electrode line CVL.

In one embodiment, the first metal layer M1 may further include a common electrode line CVL. The common electrode line CVL also extends, for example, in the first direction D1. The common electrode line CVL may be used to supply a common voltage, for example. The storage capacitor Cst1 is electrically connected to the first common electrode line CVL, and receives a common voltage supplied through the common electrode line CVL.

The first insulating layer 120 is, for example, disposed on the substrate 100 and covers the first metal layer M1. That is, the first insulating layer 120 may cover the gate electrode G, the scan line SL, the common electrode line CVL, and the first storage electrode 110. A method of forming the first insulating layer 120 is, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the first insulating layer 120 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide) Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The first insulating layer 120 may be a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the first insulating layer 120 may also have a multilayer structure.

The second metal layer M2 is disposed on the first insulating layer 120, for example. The method for forming the second metal layer M2 is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithographic etching process. For example, a second metal material layer (not shown) may be formed on the first insulating layer 120 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the second metal material layer. Then, the second metal material layer is etched by using the patterned photoresist layer as a mask to form a second metal layer M2.

The second metal layer M2 may include, for example, a data line DL, a source S, a drain D, and a second storage electrode 130. The data line DL extends, for example, in a second direction D2 orthogonal to the first direction D1. The source S is electrically connected to the corresponding data line DL, for example, to receive the corresponding data signal. The second storage electrode 130 forms, for example, a storage capacitor Cst1 with the first storage electrode 110 and the first insulating layer 120 located between the first storage electrode 110 and the second storage electrode 130. The storage capacitor Cst1 can be used to store voltage, and the stored voltage can affect the deflection state of liquid crystal molecules (not shown).

In one embodiment, the pixel structure 10 may further include a semiconductor layer SE. The semiconductor layer SE may be formed, for example, after the first insulating layer 120 is formed. That is, the semiconductor layer SE is provided on the first insulating layer 120, for example.

The method for forming the semiconductor layer SE is formed by, for example, a lithography process. For example, a semiconductor material layer (not shown) may be formed on the first insulating layer 120 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. Thereafter, the patterned photoresist layer is used as a mask, and an etching process is performed on the semiconductor material layer to form a semiconductor layer SE. The material of the semiconductor layer SE may be, for example, amorphous silicon, but the novel creation is not limited thereto. The material of the semiconductor layer SE may also be, for example, polycrystalline silicon, microcrystalline silicon, single crystal silicon, nanocrystalline silicon, or other semiconductor materials or metal oxide semiconductor materials having different lattice arrangements.

In this embodiment, the gate G, the source S, the drain D, and the semiconductor layer SE may constitute an active device T. The semiconductor layer SE may be provided corresponding to the gate G, for example, and partially covered with the source S and the drain D. The semiconductor layer SE not covered by the source S and the drain D can be used as the channel layer CH of the active device T. The active device T is, for example, any bottom-gate thin-film transistor known to those skilled in the art. However, although the present embodiment takes the bottom gate type thin film transistor as an example, the novel creation is not limited to this. In other embodiments, the active device T is, for example, a top-gate thin film transistor or other suitable thin film transistors.

The second insulating layer 140 is disposed on, for example, the first insulating layer 120 and covers the second metal layer M2. That is, the second insulating layer 140 may cover the data line DL, the source S, the drain D, and the second storage electrode 130. The method for forming the second insulating layer 140 is, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the second insulating layer 140 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The second insulating layer 140 may have a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the second insulating layer 140 may have a multilayer structure.

The shielding electrode ME is provided on, for example, the second insulating layer 140. The shielding electrode ME is formed by, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a physical metal deposition method or a metal chemical vapor deposition method may be first used to form a shielding metal material layer (not shown) on the second insulating layer 140. Next, a patterned photoresist layer (not shown) is formed on the shielding metal material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the shielding metal material layer to form a shielding electrode ME.

The shielding electrode ME may be electrically connected to another common electrode line (not shown) to receive a common voltage supplied through the common electrode line, or the shielding electrode ME may be grounded. In one embodiment, the thickness T1 of the shielding electrode ME is 0.15 μm to 0.6 μm. In a preferred embodiment, the thickness T1 of the shielding electrode ME is 0.2 μm to 0.4 μm.

In this embodiment, the shielding electrode ME is provided corresponding to the scan line SL and the data line DL. In detail, the shielding electrode ME covers the scanning lines SL and the data lines DL. Based on this, when driving the pixel structure 10, the gate driving signal through the scanning line SL and the source driving signal through the data line DL can be blocked by the shielding electrode ME without affecting the voltage received by the pixel electrode E, so that the picture The element electrode E can control the turning of liquid crystal molecules (not shown) without hindrance, thereby avoiding affecting the light transmittance and reflectance of the display panel (not shown).

There is a specific vertical distance d _p between the shielding electrode ME and the data line DL, which is substantially the thickness of the second insulating layer 140. In one embodiment, the vertical distance d _p between the shielding electrode ME and the data line DL is 0.15 μm to 1 μm. In this embodiment, the vertical distance d _p between the shielding electrode ME and the data line DL is 0.3 μm. When the vertical distance d _p between the shielding electrode ME and the data line DL is larger, it means that the thickness of the second insulating layer 140 is thicker, which makes the data line DL and the scanning line SL have less influence on the pixel electrode PE.

In addition, the shielding electrode ME of this embodiment exposes the semiconductor layer SE (ie, the channel layer CH) that is not covered by the source S and the drain D. In detail, the shielding electrode ME has an opening O exposing the channel layer CH, but the opening O not only exposes the channel layer CH, but also exposes part of the source S and the drain D, so that the shielding electrode ME and the channel layer CH There is a specific horizontal distance d _{h between them} , as shown in FIG. 1A and FIG. 1B. In one embodiment, the horizontal distance d _h between the shielding electrode ME and the channel layer CH is 1 μm to 10 μm. In a preferred embodiment, the horizontal distance d _h between the shielding electrode ME and the channel layer CH is 1.5 μm to 3 μm. In the case where there is a specific horizontal distance d _h between the shielding electrode ME and the channel layer CH, it prevents the active element T from being electrically displaced due to the setting of the shielding electrode ME.

The third insulating layer 150 is disposed on the second insulating layer 140 and covers the shielding electrode ME, for example. The third insulating layer 150 is formed by, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the third insulating layer 150 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide) Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The third insulating layer 150 may be a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the third insulating layer 150 may have a multilayer structure.

The pixel electrode PE is provided on the third insulating layer 150, for example. The pixel electrode PE is formed by, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a lithographic etching process. For example, a pixel electrode material layer (not shown) may be formed on the third insulating layer 150 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. After that, the patterned photoresist layer is used as a mask to perform an etching process on the pixel electrode material layer to form a pixel electrode PE. The material of the pixel electrode PE may be, for example, a metal oxide conductive material (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In one embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through a contact window H penetrating the second insulating layer 140 and the third insulating layer 150. In detail, the pixel electrode PE is electrically connected to the drain electrode D of the active device T, for example.

The reflective electrode RE is provided on the pixel electrode PE, for example. The method for forming the reflective electrode RE is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method followed by a lithographic etching process. For example, a reflective electrode material layer (not shown) may be formed on the pixel electrode PE first by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. Then, the patterned photoresist layer is used as a mask, and an etching process is performed on the reflective electrode material layer to form a reflective electrode RE.

The reflective electrode RE can be formed by using, for example, a metal material having a reflectivity ≧ 90%. In this embodiment, the material of the reflective electrode RE is aluminum, silver, or an alloy thereof, but the novel creation is not limited thereto.

In one embodiment, the pixel structure 10 includes a reflection region RR and a transmission region TR. The reflection region RR is, for example, located on one side of the transmission region TR. The reflective electrode RE is, for example, provided in the reflective region RR to reflect external ambient light or light emitted from a backlight source. For example, only an insulating layer or a transparent electrode (not shown) is provided in the transmissive region TR, and thus ambient light or a backlight source can be allowed to pass through. In general, the location of the reflective electrode RE can define a reflective region RR and a transmission region TR.

In this embodiment, the pixel structure includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers the scanning line and the data line. With this layout design, the signals of the scanning line and the data line do not affect the location of the signals. The pixel electrode above the pixel electrode can control the turning of the liquid crystal molecules without hindrance, thereby improving the problem that the pixel structure of this embodiment causes a decrease in light transmittance during driving.

In addition, there is a specific horizontal distance between the shielding electrode and the channel layer in this embodiment, which can avoid affecting the electrical properties of the active device.

FIG. 2A is a schematic top view of a pixel structure of a second embodiment of the novel creation. Fig. 2B is a schematic cross-sectional view taken along the line A2-A2 'in Fig. 2A. It must be noted here that the embodiments shown in FIG. 2A and FIG. 2B respectively use the component numbers and parts of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar reference numerals are used to indicate the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 2A and FIG. 2B is not omitted.

Please refer to FIG. 2A and FIG. 2B at the same time. In the embodiment shown in FIG. 2A and FIG. 2B, the shielding electrode ME of the pixel structure 20 may not only cover the scan lines SL and the data lines DL, but may only expose the channel layer, for example. CH and part of the source S and the drain D on the semiconductor layer SE. Based on this, as shown in FIG. 2B, the shielding electrode ME in this embodiment may further include a third storage electrode 160. The third storage electrode 160 forms, for example, a storage capacitor Cst2 with the second storage electrode 130 and the second insulating layer 140 located between the third storage electrode 160 and the second storage electrode 130. The storage capacitors Cst1 and Cst2 can be used to store voltage, and the stored voltage can affect the deflection state of the liquid crystal molecules.

FIG. 3A is a schematic top view of a pixel structure of a third embodiment of the novel creation. Fig. 3B is a schematic cross-sectional view taken along the line A3-A3 'in Fig. 3A. It must be noted here that the embodiments shown in FIG. 3A and FIG. 3B respectively use the component numbers and parts of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar reference numerals are used to represent the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 3A and FIG. 3B is not omitted.

Please refer to FIG. 3A and FIG. 3B simultaneously. In the embodiment shown in FIG. 3A and FIG. 3B, the shielding electrode ME of the pixel structure 30 may further cover the channel layer CH. Without the need to make the shielding electrode ME and the channel layer CH have a specific horizontal distance d _h , it may be easier to fabricate in the manufacturing process.

FIG. 4A is a schematic top view of a pixel structure of a fourth embodiment of the novel creation. Fig. 4B is a schematic cross-sectional view taken along the line A4-A4 'in Fig. 4A. It must be noted here that the embodiments shown in FIG. 4A and FIG. 4B respectively follow the component numbers and parts of the embodiments of FIG. 2A and FIG. 2B, wherein the same or similar reference numerals are used to represent the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 4A and FIG. 4B is not omitted.

Please refer to FIGS. 4A and 4B simultaneously. In the embodiment shown in FIGS. 4A and 4B, the shielding electrode ME of the pixel structure 40 may further cover the channel layer CH and include a third storage electrode 160. Without the need to make the shielding electrode ME and the channel layer CH have a specific horizontal distance d _h , it may be easier to fabricate in the manufacturing process.

FIG. 5A is a schematic top view of a pixel structure of a fifth embodiment of the novel creation. Fig. 5B is a schematic cross-sectional view taken along the line A5-A5 'in Fig. 5A. It must be noted here that the embodiments shown in FIG. 5A and FIG. 5B respectively follow the component numbers and parts of the embodiments of FIG. 1A and FIG. Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 5A and FIG. 5B is not omitted.

Please refer to FIGS. 5A and 5B at the same time. In the embodiment shown in FIGS. 5A and 5B, the third insulating layer 150 in the pixel structure 50 is made of an organic material and has a thickness T2 of, for example, 1 μm ~ 10 μm. In a preferred embodiment, the third insulating layer 150 has a thickness T2 of 2 μm to 3 μm. When the third insulating layer 150 has a larger thickness, it increases the distance between the data line DL or the scanning line SL and the pixel electrode E, and makes the data line DL and the scanning line by combining the layout design of the shielding electrode ME. The effect of SL on the pixel electrode E is minimized.

In summary, the pixel structure of the novel creation includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scanning line and the data line. This layout design can make the scanning line and the data line The signal does not affect the pixel electrode located above it, so that the pixel electrode can control the turning of the liquid crystal molecules without hindrance, thereby improving the problem that the light transmittance and reflectance of the pixel structure are reduced during driving.

Although this new type of creation has been disclosed as above by way of example, it is not intended to limit the new type of creation. Any person with ordinary knowledge in the technical field can make some changes without departing from the spirit and scope of this new type of creation Retouching, so the protection scope of this new type of creation shall be determined by the scope of the attached patent application.

10, 20, 30, 40, 50‧‧‧ pixel structure
100‧‧‧ substrate
110‧‧‧first storage electrode
120‧‧‧The first insulation layer
130‧‧‧Second storage electrode
140‧‧‧Second insulation layer
150‧‧‧third insulating layer
160‧‧‧Third storage electrode
A1-A1 ', A2-A2', A3-A3 ', A4-A4', A5-A5'‧‧‧
CH‧‧‧ Channel layer
Cst1, Cst2‧‧‧ storage capacitors
CVL‧‧‧Common electrode wire
D‧‧‧ Drain
d _h ‧‧‧horizontal distance
d _p ‧‧‧ vertical distance
DL‧‧‧Data Line
D1‧‧‧ first direction
D2‧‧‧ Second direction
G‧‧‧Gate
H‧‧‧Contact window
ME‧‧‧shielding electrode
M1‧‧‧First metal layer
M2‧‧‧Second metal layer
O‧‧‧ opening
PE‧‧‧Pixel electrode
RE‧‧‧Reflective electrode
RR‧‧‧Reflected area
S‧‧‧Source
SE‧‧‧Semiconductor Layer
SL‧‧‧scan line
T‧‧‧active element
T1, T2‧‧‧thickness
TR‧‧‧ Penetration zone

FIG. 1A is a schematic top view of a pixel structure of a first embodiment of the novel creation.
FIG. 1B is a schematic cross-sectional view of the section line A1-A1 'in FIG. 1A.
FIG. 1C is a schematic diagram of a penetrating region and a reflecting region of a pixel structure according to an embodiment of the novel creation.
FIG. 2A is a schematic top view of a pixel structure of a second embodiment of the novel creation.
FIG. 2B is a schematic cross-sectional view taken along a section line A2-A2 'in FIG. 2A.
FIG. 3A is a schematic top view of a pixel structure of a third embodiment of the novel creation.
FIG. 3B is a schematic cross-sectional view taken along a section line A3-A3 'in FIG. 3A.
FIG. 4A is a schematic top view of a pixel structure of a fourth embodiment of the novel creation.
FIG. 4B is a schematic cross-sectional view taken along section line A4-A4 'in FIG. 4A.
FIG. 5A is a schematic top view of a pixel structure of a fifth embodiment of the novel creation.
FIG. 5B is a schematic cross-sectional view taken along section line A5-A5 'in FIG. 5A.

Claims (10)

A pixel structure, including:
Substrate
Scanning lines and data lines are provided on the substrate, wherein the scanning lines extend along the first direction, and the data lines extend along the second direction;
An active element electrically connected to the corresponding scanning line and the corresponding data line;
The pixel electrode is electrically connected to the active element;
A reflective electrode is provided on the pixel electrode and is electrically connected to the pixel electrode; and a shielding electrode is provided between the pixel electrode and the substrate, wherein the shielding electrode covers at least the The scanning line and the data line. The pixel structure as described in item 1 of the patent application scope, wherein the active element includes a gate electrode, a source electrode, a drain electrode and a semiconductor layer, the gate electrode and the scan line are the same metal layer, and the source The drain electrode and the drain electrode are the same metal layer as the data line, the source electrode is electrically connected to the data line, the drain electrode is electrically connected to the pixel electrode, and the source electrode and The drain part partially covers the semiconductor layer. The pixel structure as described in item 1 of the patent application scope further includes a common electrode line extending toward the first direction, and the common electrode line and the scan line are the same metal layer. The pixel structure as described in item 2 of the patent application scope, wherein the shielding electrode exposes the semiconductor layer not covered by the source electrode and the drain electrode. The pixel structure as described in item 4 of the patent application range, wherein the horizontal distance between the shielding electrode and the semiconductor layer not covered by the source electrode and the drain electrode is 1 μm to 10 μm. The pixel structure as described in item 1 of the patent application scope, wherein the shielding electrode covers the active element. The pixel structure as described in item 1 of the patent application, wherein the vertical distance between the data line and the shielding electrode is 0.15 μm to 1 μm. The pixel structure as described in Item 1 of the patent application, wherein the thickness of the shielding electrode is 0.15 μm to 0.6 μm. The pixel structure as described in item 1 of the patent application scope, wherein an insulating layer is provided between the pixel electrode and the shielding electrode, and the insulating layer covers the shielding electrode. The pixel structure as described in item 9 of the patent application range, wherein the thickness of the insulating layer is 1 μm to 10 μm.