TWM584444U - Pixel structure - Google Patents

Pixel structure Download PDF

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TWM584444U
TWM584444U TW108207608U TW108207608U TWM584444U TW M584444 U TWM584444 U TW M584444U TW 108207608 U TW108207608 U TW 108207608U TW 108207608 U TW108207608 U TW 108207608U TW M584444 U TWM584444 U TW M584444U
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electrode
pixel
pixel structure
layer
line
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TW108207608U
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Chinese (zh)
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吳哲耀
周凱茹
江宜達
陳翰
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凌巨科技股份有限公司
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Abstract

A pixel structure including a substrate, a scan line, a data line, an active component, a pixel electrode, a reflective electrode and a shield electrode is provided. The scan line and the data line are disposed on the substrate. The scan line is extended in a first direction, and the data line is extended in a second direction. The active component is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active component. The reflective electrode is disposed on the pixel electrode and is electrically connected to the pixel electrode. The shield electrode is disposed between the pixel electrode and the substrate. The shield electrode covers the scan line and the data line at least.

Description

畫素結構Pixel structure

本新型創作是有關於一種畫素結構。This new creation is about a pixel structure.

在驅動顯示面板的畫素結構時,掃描線以及資料線會各自接收訊號,而上述訊號將會影響位於掃描線以及資料線上方的畫素電極,使得畫素電極在驅動液晶分子的轉向時受到干擾,進而導致顯示面板的透光率下降。When driving the pixel structure of the display panel, the scanning line and the data line will each receive a signal, and the above signals will affect the pixel electrodes located above the scanning line and the data line, so that the pixel electrode is subject to the driving of liquid crystal molecules. Interference, which in turn causes the light transmittance of the display panel to decrease.

習知的解決上述問題的作法為在畫素電極與掃描線以及資料線之間設置一層有機絕緣層,以阻隔來自掃描線以及資料線的訊號,然而,用於形成有機絕緣層的材料昂貴而因此提高了顯示面板的製造成本。A conventional method for solving the above problem is to provide an organic insulating layer between the pixel electrode and the scanning line and the data line to block signals from the scanning line and the data line. However, the material used to form the organic insulating layer is expensive and expensive. Therefore, the manufacturing cost of the display panel is increased.

本新型創作提供一種畫素結構,其於驅動時不影響液晶分子的偏轉,且成本低廉。The novel creation provides a pixel structure, which does not affect the deflection of liquid crystal molecules when driven, and has low cost.

本新型創作的畫素結構包括基板、掃描線、資料線、主動元件、畫素電極、反射電極以及遮蔽電極。掃描線與資料線設置於基板上。掃描線沿第一方向延伸,且資料線沿第二方向延伸。主動元件與對應的掃描線以及對應的資料線電性連接。畫素電極與主動元件電性連接。反射電極設置於畫素電極上且與畫素電極電性連接。遮蔽電極設置於畫素電極與基板之間。遮蔽電極至少覆蓋掃描線以及資料線。The pixel structure of the novel creation includes a substrate, a scanning line, a data line, an active element, a pixel electrode, a reflective electrode, and a shielding electrode. The scanning lines and the data lines are disposed on the substrate. The scan lines extend in a first direction, and the data lines extend in a second direction. The active component is electrically connected to the corresponding scan line and the corresponding data line. The pixel electrode is electrically connected to the active element. The reflective electrode is disposed on the pixel electrode and is electrically connected to the pixel electrode. The shielding electrode is disposed between the pixel electrode and the substrate. The shielding electrode covers at least the scanning line and the data line.

在本新型創作的一實施例中,上述的主動元件包括閘極、源極、汲極以及半導體層。閘極與掃描線為同一層金屬層,且源極以及汲極與資料線為同一層金屬層。源極與資料線電性連接,且汲極與畫素電極電性連接。源極以及汲極部分覆蓋半導體層。In an embodiment of the present invention, the active device includes a gate, a source, a drain, and a semiconductor layer. The gate and scan lines are the same metal layer, and the source and drain electrodes are the same metal layer as the data lines. The source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode. The source and drain portions partially cover the semiconductor layer.

在本新型創作的一實施例中,上述的畫素結構更包括朝第一方向延伸的共用電極線。共用電極線與掃描線為同一層金屬層。In an embodiment of the present invention, the above pixel structure further includes a common electrode line extending in a first direction. The common electrode line is the same metal layer as the scan line.

在本新型創作的一實施例中,上述的遮蔽電極暴露出未被源極以及汲極覆蓋的半導體層。In an embodiment of the present invention, the above-mentioned shielding electrode exposes a semiconductor layer that is not covered by the source and the drain.

在本新型創作的一實施例中,上述的遮蔽電極與未被源極以及汲極覆蓋的半導體層的水平距離為1μm~10μm。In an embodiment of the present invention, the horizontal distance between the shielding electrode and the semiconductor layer not covered by the source and the drain is 1 μm to 10 μm.

在本新型創作的一實施例中,上述的遮蔽電極覆蓋主動元件。In an embodiment of the present invention, the above-mentioned shielding electrode covers the active device.

在本新型創作的一實施例中,上述的資料線與遮蔽電極之間的距離為0.15μm~1μm。In an embodiment of the present invention, a distance between the data line and the shielding electrode is 0.15 μm to 1 μm.

在本新型創作的一實施例中,上述的遮蔽電極的厚度為0.15μm~0.6μm。In an embodiment of the present invention, the thickness of the shielding electrode is 0.15 μm to 0.6 μm.

在本新型創作的一實施例中,上述的畫素電極與遮蔽電極之間設置有絕緣層。絕緣層覆蓋遮蔽電極。In an embodiment of the present invention, an insulating layer is provided between the pixel electrode and the shielding electrode. The insulating layer covers the shielding electrode.

在本新型創作的一實施例中,上述的絕緣層的厚度為1μm~10μm。In an embodiment of the present invention, the thickness of the insulation layer is 1 μm to 10 μm.

基於上述,本新型創作的畫素結構包括設置於畫素電極與基板之間的遮蔽電極,且遮蔽電極至少覆蓋掃描線以及資料線,藉由此布局設計可避免畫素結構於驅動時影響液晶分子的偏轉程度,而使顯示面板產生透光率下降的問題。Based on the above, the pixel structure created by the new type includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scanning line and the data line. This layout design can avoid the pixel structure from affecting the liquid crystal during driving. The degree of molecular deflection causes a problem that the light transmittance of the display panel decreases.

為讓本新型創作的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the novel creation more comprehensible, embodiments are described below in detail with the accompanying drawings as follows.

以下將參照本實施例之圖式以更全面地闡述本新型創作。然而,本新型創作亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件,以下段落將不再一一贅述。另外,實施例中所提到的方向用語,例如:上、下、左、右、前或後等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明並非用來限制本新型創作。In the following, the novel creation will be explained more fully with reference to the drawings of this embodiment. However, the novel creation can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front, or rear, are only directions referring to the attached drawings. Therefore, the terminology used is used to explain and is not used to limit the novel creation.

圖1A為本新型創作的第一實施例的畫素結構的俯視示意圖。圖1B為圖1A中的剖線A1-A1’的剖面示意圖。圖1C為本新型創作的一實施例的畫素結構的穿透區與反射區的示意圖。FIG. 1A is a schematic top view of a pixel structure of a first embodiment of the novel creation. FIG. 1B is a schematic cross-sectional view taken along the line A1-A1 'in FIG. 1A. FIG. 1C is a schematic diagram of a penetrating region and a reflecting region of a pixel structure according to an embodiment of the novel creation.

請同時參照圖1A、圖1B以及圖1C,本實施例的畫素結構10包括基板100、第一金屬層M1、第一絕緣層120、第二金屬層M2、第二絕緣層140、遮蔽電極ME、第三絕緣層150、畫素電極PE以及反射電極RE。此處需特別說明的是,為使圖式簡潔,圖1A省略了畫素電極PE以及反射電極RE的繪示。Please refer to FIGS. 1A, 1B, and 1C at the same time. The pixel structure 10 of this embodiment includes a substrate 100, a first metal layer M1, a first insulating layer 120, a second metal layer M2, a second insulating layer 140, and a shielding electrode. The ME, the third insulating layer 150, the pixel electrode PE, and the reflective electrode RE. It should be particularly noted here that, for the sake of simplicity of the drawings, the pixel electrodes PE and the reflective electrodes RE are omitted in FIG. 1A.

基板100例如為可撓性基板,其可為聚合物基板或塑膠基板,但本新型創作不限於此。在其他實施例中,基板100也可例如為剛性基板,其可為玻璃基板、石英基板或矽基板。The substrate 100 is, for example, a flexible substrate, which may be a polymer substrate or a plastic substrate, but the novel creation is not limited thereto. In other embodiments, the substrate 100 may also be, for example, a rigid substrate, which may be a glass substrate, a quartz substrate, or a silicon substrate.

第一金屬層M1例如設置於基板100上。第一金屬層M1的形成方法例如是利用物理氣相沉積法或金屬化學氣相沉積法後再進行微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於基板100上形成第一金屬材料層(未繪示)。接著,於第一金屬材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對第一金屬材料層進行蝕刻製程,以形成第一金屬層M1。The first metal layer M1 is provided on the substrate 100, for example. The method for forming the first metal layer M1 is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a first metal material layer (not shown) may be formed on the substrate 100 first by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the first metal material layer. Thereafter, the patterned photoresist layer is used as a mask, and an etching process is performed on the first metal material layer to form a first metal layer M1.

第一金屬層M1可例如包括閘極G、掃描線SL、共用電極線CVL以及第一儲存電極110。掃描線SL以及共用電極線CVL例如朝第一方向D1延伸。閘極G例如與對應的掃描線SL電性連接以接收相應的閘極訊號。第一儲存電極110可例如與後續將介紹的第一絕緣層120以及第二金屬層M2構成儲存電容Cst1。共用電極線CVL可例如用於供應共用電壓。儲存電容Cst1可電性連接於共用電極線CVL,而接收經由共用電極線CVL供應的共用電壓。The first metal layer M1 may include, for example, a gate G, a scan line SL, a common electrode line CVL, and a first storage electrode 110. The scan lines SL and the common electrode lines CVL extend in the first direction D1, for example. The gate G is electrically connected to the corresponding scan line SL to receive the corresponding gate signal. The first storage electrode 110 may, for example, form a storage capacitor Cst1 with the first insulating layer 120 and the second metal layer M2 to be described later. The common electrode line CVL may be used to supply a common voltage, for example. The storage capacitor Cst1 can be electrically connected to the common electrode line CVL, and receives a common voltage supplied through the common electrode line CVL.

在一實施例中,第一金屬層M1可更包括共用電極線CVL。共用電極線CVL例如亦朝第一方向D1延伸。共用電極線CVL可例如用於供應共用電壓。儲存電容Cst1可電性連接於第一共用電極線CVL,而接收經由共用電極線CVL供應的共用電壓。In one embodiment, the first metal layer M1 may further include a common electrode line CVL. The common electrode line CVL also extends, for example, in the first direction D1. The common electrode line CVL may be used to supply a common voltage, for example. The storage capacitor Cst1 is electrically connected to the first common electrode line CVL, and receives a common voltage supplied through the common electrode line CVL.

第一絕緣層120例如設置於基板100上且覆蓋第一金屬層M1。亦即,第一絕緣層120可覆蓋閘極G、掃描線SL、共用電極線CVL以及第一儲存電極110。第一絕緣層120的形成方法例如是利用物理氣相沉積法或化學氣相沉積法而形成。在本實施例中,第一絕緣層120的材料可為無機材料(例如:氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層)、有機材料(例如:聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂)或上述之組合,但本新型創作不限於此。第一絕緣層120可為單層結構,但本新型創作不限於此。在其他實施例中,第一絕緣層120也可為多層結構。The first insulating layer 120 is, for example, disposed on the substrate 100 and covers the first metal layer M1. That is, the first insulating layer 120 may cover the gate electrode G, the scan line SL, the common electrode line CVL, and the first storage electrode 110. A method of forming the first insulating layer 120 is, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the first insulating layer 120 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide) Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The first insulating layer 120 may be a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the first insulating layer 120 may also have a multilayer structure.

第二金屬層M2例如設置於第一絕緣層120上。第二金屬層M2的形成方法例如是利用物理氣相沉積法或金屬化學氣相沉積法後再進行微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於第一絕緣層120上形成第二金屬材料層(未繪示)。接著,於第二金屬材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對第二金屬材料層進行蝕刻製程,以形成第二金屬層M2。The second metal layer M2 is disposed on the first insulating layer 120, for example. The method for forming the second metal layer M2 is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithographic etching process. For example, a second metal material layer (not shown) may be formed on the first insulating layer 120 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the second metal material layer. Then, the second metal material layer is etched by using the patterned photoresist layer as a mask to form a second metal layer M2.

第二金屬層M2可例如包括資料線DL、源極S、汲極D以及第二儲存電極130。資料線DL例如朝與第一方向D1正交的第二方向D2延伸。源極S例如與對應的資料線DL電性連接以接收相應的資料訊號。第二儲存電極130例如與第一儲存電極110以及位於第一儲存電極110與第二儲存電極130之間的第一絕緣層120形成儲存電容Cst1。儲存電容Cst1可用於儲存電壓,其儲存的電壓大小可影響液晶分子(未繪示)的偏轉狀態。The second metal layer M2 may include, for example, a data line DL, a source S, a drain D, and a second storage electrode 130. The data line DL extends, for example, in a second direction D2 orthogonal to the first direction D1. The source S is electrically connected to the corresponding data line DL, for example, to receive the corresponding data signal. The second storage electrode 130 forms, for example, a storage capacitor Cst1 with the first storage electrode 110 and the first insulating layer 120 located between the first storage electrode 110 and the second storage electrode 130. The storage capacitor Cst1 can be used to store voltage, and the stored voltage can affect the deflection state of liquid crystal molecules (not shown).

在一實施例中,畫素結構10可更包括半導體層SE。半導體層SE可例如在形成第一絕緣層120後形成。亦即,半導體層SE例如設置於第一絕緣層120上。In one embodiment, the pixel structure 10 may further include a semiconductor layer SE. The semiconductor layer SE may be formed, for example, after the first insulating layer 120 is formed. That is, the semiconductor layer SE is provided on the first insulating layer 120, for example.

半導體層SE的形成方法例如是利用微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於第一絕緣層120上形成半導體材料層(未繪示)。接著,於半導體材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對半導體材料層進行蝕刻製程,以形成半導體層SE。半導體層SE的材料可例如為非晶矽,但本新型創作不以此為限。半導體層SE的材料亦可例如為多晶矽、微晶矽、單晶矽、奈米晶矽或其它具有不同晶格排列之半導體材料或金屬氧化物半導體材料。The method for forming the semiconductor layer SE is formed by, for example, a lithography process. For example, a semiconductor material layer (not shown) may be formed on the first insulating layer 120 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. Thereafter, the patterned photoresist layer is used as a mask, and an etching process is performed on the semiconductor material layer to form a semiconductor layer SE. The material of the semiconductor layer SE may be, for example, amorphous silicon, but the novel creation is not limited thereto. The material of the semiconductor layer SE may also be, for example, polycrystalline silicon, microcrystalline silicon, single crystal silicon, nanocrystalline silicon, or other semiconductor materials or metal oxide semiconductor materials having different lattice arrangements.

在本實施例中,閘極G、源極S、汲極D以及半導體層SE可構成主動元件T。半導體層SE例如可與閘極G對應地設置,且被源極S以及汲極D部分地覆蓋。未被源極S以及汲極D覆蓋的半導體層SE可作為主動元件T的通道層CH。主動元件T例如為所屬領域中具有通常知識者所周知的任一種底部閘極型薄膜電晶體。然而,本實施例雖然是以底部閘極型薄膜電晶體為例,但本新型創作不限於此。在其他實施例中,主動元件T也例如為頂部閘極型薄膜電晶體或是其它合適類型的薄膜電晶體。In this embodiment, the gate G, the source S, the drain D, and the semiconductor layer SE may constitute an active device T. The semiconductor layer SE may be provided corresponding to the gate G, for example, and partially covered with the source S and the drain D. The semiconductor layer SE not covered by the source S and the drain D can be used as the channel layer CH of the active device T. The active device T is, for example, any bottom-gate thin-film transistor known to those skilled in the art. However, although the present embodiment takes the bottom gate type thin film transistor as an example, the novel creation is not limited to this. In other embodiments, the active device T is, for example, a top-gate thin film transistor or other suitable thin film transistors.

第二絕緣層140例如設置於第一絕緣層120上且覆蓋第二金屬層M2。亦即,第二絕緣層140可覆蓋資料線DL、源極S、汲極D以及第二儲存電極130。第二絕緣層140的形成方法例如是利用物理氣相沉積法或化學氣相沉積法而形成。在本實施例中,第二絕緣層140的材料可為無機材料(例如:氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層)、有機材料(例如:聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂)或上述之組合,但本新型創作不限於此。第二絕緣層140可為單層結構,但本新型創作不限於此。在其他實施例中,第二絕緣層140也可為多層結構。The second insulating layer 140 is disposed on, for example, the first insulating layer 120 and covers the second metal layer M2. That is, the second insulating layer 140 may cover the data line DL, the source S, the drain D, and the second storage electrode 130. The method for forming the second insulating layer 140 is, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the second insulating layer 140 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The second insulating layer 140 may have a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the second insulating layer 140 may have a multilayer structure.

遮蔽電極ME例如設置於第二絕緣層140上。遮蔽電極ME的形成方法例如是利用物理氣相沉積法或金屬化學氣相沉積法後再進行微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於第二絕緣層140上形成遮蔽金屬材料層(未繪示)。接著,於遮蔽金屬材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對遮蔽金屬材料層進行蝕刻製程,以形成遮蔽電極ME。The shielding electrode ME is provided on, for example, the second insulating layer 140. The shielding electrode ME is formed by, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a physical metal deposition method or a metal chemical vapor deposition method may be first used to form a shielding metal material layer (not shown) on the second insulating layer 140. Next, a patterned photoresist layer (not shown) is formed on the shielding metal material layer. After that, using the patterned photoresist layer as a mask, an etching process is performed on the shielding metal material layer to form a shielding electrode ME.

遮蔽電極ME可電性連接於另一共用電極線(未繪示)而接收經由此共用電極線供應的共用電壓,或者遮蔽電極ME可接地。在一實施例中,遮蔽電極ME的厚度T1為0.15μm~0.6μm。在較佳的實施例中,遮蔽電極ME的厚度T1為0.2μm~0.4μm。The shielding electrode ME may be electrically connected to another common electrode line (not shown) to receive a common voltage supplied through the common electrode line, or the shielding electrode ME may be grounded. In one embodiment, the thickness T1 of the shielding electrode ME is 0.15 μm to 0.6 μm. In a preferred embodiment, the thickness T1 of the shielding electrode ME is 0.2 μm to 0.4 μm.

在本實施例中,遮蔽電極ME與掃描線SL以及資料線DL對應地設置。詳細地說,遮蔽電極ME覆蓋掃描線SL以及資料線DL。基於此,當驅動畫素結構10時,通過掃描線SL的閘極驅動信號以及通過資料線DL的源極驅動信號可因遮蔽電極ME的阻擋而不影響畫素電極E接收的電壓,使得畫素電極E可無阻礙地操控液晶分子(未繪示)的轉向,進而避免影響顯示面板(未繪示)的透光率和反射率。In this embodiment, the shielding electrode ME is provided corresponding to the scan line SL and the data line DL. In detail, the shielding electrode ME covers the scanning lines SL and the data lines DL. Based on this, when driving the pixel structure 10, the gate driving signal through the scanning line SL and the source driving signal through the data line DL can be blocked by the shielding electrode ME without affecting the voltage received by the pixel electrode E, so that the picture The element electrode E can control the turning of liquid crystal molecules (not shown) without hindrance, thereby avoiding affecting the light transmittance and reflectance of the display panel (not shown).

遮蔽電極ME與資料線DL之間具有一特定的垂直距離d p,其實質上為第二絕緣層140的厚度。在一實施例中,遮蔽電極ME與資料線DL之間的垂直距離d p為0.15μm~1μm。在本實施例中,遮蔽電極ME與資料線DL之間的垂直距離d p為0.3μm。當遮蔽電極ME與資料線DL之間的垂直距離d p越大,代表第二絕緣層140的厚度越厚,其使得資料線DL與掃描線SL對畫素電極PE的影響越小。 There is a specific vertical distance d p between the shielding electrode ME and the data line DL, which is substantially the thickness of the second insulating layer 140. In one embodiment, the vertical distance d p between the shielding electrode ME and the data line DL is 0.15 μm to 1 μm. In this embodiment, the vertical distance d p between the shielding electrode ME and the data line DL is 0.3 μm. When the vertical distance d p between the shielding electrode ME and the data line DL is larger, it means that the thickness of the second insulating layer 140 is thicker, which makes the data line DL and the scanning line SL have less influence on the pixel electrode PE.

此外,本實施例的遮蔽電極ME暴露出未被源極S以及汲極D覆蓋的半導體層SE(即,通道層CH)。詳細地說,遮蔽電極ME具有暴露出通道層CH的開口O,但開口O不僅暴露出通道層CH,其也暴露出部分的源極S以及汲極D,使得遮蔽電極ME與通道層CH之間具有一特定的水平距離d h,如圖1A以及圖1B所示。在一實施例中,遮蔽電極ME與通道層CH之間的水平距離d h為1μm~10μm。在較佳的實施例中,遮蔽電極ME與通道層CH之間的水平距離d h為1.5μm~3μm。在遮蔽電極ME與通道層CH之間具有一特定的水平距離d h的情況下,其使得主動元件T不因遮蔽電極ME的設置而產生電性偏移的可能。 In addition, the shielding electrode ME of this embodiment exposes the semiconductor layer SE (ie, the channel layer CH) that is not covered by the source S and the drain D. In detail, the shielding electrode ME has an opening O exposing the channel layer CH, but the opening O not only exposes the channel layer CH, but also exposes part of the source S and the drain D, so that the shielding electrode ME and the channel layer CH There is a specific horizontal distance d h between them , as shown in FIG. 1A and FIG. 1B. In one embodiment, the horizontal distance d h between the shielding electrode ME and the channel layer CH is 1 μm to 10 μm. In a preferred embodiment, the horizontal distance d h between the shielding electrode ME and the channel layer CH is 1.5 μm to 3 μm. In the case where there is a specific horizontal distance d h between the shielding electrode ME and the channel layer CH, it prevents the active element T from being electrically displaced due to the setting of the shielding electrode ME.

第三絕緣層150例如設置於第二絕緣層140上且覆蓋遮蔽電極ME。第三絕緣層150的形成方法例如是利用物理氣相沉積法或化學氣相沉積法而形成。在本實施例中,第三絕緣層150的材料可為無機材料(例如:氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層)、有機材料(例如:聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂)或上述之組合,但本新型創作不限於此。第三絕緣層150可為單層結構,但本新型創作不限於此。在其他實施例中,第三絕緣層150也可為多層結構。The third insulating layer 150 is disposed on the second insulating layer 140 and covers the shielding electrode ME, for example. The third insulating layer 150 is formed by, for example, a physical vapor deposition method or a chemical vapor deposition method. In this embodiment, the material of the third insulating layer 150 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material (for example, polyimide) Resin, epoxy resin, or acrylic resin) or a combination of the above, but the novel creation is not limited to this. The third insulating layer 150 may be a single-layer structure, but the novel creation is not limited thereto. In other embodiments, the third insulating layer 150 may have a multilayer structure.

畫素電極PE例如設置於第三絕緣層150上。畫素電極PE的形成方法例如是利用物理氣相沉積法或金屬化學氣相沉積法後再進行微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於第三絕緣層150上形成畫素電極材料層(未繪示)。接著,於畫素電極材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對畫素電極材料層進行蝕刻製程,以形成畫素電極PE。畫素電極PE的材料可例如是金屬氧化物導電材料(例如:銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鍺鋅氧化物)。在一實施例中,畫素電極PE藉由貫穿第二絕緣層140與第三絕緣層150的接觸窗H與第二金屬層M2電性連接。詳細地說,畫素電極PE例如與主動元件T的汲極D電性連接。The pixel electrode PE is provided on the third insulating layer 150, for example. The pixel electrode PE is formed by, for example, a physical vapor deposition method or a metal chemical vapor deposition method followed by a lithographic etching process. For example, a pixel electrode material layer (not shown) may be formed on the third insulating layer 150 by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. After that, the patterned photoresist layer is used as a mask to perform an etching process on the pixel electrode material layer to form a pixel electrode PE. The material of the pixel electrode PE may be, for example, a metal oxide conductive material (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In one embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through a contact window H penetrating the second insulating layer 140 and the third insulating layer 150. In detail, the pixel electrode PE is electrically connected to the drain electrode D of the active device T, for example.

反射電極RE例如設置於畫素電極PE上。反射電極RE的形成方法例如是利用物理氣相沉積法或金屬化學氣相沉積法後再進行微影蝕刻製程而形成。舉例來說,可先利用物理氣相沉積法或金屬化學氣相沉積法於畫素電極PE上形成反射電極材料層(未繪示)。接著,於反射電極材料層上形成圖案化光阻層(未繪示)。之後,以圖案化光阻層為罩幕,對反射電極材料層進行蝕刻製程,以形成反射電極RE。The reflective electrode RE is provided on the pixel electrode PE, for example. The method for forming the reflective electrode RE is, for example, using a physical vapor deposition method or a metal chemical vapor deposition method followed by a lithographic etching process. For example, a reflective electrode material layer (not shown) may be formed on the pixel electrode PE first by using a physical vapor deposition method or a metal chemical vapor deposition method. Next, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. Then, the patterned photoresist layer is used as a mask, and an etching process is performed on the reflective electrode material layer to form a reflective electrode RE.

反射電極RE可例如選用反射率≥90%的金屬材料來形成。在本實施例中,反射電極RE的材料為鋁、銀或其合金,但本新型創作不限於此。The reflective electrode RE can be formed by using, for example, a metal material having a reflectivity ≧ 90%. In this embodiment, the material of the reflective electrode RE is aluminum, silver, or an alloy thereof, but the novel creation is not limited thereto.

在一實施例中,畫素結構10包括反射區RR以及穿透區TR。反射區RR例如位於穿透區TR的一側。反射電極RE例如設置於反射區RR中以反射外界的環境光或背光源發出的光。於穿透區TR中例如僅設置有絕緣層或透明電極(未繪示)因此可允許外界的環境光或背光源通過。總的來說,反射電極RE的設置位置可定義出反射區RR以及穿透區TR。In one embodiment, the pixel structure 10 includes a reflection region RR and a transmission region TR. The reflection region RR is, for example, located on one side of the transmission region TR. The reflective electrode RE is, for example, provided in the reflective region RR to reflect external ambient light or light emitted from a backlight source. For example, only an insulating layer or a transparent electrode (not shown) is provided in the transmissive region TR, and thus ambient light or a backlight source can be allowed to pass through. In general, the location of the reflective electrode RE can define a reflective region RR and a transmission region TR.

在本實施例中,畫素結構包括設置於畫素電極與基板之間的遮蔽電極,且遮蔽電極覆蓋掃描線以及資料線,藉由此布局設計可使掃描線以及資料線的訊號不影響位於其上方的畫素電極,使得畫素電極可無阻礙地操控液晶分子的轉向,藉此改善本實施例的畫素結構於驅動時造成透光率下降的問題。In this embodiment, the pixel structure includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers the scanning line and the data line. With this layout design, the signals of the scanning line and the data line do not affect the location of the signals. The pixel electrode above the pixel electrode can control the turning of the liquid crystal molecules without hindrance, thereby improving the problem that the pixel structure of this embodiment causes a decrease in light transmittance during driving.

此外,本實施例的遮蔽電極與通道層之間具有一特定的水平距離,其可避免影響主動元件的電性。In addition, there is a specific horizontal distance between the shielding electrode and the channel layer in this embodiment, which can avoid affecting the electrical properties of the active device.

圖2A為本新型創作的第二實施例的畫素結構的俯視示意圖。圖2B為圖2A中的剖線A2-A2’的剖面示意圖。在此必須說明的是,圖2A以及圖2B繪示的實施例各自沿用圖1A以及圖1B的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例描述與效果,下述實施例不再重複贅述,而圖2A以及圖2B繪示的實施例中至少一部份未省略的描述可參閱後續內容。FIG. 2A is a schematic top view of a pixel structure of a second embodiment of the novel creation. Fig. 2B is a schematic cross-sectional view taken along the line A2-A2 'in Fig. 2A. It must be noted here that the embodiments shown in FIG. 2A and FIG. 2B respectively use the component numbers and parts of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar reference numerals are used to indicate the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 2A and FIG. 2B is not omitted.

請同時參照圖2A以及圖2B,在圖2A以及圖2B所繪示的實施例中,畫素結構20的遮蔽電極ME可不僅覆蓋掃描線SL以及資料線DL,其例如可僅暴露出通道層CH以及位於半導體層SE上的部分源極S以及汲極D。基於此,如圖2B所示,本實施例的遮蔽電極ME可更包括第三儲存電極160。第三儲存電極160例如與第二儲存電極130以及位於第三儲存電極160與第二儲存電極130之間的第二絕緣層140形成儲存電容Cst2。儲存電容Cst1、Cst2可用於儲存電壓,其儲存的電壓大小可影響液晶分子的偏轉狀態。Please refer to FIG. 2A and FIG. 2B at the same time. In the embodiment shown in FIG. 2A and FIG. 2B, the shielding electrode ME of the pixel structure 20 may not only cover the scan lines SL and the data lines DL, but may only expose the channel layer, for example. CH and part of the source S and the drain D on the semiconductor layer SE. Based on this, as shown in FIG. 2B, the shielding electrode ME in this embodiment may further include a third storage electrode 160. The third storage electrode 160 forms, for example, a storage capacitor Cst2 with the second storage electrode 130 and the second insulating layer 140 located between the third storage electrode 160 and the second storage electrode 130. The storage capacitors Cst1 and Cst2 can be used to store voltage, and the stored voltage can affect the deflection state of the liquid crystal molecules.

圖3A為本新型創作的第三實施例的畫素結構的俯視示意圖。圖3B為圖3A中的剖線A3-A3’的剖面示意圖。在此必須說明的是,圖3A以及圖3B繪示的實施例各自沿用圖1A以及圖1B的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例描述與效果,下述實施例不再重複贅述,而圖3A以及圖3B繪示的實施例中至少一部份未省略的描述可參閱後續內容。FIG. 3A is a schematic top view of a pixel structure of a third embodiment of the novel creation. Fig. 3B is a schematic cross-sectional view taken along the line A3-A3 'in Fig. 3A. It must be noted here that the embodiments shown in FIG. 3A and FIG. 3B respectively use the component numbers and parts of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar reference numerals are used to represent the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 3A and FIG. 3B is not omitted.

請同時參照圖3A以及圖3B,在圖3A以及圖3B所繪示的實施例中,畫素結構30的遮蔽電極ME可更覆蓋通道層CH。在無須使遮蔽電極ME與通道層CH之間具有一特定的水平距離d h的情況下,其在製程上會較易於製作。 Please refer to FIG. 3A and FIG. 3B simultaneously. In the embodiment shown in FIG. 3A and FIG. 3B, the shielding electrode ME of the pixel structure 30 may further cover the channel layer CH. Without the need to make the shielding electrode ME and the channel layer CH have a specific horizontal distance d h , it may be easier to fabricate in the manufacturing process.

圖4A為本新型創作的第四實施例的畫素結構的俯視示意圖。圖4B為圖4A中的剖線A4-A4’的剖面示意圖。在此必須說明的是,圖4A以及圖4B繪示的實施例各自沿用圖2A以及圖2B的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例描述與效果,下述實施例不再重複贅述,而圖4A以及圖4B繪示的實施例中至少一部份未省略的描述可參閱後續內容。FIG. 4A is a schematic top view of a pixel structure of a fourth embodiment of the novel creation. Fig. 4B is a schematic cross-sectional view taken along the line A4-A4 'in Fig. 4A. It must be noted here that the embodiments shown in FIG. 4A and FIG. 4B respectively follow the component numbers and parts of the embodiments of FIG. 2A and FIG. 2B, wherein the same or similar reference numerals are used to represent the same or similar components, and Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 4A and FIG. 4B is not omitted.

請同時參照圖4A以及圖4B,在圖4A以及圖4B所繪示的實施例中,畫素結構40的遮蔽電極ME可更覆蓋通道層CH且包括第三儲存電極160。在無須使遮蔽電極ME與通道層CH之間具有一特定的水平距離d h的情況下,其在製程上會較易於製作。 Please refer to FIGS. 4A and 4B simultaneously. In the embodiment shown in FIGS. 4A and 4B, the shielding electrode ME of the pixel structure 40 may further cover the channel layer CH and include a third storage electrode 160. Without the need to make the shielding electrode ME and the channel layer CH have a specific horizontal distance d h , it may be easier to fabricate in the manufacturing process.

圖5A為本新型創作的第五實施例的畫素結構的俯視示意圖。圖5B為圖5A中的剖線A5-A5’的剖面示意圖。在此必須說明的是,圖5A以及圖5B繪示的實施例各自沿用圖1A以及圖1B的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例描述與效果,下述實施例不再重複贅述,而圖5A以及圖5B繪示的實施例中至少一部份未省略的描述可參閱後續內容。FIG. 5A is a schematic top view of a pixel structure of a fifth embodiment of the novel creation. Fig. 5B is a schematic cross-sectional view taken along the line A5-A5 'in Fig. 5A. It must be noted here that the embodiments shown in FIG. 5A and FIG. 5B respectively follow the component numbers and parts of the embodiments of FIG. 1A and FIG. Explanation of the same technical content is omitted. For the description of the omitted parts, reference may be made to the description and effects of the foregoing embodiments. The following embodiments are not repeated, and at least a part of the descriptions of the embodiments shown in FIG. 5A and FIG. 5B is not omitted.

請同時參照圖5A以及圖5B,在圖5A以及圖5B所繪示的實施例中,畫素結構50中的第三絕緣層150為由有機材料製成,且具有的厚度T2例如為1μm~10μm。在較佳的實施例中,第三絕緣層150具有的厚度T2為2μm~3μm。當第三絕緣層150具有的厚度越大時,其讓資料線DL或掃描線SL與畫素電極E之間的距離增加,並透過結合遮蔽電極ME的布局設計,使得資料線DL與掃描線SL對畫素電極E的影響減至最小。Please refer to FIGS. 5A and 5B at the same time. In the embodiment shown in FIGS. 5A and 5B, the third insulating layer 150 in the pixel structure 50 is made of an organic material and has a thickness T2 of, for example, 1 μm ~ 10 μm. In a preferred embodiment, the third insulating layer 150 has a thickness T2 of 2 μm to 3 μm. When the third insulating layer 150 has a larger thickness, it increases the distance between the data line DL or the scanning line SL and the pixel electrode E, and makes the data line DL and the scanning line by combining the layout design of the shielding electrode ME. The effect of SL on the pixel electrode E is minimized.

綜上所述,本新型創作的畫素結構包括設置於畫素電極與基板之間的遮蔽電極,且遮蔽電極至少覆蓋掃描線以及資料線,藉由此布局設計可使掃描線以及資料線的訊號不影響位於其上方的畫素電極,使得畫素電極可無阻礙地操控液晶分子的轉向,藉此改善畫素結構於驅動時造成透光率和反射率下降的問題。In summary, the pixel structure of the novel creation includes a shielding electrode disposed between the pixel electrode and the substrate, and the shielding electrode covers at least the scanning line and the data line. This layout design can make the scanning line and the data line The signal does not affect the pixel electrode located above it, so that the pixel electrode can control the turning of the liquid crystal molecules without hindrance, thereby improving the problem that the light transmittance and reflectance of the pixel structure are reduced during driving.

雖然本新型創作已以實施例揭露如上,然其並非用以限定本新型創作,任何所屬技術領域中具有通常知識者,在不脫離本新型創作的精神和範圍內,當可作些許的更動與潤飾,故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although this new type of creation has been disclosed as above by way of example, it is not intended to limit the new type of creation. Any person with ordinary knowledge in the technical field can make some changes without departing from the spirit and scope of this new type of creation Retouching, so the protection scope of this new type of creation shall be determined by the scope of the attached patent application.

10、20、30、40、50‧‧‧畫素結構
100‧‧‧基板
110‧‧‧第一儲存電極
120‧‧‧第一絕緣層
130‧‧‧第二儲存電極
140‧‧‧第二絕緣層
150‧‧‧第三絕緣層
160‧‧‧第三儲存電極
A1-A1’、A2-A2’、A3-A3’、A4-A4’、A5-A5’‧‧‧剖線
CH‧‧‧通道層
Cst1、Cst2‧‧‧儲存電容
CVL‧‧‧共用電極線
D‧‧‧汲極
dh‧‧‧水平距離
dp‧‧‧垂直距離
DL‧‧‧資料線
D1‧‧‧第一方向
D2‧‧‧第二方向
G‧‧‧閘極
H‧‧‧接觸窗
ME‧‧‧遮蔽電極
M1‧‧‧第一金屬層
M2‧‧‧第二金屬層
O‧‧‧開口
PE‧‧‧畫素電極
RE‧‧‧反射電極
RR‧‧‧反射區
S‧‧‧源極
SE‧‧‧半導體層
SL‧‧‧掃描線
T‧‧‧主動元件
T1、T2‧‧‧厚度
TR‧‧‧穿透區
10, 20, 30, 40, 50‧‧‧ pixel structure
100‧‧‧ substrate
110‧‧‧first storage electrode
120‧‧‧The first insulation layer
130‧‧‧Second storage electrode
140‧‧‧Second insulation layer
150‧‧‧third insulating layer
160‧‧‧Third storage electrode
A1-A1 ', A2-A2', A3-A3 ', A4-A4', A5-A5'‧‧‧
CH‧‧‧ Channel layer
Cst1, Cst2‧‧‧ storage capacitors
CVL‧‧‧Common electrode wire
D‧‧‧ Drain
d h ‧‧‧horizontal distance
d p ‧‧‧ vertical distance
DL‧‧‧Data Line
D1‧‧‧ first direction
D2‧‧‧ Second direction
G‧‧‧Gate
H‧‧‧Contact window
ME‧‧‧shielding electrode
M1‧‧‧First metal layer
M2‧‧‧Second metal layer
O‧‧‧ opening
PE‧‧‧Pixel electrode
RE‧‧‧Reflective electrode
RR‧‧‧Reflected area
S‧‧‧Source
SE‧‧‧Semiconductor Layer
SL‧‧‧scan line
T‧‧‧active element
T1, T2‧‧‧thickness
TR‧‧‧ Penetration zone

圖1A為本新型創作的第一實施例的畫素結構的俯視示意圖。
圖1B為圖1A中的剖線A1-A1’的剖面示意圖。
圖1C為本新型創作的一實施例的畫素結構的穿透區與反射區的示意圖。
圖2A為本新型創作的第二實施例的畫素結構的俯視示意圖。
圖2B為圖2A中的剖線A2-A2’的剖面示意圖。
圖3A為本新型創作的第三實施例的畫素結構的俯視示意圖。
圖3B為圖3A中的剖線A3-A3’的剖面示意圖。
圖4A為本新型創作的第四實施例的畫素結構的俯視示意圖。
圖4B為圖4A中的剖線A4-A4’的剖面示意圖。
圖5A為本新型創作的第五實施例的畫素結構的俯視示意圖。
圖5B為圖5A中的剖線A5-A5’的剖面示意圖。
FIG. 1A is a schematic top view of a pixel structure of a first embodiment of the novel creation.
FIG. 1B is a schematic cross-sectional view of the section line A1-A1 'in FIG. 1A.
FIG. 1C is a schematic diagram of a penetrating region and a reflecting region of a pixel structure according to an embodiment of the novel creation.
FIG. 2A is a schematic top view of a pixel structure of a second embodiment of the novel creation.
FIG. 2B is a schematic cross-sectional view taken along a section line A2-A2 'in FIG. 2A.
FIG. 3A is a schematic top view of a pixel structure of a third embodiment of the novel creation.
FIG. 3B is a schematic cross-sectional view taken along a section line A3-A3 'in FIG. 3A.
FIG. 4A is a schematic top view of a pixel structure of a fourth embodiment of the novel creation.
FIG. 4B is a schematic cross-sectional view taken along section line A4-A4 'in FIG. 4A.
FIG. 5A is a schematic top view of a pixel structure of a fifth embodiment of the novel creation.
FIG. 5B is a schematic cross-sectional view taken along section line A5-A5 'in FIG. 5A.

Claims (10)

一種畫素結構,包括:
基板;
掃描線與資料線,設置於所述基板上,其中所述掃描線沿第一方向延伸,且所述資料線沿第二方向延伸;
主動元件,與對應的所述掃描線以及對應的所述資料線電性連接;
畫素電極,與所述主動元件電性連接;
反射電極,設置於所述畫素電極上,且與所述畫素電極電性連接;以及
遮蔽電極,設置於所述畫素電極與所述基板之間,其中所述遮蔽電極至少覆蓋所述掃描線以及所述資料線。
A pixel structure, including:
Substrate
Scanning lines and data lines are provided on the substrate, wherein the scanning lines extend along the first direction, and the data lines extend along the second direction;
An active element electrically connected to the corresponding scanning line and the corresponding data line;
The pixel electrode is electrically connected to the active element;
A reflective electrode is provided on the pixel electrode and is electrically connected to the pixel electrode; and a shielding electrode is provided between the pixel electrode and the substrate, wherein the shielding electrode covers at least the The scanning line and the data line.
如申請專利範圍第1項所述的畫素結構,其中所述主動元件包括閘極、源極、汲極以及半導體層,所述閘極與所述掃描線為同一層金屬層,所述源極以及所述汲極與所述資料線為同一層金屬層,所述源極與所述資料線電性連接,所述汲極與所述畫素電極電性連接,且所述源極以及所述汲極部分覆蓋所述半導體層。The pixel structure as described in item 1 of the patent application scope, wherein the active element includes a gate electrode, a source electrode, a drain electrode and a semiconductor layer, the gate electrode and the scan line are the same metal layer, and the source The drain electrode and the drain electrode are the same metal layer as the data line, the source electrode is electrically connected to the data line, the drain electrode is electrically connected to the pixel electrode, and the source electrode and The drain part partially covers the semiconductor layer. 如申請專利範圍第1項所述的畫素結構,其更包括朝所述第一方向延伸的共用電極線,且所述共用電極線與所述掃描線為同一層金屬層。The pixel structure as described in item 1 of the patent application scope further includes a common electrode line extending toward the first direction, and the common electrode line and the scan line are the same metal layer. 如申請專利範圍第2項所述的畫素結構,其中所述遮蔽電極暴露出未被所述源極以及所述汲極覆蓋的所述半導體層。The pixel structure as described in item 2 of the patent application scope, wherein the shielding electrode exposes the semiconductor layer not covered by the source electrode and the drain electrode. 如申請專利範圍第4項所述的畫素結構,其中所述遮蔽電極與未被所述源極以及所述汲極覆蓋的所述半導體層的水平距離為1μm~10μm。The pixel structure as described in item 4 of the patent application range, wherein the horizontal distance between the shielding electrode and the semiconductor layer not covered by the source electrode and the drain electrode is 1 μm to 10 μm. 如申請專利範圍第1項所述的畫素結構,其中所述遮蔽電極覆蓋所述主動元件。The pixel structure as described in item 1 of the patent application scope, wherein the shielding electrode covers the active element. 如申請專利範圍第1項所述的畫素結構,其中所述資料線與所述遮蔽電極之間的垂直距離為0.15μm~1μm。The pixel structure as described in item 1 of the patent application, wherein the vertical distance between the data line and the shielding electrode is 0.15 μm to 1 μm. 如申請專利範圍第1項所述的畫素結構,其中所述遮蔽電極的厚度為0.15μm~0.6μm。The pixel structure as described in Item 1 of the patent application, wherein the thickness of the shielding electrode is 0.15 μm to 0.6 μm. 如申請專利範圍第1項所述的畫素結構,其中所述畫素電極與所述遮蔽電極之間設置有絕緣層,所述絕緣層覆蓋所述遮蔽電極。The pixel structure as described in item 1 of the patent application scope, wherein an insulating layer is provided between the pixel electrode and the shielding electrode, and the insulating layer covers the shielding electrode. 如申請專利範圍第9項所述的畫素結構,其中所述絕緣層的厚度為1μm~10μm。The pixel structure as described in item 9 of the patent application range, wherein the thickness of the insulating layer is 1 μm to 10 μm.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI715064B (en) * 2019-06-14 2021-01-01 凌巨科技股份有限公司 Pixel structure

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