TWM587817U - Wafer bonding film - Google Patents

Abstract

This creation is a wafer bonding film, which includes a wafer dicing carrier layer, an intermediate bonding layer, and a wafer bonding layer. The intermediate bonding layer is attached to the wafer dicing carrier layer, and the wafer is placed on the wafer bonding layer. The wafer bonding layer has excellent adhesion to the wafer, especially the wafer cutting carrier layer after UV light irradiation will reduce the viscosity or lose the adhesion to the intermediate bonding layer, so the wafer can be placed relatively firmly on the wafer bonding layer At the same time, the intermediate bonding layer can be easily separated from the wafer dicing carrier layer, which facilitates the subsequent semiconductor packaging processing process, which greatly improves the overall processing efficiency and product yield.

Description

Wafer bonding film

This creation relates to a wafer bonding film, in particular, a double-layer structure is formed by using an intermediate bonding layer and a wafer bonding layer, and the intermediate bonding layer located below the double-layer structure is attached to the wafer cutting bearing layer, and The wafer bonding layer above the double-layer structure is used to place the wafer, and the wafer bonding layer has excellent adhesion to the wafer, and the wafer cutting carrier layer after ultraviolet light irradiation will reduce the viscosity or lose the adhesion to the intermediate bonding layer. Therefore, the wafer can be fairly firmly placed on the wafer bonding layer, and at the same time, the intermediate bonding layer can be easily separated from the wafer cutting carrier layer, which facilitates the subsequent semiconductor packaging processing process and greatly improves the overall processing efficiency and product yield.

In the semiconductor manufacturing process, the wafer after multiple lithographic etching processes already contains multiple dies, and each die contains electrical circuits. Appropriate cutting processing is required to separate individual dies for subsequent wire bonding, Packaging process to form a commercially available integrated circuit (IC).

In order to cut the wafer to separate individual dies, the wafer needs to be fixed on a specific carrier film, and conventional technologies often use a die attach file (DAF) as the required carrier film. Specifically, the upper surface of the die attach film is used to place a wafer, and the lower surface of the die attach film is used to attach to a wafer cutting carrier layer, wherein the upper surface of the die attach film faces The wafer is quite sticky to stabilize the wafer and avoid movement, and the wafer cutting carrier layer will lose the stickiness to the lower surface of the die attach film after being irradiated with ultraviolet light, so they can be easily separated from each other.

In short, the die attach film must have strong adhesion to the wafer and low adhesion to the wafer dicing carrier layer.

In conventional technology, generally, the upper and lower interfaces of the die attach film are adjusted to a moderate degree of attach property, and then a siloxane coupling agent is added to improve the affinity to the wafer surface. However, the conventional technique has the disadvantage that it cannot maintain the low viscosity of the wafer dicing carrier layer at the same time. Therefore, there is a great need for an innovative wafer bonding film to improve the overall wafer processing efficiency and product yield, so as to solve all the problems of the conventional technology.

The main purpose of this creation is to provide a wafer bonding film, which includes a wafer cutting carrier layer, an intermediate bonding layer, and a wafer bonding layer that are electrically insulating and are stacked sequentially from bottom to top, and the thickness of the intermediate bonding layer is greater than Or equal to the thickness of the wafer bonding layer, which can be used to bond and carry the bonded wafer and facilitate subsequent processing of the wafer.

Specifically, the wafer dicing carrier layer is electrically insulating, has an upper surface and a lower surface, and includes a first resin material, a photoinitiator, and a fluorine-modified acrylic resin. The fluorine-modified acrylic resin is cut on the wafer. The weight percentage in the bearing layer is 1 to 5%, and the first resin material includes an acrylic resin.

The intermediate bonding layer is electrically insulating and has an upper surface and a lower surface. The lower surface of the intermediate bonding layer is attached to the upper surface of the wafer dicing carrier layer. In particular, the upper surface of the wafer dicing carrier layer faces the intermediate bonding layer. The lower surface is sticky. In addition, the intermediate bonding layer includes a second resin material, a polycyclic resin, an inorganic material, and an intermediate bonding layer hardener. The second resin material includes at least one of an epoxy resin and an acrylic resin, and the polycyclic resin includes a fluorene ring resin. And at least one of the naphthalene ring resin, and the weight percentage of the inorganic material in the intermediate bonding layer is 50 to 80%.

The wafer bonding layer is electrically insulating and has an upper surface and a lower surface. The lower surface of the wafer bonding layer is attached to the upper surface of the intermediate bonding layer, and the upper surface of the wafer bonding layer is adhesive to the wafer. For attaching and placing wafers. In addition, the wafer bonding layer includes a third resin material and a wafer bonding hardener, wherein the third resin material includes at least one of an epoxy resin and an acrylic resin.

Furthermore, the photoinitiator of the wafer dicing carrier layer causes the wafer dicing carrier layer to react when irradiated with ultraviolet light, and after the reaction, the upper surface of the wafer dicing carrier layer loses adhesion to the lower surface of the intermediate bonding layer. Sexually separated from each other.

Therefore, this creation uses the intermediate bonding layer and the wafer bonding layer to form a double-layer structure, and the intermediate bonding layer located below the double-layer structure is attached to the wafer dicing carrier layer, and the wafer bonding layer is located above the double-layer structure. When placing a wafer, in particular, the wafer bonding layer has excellent adhesiveness to the wafer, and the wafer dicing carrier layer after ultraviolet light irradiation may reduce or lose adhesion to the intermediate bonding layer. It is obvious that the wafer can be fairly firmly placed on the wafer bonding layer. At the same time, the intermediate bonding layer can be easily separated from the wafer cutting carrier layer, which facilitates the subsequent semiconductor packaging processing process and greatly improves the overall processing efficiency and product. Yield.

The following is a more detailed description of the implementation of this creation with illustrations and component symbols, so that those skilled in the art can implement it after studying this manual.

Please refer to the first figure, which is a schematic diagram of a wafer bonding film of this creative embodiment. As shown in the first figure, the wafer bonding film of this creation includes a wafer dicing carrier layer 10, an intermediate bonding layer 20, and a wafer bonding layer 30 which are electrically insulating and are sequentially stacked from bottom to top, which can be used for bonding, Carries a bonded wafer (Wafer) 40 to facilitate subsequent dicing and packaging processes.

Specifically, the wafer dicing carrier layer 10 has an upper surface and a lower surface, and includes a first resin material, a light initiator, and a fluorine-modified acrylic resin. The first resin material includes an acrylic resin, and the fluorine-modified acrylic resin. The weight percentage of the resin in the entire wafer dicing carrier layer is 1 to 5%.

In addition, the intermediate bonding layer 20 has an upper surface and a lower surface, and includes a second resin material, a polycyclic resin, an inorganic material, and an intermediate bonding layer hardener. The lower surface of the intermediate bonding layer 20 is attached to the upper surface of the wafer dicing carrier layer 10, and the upper surface of the wafer dicing carrier layer 10 is adhesive to the lower surface of the intermediate bonding layer 20. Further, the second resin material includes at least one of an epoxy resin and an acrylic resin, and the polycyclic resin may include at least one of a fluorene ring resin and a naphthalene ring resin, and the inorganic material may include silicon dioxide (SiO ₂ ). The weight percentage in the intermediate bonding layer 20 is 50 to 80%.

The thickness of the intermediate bonding layer 20 is specifically designed to be greater than or equal to the thickness of the wafer bonding layer 30, and the glass transition temperature (Tg) of the intermediate bonding layer 20 is between 120 ° C and 220 ° C. In addition, the thermal expansion coefficient of the intermediate bonding layer 20 is between 20 and 50 ppm / K when the glass transition temperature is below, and the thermal expansion coefficient of the intermediate bonding layer 20 is between 120 and 250 ppm / K when the glass transition temperature is above.

Furthermore, the wafer bonding layer 30 has an upper surface and a lower surface, and includes a third resin material and a wafer bonding hardener. The lower surface of the wafer bonding layer 30 is attached to the upper surface of the intermediate bonding layer 20, and the upper surface of the wafer bonding layer 30 is adhesive to the wafer 40 and is used to attach and place the wafer 40. Further, the third resin material includes at least one of an epoxy resin and an acrylic resin.

More specifically, the photo-initiator of the wafer dicing carrier layer 10 can cause the wafer dicing carrier layer 10 to generate a specific reaction when irradiated with ultraviolet light (UV), and after the reaction, the wafer dicing carrier layer 10 can react. The upper surface of 10 loses the adhesiveness to the lower surface of the intermediate bonding layer 20 and becomes detached from each other. In particular, the fluorine-modified acrylic resin can be used to change the surface characteristics of the wafer dicing carrier layer 10 after a specific reaction, such as increasing the surface tension, so that it can be easily separated from the intermediate bonding layer 20.

The purpose of the creator of the wafer bonding film is to firmly bond and place the wafer 40 to facilitate subsequent dicing of the wafer 40 to form multiple dies or chips. The layer 10 is easily separated from the intermediate bonding layer 20 after being irradiated with ultraviolet light. Therefore, the water vapor transmission rate of the intermediate bonding layer 20 is specifically designed to be lower than 10-15 g / m2 * day, and the wafer bonding layer 30 Water vapor transmission rate is below 10-15g / m2 * day. In addition, in order to achieve proper mechanical strength, the thickness of the wafer dicing carrier layer 10 is specifically designed to be between 20 and 50 μm, and the thickness of the wafer bonding layer 30 and the thickness of the intermediate bonding layer 20 are totaled between 5 to 80 μm .

In order to further explain the characteristics of the original wafer bonding film more clearly, please refer to the second to sixth figures, the application schematic diagram of the original wafer bonding film, and taking wafer dicing as an example.

First, the wafer 40 is attached to the adhesive wafer bonding layer 30 in the original wafer bonding film, so it is fixed, and further, the ring frame 50 is pressed on the wafer bonding layer 30 and close to the wafer 40. Around. Then, the wafer 40 is cut by the wafer cutting tool 60 to form a plurality of cutting lanes C, such as using an optical laser or a mechanical cutting knife.

Then, the wafer dicing carrier layer 10 is irradiated with ultraviolet light L, such as irradiating from the bottom to the top, so that the wafer dicing carrier layer 10 reacts to greatly reduce the adhesiveness to the intermediate bonding layer 20, or even lose the adhesiveness. Next, the wafer gripper 70, such as a suction cup, is used to take out the individual crystal grains 41 separated by the dicing path C from the bottom to the top one by one. To improve the extraction efficiency of the crystal grains 41, A die pusher 71 is used to push the die 41 toward the lower surface of the wafer dicing carrier layer 10 from the bottom up.

In addition, the above-mentioned die 41 can be placed on the wafer carrier 80 and attached to the wafer carrier 80 by the intermediate bonding layer 20. That is, the wafer bonding layer 30 is sandwiched between the intermediate bonding layer 20 and the wafer carrier. Alternatively, the plurality of dies 41 described above may be stacked into a multilayer structure between the boards 80, as shown in FIG. 6, and then the multilayer structure is placed on the wafer carrier board 80. At this time, the die 41 has been placed on the wafer carrier board 80, and the required wire bonding and packaging processes can be performed to complete the electrical connection and protect the die 41 from the external environment.

In summary, the characteristics of this creation are that a double-layer structure is formed by using an intermediate bonding layer and a wafer bonding layer, and the intermediate bonding layer located below the double-layer structure is attached to the wafer cutting bearing layer, and the double-layer structure The wafer bonding layer on the top is used to place the wafer. In particular, the wafer bonding layer has excellent adhesion to the wafer, and the wafer cutting carrier layer after ultraviolet light irradiation will reduce the viscosity or lose the adhesion to the intermediate bonding layer. Therefore, the wafer can be fairly firmly placed on the wafer bonding layer, and at the same time, the intermediate bonding layer can be easily separated from the wafer cutting carrier layer, which facilitates subsequent semiconductor packaging processing processes.

The above are only for explaining the preferred embodiment of the creation, and are not intended to restrict the creation in any form. Therefore, any modification or change related to the creation under the same spirit of creation , Should still be included in the scope of protection of this creative intention.

10‧‧‧ Wafer dicing carrier
20‧‧‧ intermediate bonding layer
30‧‧‧ Wafer Bonding Layer
40‧‧‧ wafer
41‧‧‧ Grain
50‧‧‧ ring frame
60‧‧‧ Wafer Cutting Tool
70‧‧‧ Wafer gripper
71‧‧‧ Wafer Pusher
80‧‧‧ Wafer Carrier Board
C‧‧‧cut road
L‧‧‧ UV

The first figure shows a schematic diagram of a wafer bonding film according to this creative embodiment.
The second to sixth figures show application diagrams of the original wafer bonding film.

Claims (5)

A wafer bonding film includes:
A wafer cutting carrier layer is electrically insulating, has an upper surface and a lower surface, and includes a first resin material, a photoinitiator, and a fluorine-modified acrylic resin. The fluorine-modified acrylic resin is in the crystal. The weight percentage in the circular cutting bearing layer is 1 to 5%, and the first resin material includes an acrylic resin;
An intermediate bonding layer is electrically insulating and has an upper surface and a lower surface, and the lower surface of the intermediate bonding layer is attached to the upper surface of the wafer dicing carrier layer, and the upper surface of the wafer dicing carrier layer It has adhesiveness to the lower surface of the intermediate bonding layer. The intermediate bonding layer includes a second resin material, a polycyclic resin, an inorganic material, and an intermediate bonding layer hardener. The second resin material includes epoxy resin and acrylic acid. At least one of resins, the polycyclic resin comprising at least one of a fluorene ring resin and a naphthalene ring resin, the weight percentage of the inorganic material in the intermediate bonding layer is 50 to 80%; and a wafer bonding layer, For electrical insulation, there is an upper surface and a lower surface, the lower surface of the wafer bonding layer is attached to the upper surface of the intermediate bonding layer, and the upper surface of the wafer bonding layer is adhesive to a wafer. The wafer is attached for placement, and the wafer bonding layer includes a third resin material and a wafer bonding hardener. The third resin material includes at least one of epoxy resin and acrylic resin. ,
Wherein, a thickness of the intermediate bonding layer is greater than or equal to a thickness of the wafer bonding layer, and the photo-initiator of the wafer dicing carrier layer causes the wafer dicing carrier layer to generate a reaction when irradiating ultraviolet light, and After the reaction, the upper surface of the wafer dicing carrier layer loses the adhesiveness to the lower surface of the intermediate bonding layer and becomes detached from each other. The wafer bonding film according to item 1 of the scope of patent application, wherein a glass transition temperature (Tg) of the intermediate bonding layer is between 120 ° C and 220 ° C. The wafer bonding film according to item 2 of the patent application scope, wherein a thermal expansion coefficient of the intermediate bonding layer is between 20 and 50 ppm / K below the glass transition temperature, and a thermal expansion coefficient of the intermediate bonding layer is between Above the glass transition temperature is between 120 and 250 ppm / K, and the inorganic material includes silicon dioxide (SiO ₂ ). The wafer bonding film according to item 1 of the patent application scope, wherein a water vapor transmission rate of the wafer bonding layer is lower than 10-15 g / m2 * day, and a water vapor transmission rate of the intermediate bonding layer Below 10-15g / m2 * day. The wafer bonding film according to item 1 of the scope of the patent application, wherein the thickness of the wafer bonding layer and the thickness of the intermediate bonding layer are between 5 and 80 μm in total, and a thickness of the wafer cutting carrier layer is between Between 20 and 50 μm.