TWM582231U - Inkjet chip packaging structure - Google Patents
Inkjet chip packaging structure Download PDFInfo
- Publication number
- TWM582231U TWM582231U TW108204188U TW108204188U TWM582231U TW M582231 U TWM582231 U TW M582231U TW 108204188 U TW108204188 U TW 108204188U TW 108204188 U TW108204188 U TW 108204188U TW M582231 U TWM582231 U TW M582231U
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- Prior art keywords
- circuit board
- pads
- wafer
- inkjet
- chip package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- Wire Bonding (AREA)
Abstract
一種噴墨晶片封裝結構,包含:一電路板,係一長方形態樣,具有二長邊以及二短邊,並包含複數個電路板焊墊、複數個金屬裸露區以及一容置開口,電路板焊墊設置於容置開口之相對兩側;一噴墨晶片,容置在電路板之容置開口內,並包含複數個晶片焊墊,晶片焊墊分別與電路板焊墊的位置相對應設置;以及複數個導線,以半導體打線製程製出,每一導線兩端分別連接相對應之電路板焊墊以及相對應之晶片焊墊,使得噴墨晶片透過導線與金屬裸露區電性連接。An inkjet chip package structure comprising: a circuit board having a rectangular shape, having two long sides and two short sides, and comprising a plurality of circuit board pads, a plurality of metal bare regions, and a receiving opening, the circuit board The soldering pads are disposed on opposite sides of the receiving opening; an inkjet wafer is received in the receiving opening of the circuit board and includes a plurality of wafer pads, and the wafer pads are respectively disposed corresponding to the positions of the circuit board pads And a plurality of wires are formed by a semiconductor wire bonding process, and the opposite ends of each wire are respectively connected with corresponding circuit board pads and corresponding wafer pads, so that the inkjet wafers are electrically connected to the bare metal regions through the wires.
Description
本案係關於一種封裝結構,尤指一種噴墨晶片的封裝結構。This case relates to a package structure, especially a package structure of an inkjet wafer.
隨著科技的日新月異,在噴墨晶片封裝時,傳統的捲帶式自動接合技術(Tape Auto-mated Bonding, TAB)在應用時有許多需要克服的地方。如第1圖至第2B圖所示,傳統的噴墨晶片封裝結構1包含一捲帶11、一噴墨晶片12以及複數個導線13。捲帶11上設置有複數個金屬裸露區11a。噴墨晶片12上設置有複數個晶片焊墊12a。導線13兩端分別連接噴墨晶片12的晶片焊墊12a以及捲帶11,使噴墨晶片12透過導線13與捲帶11的金屬裸露區11a電性連接。在執行捲帶式自動接合時,若有定位偏移發生,導線13若與鄰近之晶片焊墊12a電性連接,會產生短路,增加產品不良率。With the rapid development of technology, the traditional Tape Auto-mated Bonding (TAB) has many problems to overcome when applying inkjet chip packaging. As shown in FIGS. 1 to 2B, the conventional ink-jet chip package structure 1 includes a tape 11, an ink-jet wafer 12, and a plurality of wires 13. The tape 11 is provided with a plurality of metal bare regions 11a. A plurality of wafer pads 12a are disposed on the inkjet wafer 12. The two ends of the wire 13 are respectively connected to the wafer pad 12a of the inkjet wafer 12 and the tape 11 so that the inkjet wafer 12 is electrically connected to the metal bare region 11a of the tape 11 through the wire 13. When the tape-and-tape automatic bonding is performed, if a positioning offset occurs, the wire 13 is electrically connected to the adjacent wafer pad 12a, which causes a short circuit and increases the product defect rate.
因此,傳統的捲帶式自動接合技術逐漸被軟性印刷電路板(Flexible Printed Circuit, FPC)所取代,故如何利用創新的封裝結構使得軟性印刷電路板能順利的應用在噴墨晶片封裝上,為目前需要解決的議題。Therefore, the traditional tape and reel automatic bonding technology is gradually replaced by a Flexible Printed Circuit (FPC), so how to use the innovative package structure enables the flexible printed circuit board to be smoothly applied to the inkjet chip package. The issues that need to be addressed now.
本案之主要目的在於提供一種噴墨晶片封裝結構,利用創新的封裝結構,使得軟性印刷電路板能順利的應用在噴墨晶片封裝上,增加生產效率並減少產品不良率。The main purpose of this case is to provide an inkjet chip package structure, which utilizes an innovative package structure, so that the flexible printed circuit board can be smoothly applied to the inkjet chip package, thereby increasing production efficiency and reducing product defect rate.
為達上述目的,本案之較廣義實施態樣為提供一種噴墨晶片封裝結構,包含一電路板、一噴墨晶片以及複數個導線。電路板係一長方形態樣,具有二長邊以及二短邊,並包含複數個電路板焊墊、複數個金屬裸露區以及一容置開口。電路板焊墊設置於容置開口之相對兩側。噴墨晶片容置在電路板之容置開口內,並包含複數個晶片焊墊。晶片焊墊分別與電路板焊墊的位置相對應設置。導線以半導體打線製程製出,並且每一導線兩端分別連接相對應之電路板焊墊以及相對應之晶片焊墊,使得噴墨晶片透過導線與金屬裸露區電性連接。To achieve the above object, a broader aspect of the present invention provides an ink jet chip package structure including a circuit board, an ink jet wafer, and a plurality of wires. The circuit board has a rectangular shape with two long sides and two short sides, and includes a plurality of circuit board pads, a plurality of metal bare areas, and a receiving opening. The circuit board pads are disposed on opposite sides of the receiving opening. The inkjet wafer is housed in a receiving opening of the circuit board and includes a plurality of wafer pads. The wafer pads are respectively disposed corresponding to the positions of the circuit board pads. The wires are formed by a semiconductor wire bonding process, and the opposite ends of each wire are respectively connected with corresponding circuit board pads and corresponding wafer pads, so that the ink-jet wafers are electrically connected to the bare metal regions through the wires.
體現本案特徵與優點的實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非用以限制本案。Embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It is to be understood that the present invention is capable of various modifications in various embodiments, and is not intended to limit the scope of the invention.
請參閱第3圖至第4B圖,於本案第一實施例中,噴墨晶片封裝結構10包含一電路板2、一噴墨晶片3以及複數個導線4。電路板2係一長方型態樣,具有二長邊21以及二短邊22,並包含複數個金屬裸露區2a、複數個電路板焊墊2b以及一容置開口2c。電路板焊墊2b設置於容置開口2c對應於短邊22之相對兩側。於本案第一實施例中,電路板2為一軟性印刷電路板,但不以此為限。噴墨晶片3容置在電路板2之容置開口2c內,並包含複數個晶片焊墊3a。晶片焊墊3a分別與電路板焊墊2b的位置相對應設置,因此晶片焊墊3a亦設置於容置開口2c對應於短邊22之相對兩側。於本案第一實施例中,噴墨晶片3為一長方型態樣,但不以此為限。導線4以半導體打線製程製出,並且每一導線兩端分別連接相對應之電路板焊墊2b以及相對應之晶片焊墊3a,使得噴墨晶片3透過導線4與金屬裸露區2a電性連接。於本案第一實施例中,每一電路板焊墊2b與相對應之晶片焊墊3a透過至少兩條導線4連接,如此噴墨晶片3可實現高電壓與高電流之電性特質。每一電路板焊墊2b與相對應之晶片焊墊3a所搭配之導線4的數量可依電性需求而變更,不以此為限。Referring to FIGS. 3 to 4B, in the first embodiment of the present invention, the inkjet chip package structure 10 includes a circuit board 2, an inkjet wafer 3, and a plurality of wires 4. The circuit board 2 is a rectangular shape having two long sides 21 and two short sides 22, and includes a plurality of metal bare regions 2a, a plurality of circuit board pads 2b, and a receiving opening 2c. The circuit board pads 2b are disposed on the opposite sides of the accommodating opening 2c corresponding to the short sides 22. In the first embodiment of the present invention, the circuit board 2 is a flexible printed circuit board, but is not limited thereto. The inkjet wafer 3 is housed in the receiving opening 2c of the circuit board 2 and includes a plurality of wafer pads 3a. The wafer pads 3a are respectively disposed corresponding to the positions of the circuit board pads 2b. Therefore, the wafer pads 3a are also disposed on the opposite sides of the accommodating opening 2c corresponding to the short sides 22. In the first embodiment of the present invention, the inkjet wafer 3 is in a rectangular shape, but is not limited thereto. The wires 4 are formed by a semiconductor wire bonding process, and the corresponding circuit board pads 2b and the corresponding wafer pads 3a are respectively connected to the two ends of the wires, so that the inkjet chips 3 are electrically connected to the metal bare regions 2a through the wires 4. . In the first embodiment of the present invention, each of the circuit board pads 2b and the corresponding wafer pads 3a are connected through at least two wires 4, so that the ink-jet wafer 3 can realize the electrical characteristics of high voltage and high current. The number of the wires 4 of each of the circuit board pads 2b and the corresponding wafer pads 3a can be changed according to the electrical requirements, and is not limited thereto.
值得注意的是,電路板2中設置有複數個電路導線(未圖示),使得電路板焊墊2b以及金屬裸露區2a得以電性連接。此外,每一電路板焊墊2b下方設置有一絕緣材料(未圖示),用以提供支撐力予電路板焊墊2b,此特徵可依設計需求而變更,不以此為限。It should be noted that a plurality of circuit wires (not shown) are disposed in the circuit board 2, so that the circuit board pad 2b and the metal bare region 2a are electrically connected. In addition, an insulating material (not shown) is disposed under each of the circuit board pads 2b to provide a supporting force to the circuit board pads 2b. This feature may be changed according to design requirements, and is not limited thereto.
值得注意的是,電路板焊墊2b以及晶片焊墊3a的材質為任一導電材質。於本案第一實施例中,電路板焊墊2b以及晶片焊墊3a為金屬材質,但不以此為限。於本案第一實施例中,導線4的材質為半導體打線製程所使用之任一金屬材質,可依製程需求而變更,不以此為限。It should be noted that the material of the circuit board pad 2b and the wafer pad 3a is any conductive material. In the first embodiment of the present invention, the circuit board pad 2b and the wafer pad 3a are made of metal, but are not limited thereto. In the first embodiment of the present invention, the material of the wire 4 is any metal material used in the semiconductor wire-bonding process, and may be changed according to the process requirements, and is not limited thereto.
請參閱第5圖以及第6圖,於本案第二實施例中,噴墨晶片封裝結構10'的結構與第一實施例中的噴墨晶片封裝結構10大致相同,不同之處在於電路板焊墊2b'以及晶片焊墊3a'的設置位置。於本案第二實施例中,電路板焊墊2b'以及晶片焊墊3a'設置於容置開口2c對應於長邊21之相對兩側,並且每一電路板焊墊2b'與相對應之晶片焊墊3a'亦透過至少兩條導線4連接以實現噴墨晶片3高電壓與高電流之電性特質。Referring to FIG. 5 and FIG. 6, in the second embodiment of the present invention, the structure of the ink-jet chip package structure 10' is substantially the same as that of the ink-jet chip package structure 10 of the first embodiment, except that the board is soldered. The pad 2b' and the placement position of the wafer pad 3a'. In the second embodiment of the present invention, the circuit board pad 2b' and the wafer pad 3a' are disposed on the opposite sides of the receiving opening 2c corresponding to the long side 21, and each of the circuit board pads 2b' and the corresponding wafer The pad 3a' is also connected through at least two wires 4 to achieve the electrical characteristics of the high voltage and high current of the inkjet wafer 3.
綜上所述,本案提供一種噴墨晶片封裝結構,利用創新的封裝結構,使得軟性印刷電路板能順利的應用在噴墨晶片封裝上,增加生產效率並減少產品不良率。In summary, the present invention provides an inkjet chip package structure, which utilizes an innovative package structure to enable a flexible printed circuit board to be smoothly applied to an inkjet chip package, thereby increasing production efficiency and reducing product defect rate.
本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.
10、10'‧‧‧噴墨晶片封裝結構 2‧‧‧電路板 21‧‧‧長邊 22‧‧‧短邊 2a‧‧‧金屬裸露區 2b、2b'‧‧‧電路板焊墊 2c‧‧‧容置開口 3‧‧‧噴墨晶片 3a、3a'‧‧‧晶片焊墊 4‧‧‧導線 1‧‧‧噴墨晶片封裝結構 11‧‧‧捲帶 11a‧‧‧金屬裸露區 12‧‧‧噴墨晶片 12a‧‧‧晶片焊墊 13‧‧‧導線 10, 10'‧‧‧Inkjet chip package structure 2‧‧‧ boards 21‧‧‧Longside 22‧‧‧ Short side 2a‧‧‧Metal bare area 2b, 2b'‧‧‧ circuit board pads 2c‧‧‧ accommodating opening 3‧‧‧Inkjet wafer 3a, 3a'‧‧‧ wafer pads 4‧‧‧ wire 1‧‧‧Inkjet chip package structure 11‧‧‧ Tapes 11a‧‧‧metal exposed area 12‧‧‧Inkjet wafer 12a‧‧‧ wafer pads 13‧‧‧Wire
第1圖為先前技術中噴墨晶片封裝結構的示意圖。 第2A圖以及第2B圖為先前技術中噴墨晶片封裝結構的局部放大示意圖。 第3圖為本案第一實施例之噴墨晶片封裝結構的示意圖。 第4A圖及第4B圖為本案第一實施例之噴墨晶片封裝結構的局部放大示意圖。 第5圖為本案第二實施例之噴墨晶片封裝結構的示意圖。 第6圖為本案第二實施例之噴墨晶片封裝結構的局部放大示意圖。 Figure 1 is a schematic illustration of an ink jet chip package structure of the prior art. 2A and 2B are partial enlarged views of the prior art inkjet chip package structure. Fig. 3 is a schematic view showing the structure of the ink-jet chip package of the first embodiment of the present invention. 4A and 4B are partial enlarged views of the ink-jet chip package structure of the first embodiment of the present invention. Fig. 5 is a schematic view showing the structure of the ink-jet chip package of the second embodiment of the present invention. Figure 6 is a partially enlarged schematic view showing the structure of the ink-jet chip package of the second embodiment of the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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TW108204188U TWM582231U (en) | 2019-04-03 | 2019-04-03 | Inkjet chip packaging structure |
Applications Claiming Priority (1)
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TW108204188U TWM582231U (en) | 2019-04-03 | 2019-04-03 | Inkjet chip packaging structure |
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TWM582231U true TWM582231U (en) | 2019-08-11 |
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TW108204188U TWM582231U (en) | 2019-04-03 | 2019-04-03 | Inkjet chip packaging structure |
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2019
- 2019-04-03 TW TW108204188U patent/TWM582231U/en not_active IP Right Cessation
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