TWM468018U - Semiconductor light emittingelement with light reflecting layer - Google Patents

Description

Semiconductor light emitting device with light reflecting layer

The present invention relates to a semiconductor light emitting device, and further to a semiconductor light emitting device with a light reflecting layer.

As the luminous efficiency of semiconductor light-emitting wafers increases and the manufacturing cost decreases, semiconductor light-emitting wafers have been widely used in the fields of backlighting, display, and illumination.

The conventional semiconductor light-emitting device comprises a substrate, an n-type conductive layer, a light-emitting layer, a p-type conductive layer, an n-type electrode, a p-type electrode, a conductive line, an insulating layer and a pad, etc., an n-type conductive layer, a light-emitting layer and a p-type conductive The layers together form a semiconductor stack disposed on the substrate, and the n-type electrode and the p-type electrode are electrically connected to the n-type conductive layer and the p-type conductive layer, respectively. When the semiconductor light-emitting device emits light, in addition to the light-emitting surface, the light is emitted from other surfaces and sides of the semiconductor light-emitting device, so that the light emitted by the semiconductor light-emitting device cannot be fully utilized, which not only reduces the luminous efficiency of the semiconductor light-emitting device, but also affects the light-emitting efficiency of the semiconductor light-emitting device. The light shape of the light emitting device is not suitable for projection type light sources and devices such as requiring a small emission angle.

The technical problem to be solved by the present invention is to provide a semiconductor light-emitting device which improves luminous efficiency and light-emitting shape.

In order to solve the above technical problems, the present invention provides a semiconductor light emitting device with a light reflecting layer, comprising a substrate having a first surface and a second surface, wherein the first surface is provided with a semiconductor light emitting wafer; and the semiconductor light emitting chip has at least one The surface and/or the side are light exiting surfaces, the other surfaces and sides of the semiconductor light emitting wafer being surrounded by at least one light reflecting layer in addition to the light exiting surface.

Preferably, the light reflecting layer comprises one or more combinations of a non-metal based light reflecting layer and a metal based light reflecting layer.

Preferably, the semiconductor light-emitting chip comprises at least one semiconductor stack, the semiconductor stack comprises at least an n-type conductive layer, a light-emitting layer and a p-type conductive layer which are sequentially stacked; at least one of the semiconductor laminate is provided The n-type electrode electrically connected to the n-type conductive layer and at least one p-type electrode electrically connected to the p-type conductive layer; at least one n-type exposed to the n-type conductive layer on the surface of the p-type conductive layer The electrode is recessed, the n-type electrode is disposed in the n-type electrode recess; the semiconductor stack is disposed on the first surface of the substrate with the p-type conductive layer facing the substrate; the n-type conductive The surface of the layer facing away from the substrate is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer is coated on the surface and the side surface of the semiconductor laminate except the light-emitting surface, at least one of the p-type electrodes And at least one of the n-type electrodes exposes a surface of the light reflecting layer.

Preferably, the light-emitting surface further comprises part or all of the side surfaces of the semiconductor laminate.

Preferably, an n-type electrode interconnection layer is formed in the light reflection layer, the n-type electrode interconnection layer is electrically connected to at least one of the n-type electrodes; and/or a p is formed in the light reflection layer. a type electrode interconnection layer, the p-type electrode interconnection layer being electrically connected to at least one of the p-type electrodes; the n-type electrode interconnection layer and the p-type electrode interconnection layer being insulated from each other.

Preferably, part or all of the surface of the p-type conductive layer is provided with at least one p-type current spreading layer, at least one of the p-type electrodes is electrically connected to the p-type current spreading layer; the light reflecting layer wrapping portion And or all of the p-type current spreading layer; and/or a portion or all of the surface of the n-type conductive layer is provided with at least one n-type current spreading layer, at least one of the n-type electrode and the n-type current The expansion layer is electrically connected; the light reflection layer encapsulates part or all of the n-type current spreading layer.

Preferably, the p-type current spreading layer comprises one or more combinations of a p-type light-transmitting current spreading layer and a p-type metal-based current-expanding reflective layer; the p-type light-transmitting current spreading layer comprises ZnO, ITO, and heavy doping One or more combinations of p-type metal-based current-expanding reflective layers including one or more of a p-type metal diffusion barrier layer, a p-type conductive diffusion layer, a p-type light-reflecting layer, and a p-type contact layer Combining; the n-type current spreading layer comprises one or more combinations of an n-type light-transmitting current spreading layer and an n-type metal-based current spreading reflecting layer; the n-type light-transmitting current spreading layer comprises ZnO, ITO, and heavily doped n One or more combinations of the type of conductive layer, the n-type metal-based current spreading reflective layer comprising one or more combinations of an n-type metal diffusion barrier layer, a p-type conductive expansion layer, a p-type light reflective layer, and a p-type contact layer .

Preferably, at least one transparent insulating layer is disposed between the light reflecting layer and the p-type current spreading layer and/or the n-type current spreading layer.

Preferably, the first surface of the substrate is provided with at least one p-type pad and at least one n-type pad; the p-type pad is electrically connected to the p-type electrode exposing the light reflecting layer, The n-type pad is electrically connected to the n-type electrode exposing the light-reflecting layer; or the light-reflecting layer is provided with at least one insulating protective layer, at least one of the p-type electrodes exposing the insulating protection The layer is electrically connected to the p-type pad, and at least one of the n-type electrodes exposes the insulating protective layer to be electrically connected to the n-type pad.

In the insulating protective layer, at least one n-type electrode interconnection layer is disposed, and the n-type electrode interconnection layer is electrically connected to at least one n-type electrode under the n-type electrode interconnection layer, and at least one The n-electrode is electrically connected above the n-type electrode interconnection layer; and/or, in the insulating protection layer, at least one p-type electrode interconnection layer is provided, the p-type electrode interconnection layer and At least one p-type electrode underlying the p-type electrode interconnection layer is electrically connected to at least one of the p-electrodes located above the p-type electrode interconnection layer; the n-type electrode interconnection layer and p The type electrode interconnection layers are insulated from each other.

Preferably, the substrate is further provided with at least one p-type pad and at least one n-type pad; the p-type pad is disposed at a position including one or more of the first surface, the second surface, and the side of the substrate The p-type pad is electrically connected to the p-type pad through at least one p-type interconnect metal, and the p-type interconnect metal passes through the first surface, the second surface, the side surface of the substrate, Passing through one or more of the substrates; or, the p-type pad is a p-type pin-shaped pad electrically connected to the p-type pad through the substrate; the n-type pad is disposed The position includes one or more of the first surface, the second surface, and the side surface of the substrate; the n-type pad is electrically connected to the n-type pad through at least one n-type interconnect metal, the n-type mutual a position at which the metal passes includes one or more of the first surface, the second surface, and the side surface of the substrate; or the n-type pad passes through the substrate and the n-type solder The pad is electrically connected to the n-type pin pad.

Preferably, the n-type electrode recess includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess.

The implementation of the present invention has the following beneficial effects: the semiconductor light-emitting device of the present invention has a simple structure and is convenient to manufacture, and has a light-reflecting layer on its non-light-emitting surface to improve luminous efficiency and light-emitting shape; and can also be provided by a p-type pad, n-type The solder pad enables the semiconductor light-emitting chip to be used for reflow soldering.

11, 21, 31, 41, 51, 61, 71‧‧‧ substrates
15, 25, 35, 45, 55, 65, 75‧ ‧ light reflective layer
12, 22, 32, 42, 52, 62, 72‧‧‧ semiconductor stack
12a, 22a, 32a, 42a, 52a, 62a, 72a‧‧‧n type conductive layer
12b, 22b, 32b, 42b, 52b, 62b, 72b‧‧‧ luminescent layer
12c, 22c, 32c, 42c, 52c, 62c, 72c‧‧‧ p type conductive layer
12d, 22d, 32d, 42d, 52d, 62d, 72d‧‧‧n type electrode depression
13, 23, 33, 43, 53, 63, 73‧‧‧n type electrodes
14, 24, 34, 44, 54, 64‧‧‧p-type electrodes
33a, 73a‧‧‧first n-type electrode
33b, 73b‧‧‧ second n-type electrode
74a‧‧‧First p-type electrode
74b‧‧‧Second p-type electrode
251, 551, ‧ ‧ non-metallic based light reflecting layer
252, 552, ‧‧‧ metal-based light reflecting layer
47, 67‧‧‧Transparent insulation
26, 36, 46, 56, 66, 76‧‧ ‧ insulating protective layer
141, 241, 341, ‧‧‧p type current spreading layer
131, 231, 331, 431, 531, 631, 731‧‧‧n type current expansion layer
132, 232, 332, 432, 532, 632, 732‧‧‧n type solder pads
142, 242, 342, 442, 542, 642, 742‧‧‧p type solder pads
133, 233, 333, 433, 533, 633, 733‧‧‧n type pads
143, 243, 343, 443, 543, 643, 743 ‧ ‧ p-type pads
134, 234, 334, 434, 534, 634, 734‧‧‧n type interconnect metal
144, 244, 344, 444, 544, 644, 744‧‧‧p type interconnect metal
335, 735‧‧‧n type electrode interconnection layer
745‧‧‧p type electrode interconnection layer

The first figure is a schematic structural view of a first embodiment of a semiconductor light emitting device with a light reflecting layer;
2 is a schematic structural view of a second embodiment of a semiconductor light emitting device with a light reflecting layer;
The third figure is a schematic structural view of a third embodiment of a semiconductor light emitting device with a light reflecting layer;
The fourth figure is a schematic structural view of a fourth embodiment of the semiconductor light emitting device with a light reflecting layer;
The fifth figure is a schematic structural view of a fifth embodiment of the semiconductor light emitting device with a light reflecting layer;
6 is a schematic structural view of a sixth embodiment of a semiconductor light emitting device with a light reflecting layer;
The seventh figure is a schematic structural view of a seventh embodiment of the semiconductor light-emitting device with a light-reflecting layer.

As shown in the first figure, the semiconductor light-emitting device with a light-reflecting layer according to the first embodiment of the present invention comprises a substrate 11 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 11. The semiconductor light-emitting wafer has at least one surface and/or side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 15 except for the light-emitting surface.

The light reflecting layer 15 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 12, at least one n-type electrode 13, and at least one p-type electrode 14. The semiconductor stack 12 includes at least an n-type conductive layer 12a, a light-emitting layer 12b and a p-type conductive layer 12c which are sequentially stacked. The n-type electrode 13 is disposed on the semiconductor layer 12 and electrically connected to the n-type conductive layer 12a, p-type The electrode 14 is disposed on the semiconductor stack 12 and is electrically connected to the p-type conductive layer 12c. On the surface of the p-type conductive layer 12c, at least one n-type electrode recess 12d is formed which exposes a portion of the n-type conductive layer 12a, and the n-type electrode 13 is provided in the n-type electrode recess 12d.

The bottom surface of the n-type electrode recess 12d is located in the surface or surface of the n-type conductive layer 12a. The n-type electrode recess 12d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess. The n-type electrode groove is a long strip-shaped groove, and the opposite ends of the groove are closed or open; the n-type electrode concave hole has a circular shape, a square shape and the like. In order to minimize the reduction in the area of the light-emitting layer 12b, the area of the n-type electrode recess 12d to be formed should be as small as possible. In the present embodiment, the n-type electrode recess 12d is an n-type electrode recess, and the recess has a trapezoidal cross section.

The semiconductor laminate 12 is disposed on the first surface of the substrate 11 toward the substrate 11 with the p-type conductive layer 12c. The surface of the n-type conductive layer 12a facing away from the substrate 11 is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer 15 is wrapped on the surface and the peripheral side of the semiconductor laminate 12 except the light-emitting surface, at least one p-type electrode 14 and at least one n The type electrode 13 is exposed to the surface of the light reflecting layer 15. As an alternative embodiment, the light exiting surface may also include some or all of the sides of the semiconductor stack 12. Further, the light reflecting layer 15 may also be wrapped onto the exposed portion of the first surface of the substrate 11.

The light reflecting layer 15 includes, but is not limited to, one or more combinations of a non-metal based light reflecting layer and a metal based light reflecting layer. When the light reflecting layer 15 is a non-metal based light reflecting layer, it is not electrically conductive with the semiconductor layer 12, and the light reflecting layer 15 wraps part or all of the semiconductor layer 12 without causing a short circuit. When the light reflecting layer 15 is a metal-based light reflecting layer, it is electrically conductive with the semiconductor laminate 12, and therefore, preferably, the light reflecting layer 15 is insulated from the p-type electrode 14 and/or the n-type electrode 13 to prevent light reflection. The layer 15 is simultaneously electrically conductive with the p-type electrode 14 and the n-type electrode 13 to cause a short circuit.

In order to uniformly distribute the current to the entire semiconductor light-emitting chip and uniformly emit the light-emitting layer 12b, at least one p-type current spreading layer 141 may be provided in part or all of the surface of the p-type conductive layer 12c, and at least one p-type electrode 14 and p may be provided. The type current spreading layer 141 is electrically connected; or, at least one n-type current spreading layer 131 is provided in part or all of the surface of the n-type conductive layer 12a (ie, the surface of the n-type electrode recess 12d), at least one n-type electrode 13 and n-type The current spreading layer 131 is electrically connected; or, the p-type current spreading layer 141 and the n-type current spreading layer 131 are simultaneously disposed.

The p-type current spreading layer 141 includes one or more combinations of a p-type light-transmitting current spreading layer and a p-type metal-based current-expanding reflective layer; the p-type light-transmitting current spreading layer includes ZnO, ITO, and a heavily doped p-type conductive layer. In one or more combinations, the p-type metal-based current spreading reflective layer comprises one or more combinations of a p-type metal diffusion barrier layer, a p-type conductive expansion layer, a p-type light reflective layer, and a p-type contact layer. The material used for the p-type metal diffusion barrier layer includes, but is not limited to, one or more of a refractory metal, a refractory metal nitride, a refractory metal carbide, and a refractory metal ternary alloy, including but not limited to W, One or more of Ti, Mo, Ta, TiW; materials used for the p-type conductive expansion layer include, but are not limited to, one or more of ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO The material used for the p-type light reflecting layer includes, but is not limited to, one or more of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof; and the p-type contact layer is used. Materials include, but are not limited to, one or more of ITO, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped low resistance p-type conductive layers.

The n-type current spreading layer 131 includes one or more combinations of an n-type light-transmitting current spreading layer and an n-type metal-based current-amplifying reflecting layer; the n-type light-transmitting current spreading layer includes ZnO, ITO, and a heavily doped n-type conductive layer. In one or more combinations, the n-type metal-based current spreading reflective layer comprises one or more combinations of an n-type metal diffusion barrier layer, a p-type conductive expansion layer, a p-type light reflective layer, and a p-type contact layer. The material used for the n-type metal diffusion barrier layer includes, but is not limited to, one or more of a refractory metal, a refractory metal nitride, a refractory metal carbide, and a refractory metal ternary alloy, including but not limited to W, One or more of Ti, Mo, Ta, TiW; materials used for the n-type conductive expansion layer include, but are not limited to, one or more of ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO The material used for the n-type light reflecting layer includes, but is not limited to, one or more of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof; Materials include, but are not limited to, one or more of ITO, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped low resistance n-type conductive layers.

In this embodiment, the light reflecting layer 15 is a non-metal based light reflecting layer, and the surface of the p-type conductive layer 12c and the surface of the n-type conductive layer 12a are respectively provided with a p-type current spreading layer 141 and an n-type current spreading layer 131, at least one The p-type electrode 14 and the n-type electrode 13 are electrically connected to the p-type current spreading layer 141 and the n-type current spreading layer 131, respectively. The p-type electrode 14 is in direct contact with the p-type current conducting layer 141 and the p-type conductive layer 12c to form a conductive connection, and the n-type electrode 13 is in direct contact with the n-type current conducting layer 131 and the n-type conductive layer 12a to form a conductive connection. It can be understood that the p-type electrode 14 and the n-type electrode 13 can also be disposed on the p-type current spreading layer 141 and the n-type current spreading layer 131, respectively. The light reflecting layer 15 is directly wrapped on part or all of the p-type current spreading layer 141 and/or part or all of the n-type current spreading layer 131. It can be understood that the light reflecting layer 15 may not wrap the current spreading layer.

Further, the first surface of the substrate 11 is provided with at least one p-type pad 142 and at least one n-type pad 132, and the p-type pad 142 and the n-type pad 132 are insulated from each other. The p-type pad 142 is electrically connected to at least one p-type electrode 14 exposing the light-reflecting layer, and the n-type pad 132 is electrically connected to at least one p-type electrode 14 exposing the light-reflecting layer; or the light-reflecting layer 15 is provided with at least An insulating protective layer, at least one p-type electrode 14 is exposed to the insulating protective layer and electrically connected to the p-type pad 142, and at least one of the n-type electrodes 13 is exposed to the insulating protective layer and is electrically connected to the n-type pad 132. The p-type electrode 142 and the n-type pad 132 are electrically connected to the p-type electrode 14 and the n-type electrode 13, respectively, to fix the semiconductor light-emitting wafer on the first surface of the substrate 11. The insulating protective layer is a transparent insulating protective layer or a non-transparent insulating protective layer, and the transparent insulating protective layer can be used for materials including, but not limited to, cerium oxide, aluminum oxide, titanium oxide, glass, light-transmitting ceramic, resin, germanium. A combination of a variety of rubbers.

In this embodiment, since the light reflecting layer 15 is a non-metal based light reflecting layer, the p-type pad 142 and the n-type pad 132 can be directly in contact with the light reflecting layer 15 to electrically connect the p-type electrodes 14 and n, respectively. Type electrode 13. The surface area of the solder pad is larger than the corresponding cross-sectional area of the electrode, and the gap between the solder pads is sufficient, so that the solder paste and the reflow soldering process can be used to fix the semiconductor light-emitting chip on the substrate 11 and conduct electricity with the outside. connection.

In addition, when the light reflecting layer 15 is a non-metal based light reflecting layer, at least one n-type electrode interconnect layer (not shown) and/or a p-type electrode interconnect layer may be disposed in the light reflecting layer 15 (not The electrode interconnection layer may be a conductive metal layer made of a metal or alloy material having electrical conductivity, and may be a single layer structure or a multilayer structure, and the shape is not limited, and may be, for example, a rectangle, a circle, or the like. . The n-type electrode 13 and the p-type electrode 14 may be provided in multiple layers. The n-type electrode interconnection layer is electrically connected to at least one n-type electrode under the n-type electrode interconnection layer, and is electrically connected to at least one n-electrode located above the n-type electrode interconnection layer; the p-type electrode interconnection layer and at least one A p-type electrode underlying the p-type electrode interconnect layer is electrically connected to at least one p-electrode located above the p-type electrode interconnect layer. When the n-type electrode interconnection layer and the p-type electrode interconnection layer are simultaneously provided, the n-type electrode interconnection layer and the p-type electrode interconnection layer are insulated from each other. Or, when the light reflecting layer 15 is a multilayer structure including a non-metal based light reflecting layer and a metal based light reflecting layer, the metal based light reflecting layer is located between the non-metal based light reflecting layers, so that the metal based light reflecting layer can form n The type of electrode interconnection layer and/or the p-type electrode interconnection layer can eliminate the fabrication of the usual n-type electrode interconnection layer and/or p-type electrode interconnection layer, simplifying the process.

The substrate 11 is further provided with at least one p-type pad 143 electrically connected to the p-type pad 142 and at least one n-type pad 133 electrically connected to the n-type pad 132. The pad can be electrically connected to the outside. The placement positions of the p-type pad 143 and the n-type pad 133 include one or more of the first surface of the substrate 11, the second surface of the substrate 11, and the side surface of the substrate 11; and the p-type pad 143 may be interconnected by p-type The metal 144 is electrically connected to the p-type pad 142, and the n-type pad 133 is electrically connected to the n-type pad 132 through the n-type interconnect metal 134. The position at which the p-type interconnect metal 144 and the n-type interconnect metal 134 pass includes one or more of the first surface of the substrate 11, the second surface of the substrate 11, the side of the substrate 11, and the through substrate 11. Alternatively, the p-type pad 143 is a p-type pin-shaped pad electrically connected through the substrate 11 and the p-type pad 142, and the n-type pad 133 is an n-type pin electrically connected through the substrate 11 and the n-type pad 132. Shaped pad.

The substrate 11 may be an insulating substrate, including a ceramic substrate, a glass substrate, a glass-ceramic substrate, a plastic substrate, or a composite structure substrate; the substrate 11 may also be a conductive substrate, and the conductive substrate may be a metal substrate or other substrate having conductive properties, metal The material that can be used for the substrate includes one or more of iron, iron alloy, copper, copper alloy, aluminum, aluminum alloy, molybdenum, and molybdenum alloy. When the substrate 11 is a conductive substrate, between the substrate 11 and the conductive circuit, that is, the substrate 11 and the p-type pad 142, the p-type interconnect metal 144, the p-type pad 143, the n-type pad 132, and the n-type interconnection A substrate insulating layer is disposed between the metal 134 and the n-type pad 133. In the present embodiment, the substrate 11 is an insulating substrate. The first surface of the substrate 11 is a smooth flat surface or a smooth surface with a concave-convex platform.

As shown in the second figure, the semiconductor light-emitting device with a light-reflecting layer according to the second embodiment of the present invention comprises a substrate 21 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 21. The semiconductor light-emitting wafer has at least one surface and/or side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 25 except for the light-emitting surface.

The light reflecting layer 25 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 22, at least one n-type electrode 23, and at least one p-type electrode 24. The semiconductor laminate 22 includes at least an n-type conductive layer 22a, a light-emitting layer 22b and a p-type conductive layer 22c. The n-type electrode 23 is disposed on the semiconductor layer 22 and electrically connected to the n-type conductive layer 22a. The electrode 24 is disposed on the semiconductor stack 22 and is electrically connected to the p-type conductive layer 22c. On the surface of the p-type conductive layer 22c, at least one n-type electrode recess 22d is formed which exposes a portion of the n-type conductive layer 22a, and the n-type electrode 23 is provided in the n-type electrode recess 22d. The bottom surface of the n-type electrode recess 22d is located in or on the surface of the n-type conductive layer 22a. The n-type electrode recess 22d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess. In the present embodiment, the n-type electrode recess 22d is an n-type electrode recess, and the recess has a trapezoidal cross section.

The semiconductor laminate 22 is disposed on the first surface of the substrate 21 toward the substrate 21 with the p-type conductive layer 22c. The surface of the n-type conductive layer 22a facing away from the substrate 21 is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer 25 is wrapped on the surface and the peripheral side of the semiconductor laminate 22 except the light-emitting surface, at least one p-type electrode 24 and at least one n The type electrode 23 is exposed to the surface of the light reflecting layer 25. As an alternative embodiment, the light exit surface may also include some or all of the sides of the semiconductor stack 22. Further, the light reflecting layer 25 may also be wrapped onto the exposed portion of the first surface of the substrate 21.

At least one p-type current spreading layer 241 is provided in part or all of the surface of the p-type conductive layer 22c, at least one p-type electrode 24 is electrically connected to the p-type current spreading layer 241; or, on the surface of the n-type conductive layer 22a (ie, n At least one n-type current spreading layer 231 is provided in part or all of the surface of the electrode recess 22d, at least one n-type electrode 23 is electrically connected to the n-type current spreading layer 231; or, the p-type current spreading layer 241 and the n-type current spreading Layer 231 is set at the same time.

The first surface of the substrate 21 is provided with at least one p-type pad 242 and at least one n-type pad 232. The p-type pad 242 is electrically connected to at least one p-type electrode 24 exposing the light-reflecting layer, and the n-type pad 232 is electrically connected to at least one of the n-type electrodes 23 exposing the light-reflecting layer. The p-type electrode 242 and the n-type pad 232 are electrically connected to the p-type electrode 24 and the n-type electrode 23, respectively, to fix the semiconductor light-emitting wafer on the first surface of the substrate 21.

This embodiment is different from the first embodiment in that the light reflecting layer 25 includes a non-metal based light reflecting layer 251 and a metal based light reflecting layer 252. The non-metal based light reflecting layer 251 is wrapped on the surface of the semiconductor layer 22 and part or all of the p-type current spreading layer 241 and/or part or all of the n-type current spreading layer 231. The metal-based light reflecting layer 252 is located on the non-metal-based light reflecting layer 251, thereby preventing the metal-based light reflecting layer 252 from directly contacting the semiconductor layer 22 to conduct electricity. The metal-based light reflecting layer 252 can reflect light that may penetrate the non-metal-based light reflecting layer 251, particularly at the side of the semiconductor light-emitting chip, the non-metal-based light reflecting layer 251 such as a Bragg reflection layer (DBR) and total reflection. The reflectivity of the layer (ODR) will be relatively low, and the overall reflectance of the light reflecting layer 25 can be improved by using the metal-based light reflecting layer 252.

Further, at least one insulating protective layer 26 is provided between the light reflecting layer 25 and the p-type pad 242 and the n-type pad 232. That is, the insulating protective layer 26 is located on the metal-based light reflecting layer 252, and the p-type pad 242 and the n-type pad 232 are in contact with the insulating protective layer 26 to electrically connect the p-type electrode 24 and the n-type electrode 23, respectively.

In addition, the non-metal-based light-reflecting layer 251 can also be replaced by at least one light-transmissive insulating layer, and the function of reflecting light is completed by the metal-based light-reflecting layer 252, which can simplify the structure and reduce the process. The metal-based light-reflecting layer 252 is not electrically connected (insulated) to the p-type electrode 24 and the n-type electrode 23, or is only electrically connected to the p-type electrode 24 or the n-type electrode 23 to avoid the between the p-type electrode 24 and the n-type electrode 23. Conductive and short circuited.

In the above embodiment, the substrate 21 is further provided with at least one p-type pad 243 electrically connected to the p-type pad 242 and at least one n-type pad 233 electrically connected to the n-type pad 232. The pad can be electrically connected to the outside. The placement positions of the p-type pad 243 and the n-type pad 233 include one or more of the first surface of the substrate 21, the second surface of the substrate 21, and the side surface of the substrate 21; and the p-type pad 243 may be interconnected by p-type The metal 244 is electrically connected to the p-type pad 242, and the n-type pad 233 is electrically connected to the n-type pad 232 through the n-type interconnect metal 234. The position at which the p-type interconnect metal 244 and the n-type interconnect metal 234 pass includes one or more of the first surface of the substrate 21, the second surface of the substrate 21, the side of the substrate 21, and the through substrate 21. Alternatively, the p-type pad 243 is a p-type pin-shaped pad electrically connected through the substrate 21 and the p-type pad 242, and the n-type pad 233 is an n-type pin electrically connected through the substrate 21 and the n-type pad 232. Shaped pad.

The substrate 21 may be an insulating substrate, or a conductive substrate. When the substrate 21 is a conductive substrate, between the substrate 21 and the conductive circuit, that is, the substrate 21 and the p-type pad 242, the p-type interconnect metal 244, the p-type pad 243, the n-type pad 232, and the n-type interconnection A substrate insulating layer is disposed between the metal 234 and the n-type pad 233. In the present embodiment, the substrate 21 is an insulating substrate. The first surface of the substrate 21 is a smooth flat surface or a smooth surface with a concave-convex platform.

As shown in the third figure, the semiconductor light-emitting device with a light-reflecting layer according to the third embodiment of the present invention comprises a substrate 31 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 31. The semiconductor light-emitting wafer has at least one surface and/or a side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 35 except for the light-emitting surface.

The light reflecting layer 35 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 32, at least one n-type electrode 33, and at least one p-type electrode 34. The semiconductor laminate 32 includes at least an n-type conductive layer 32a, a light-emitting layer 32b, and a p-type conductive layer 32c. The n-type electrode 33 is disposed on the semiconductor layer 32 and electrically connected to the n-type conductive layer 32a. The electrode 33 is provided on the semiconductor stack 32 and is electrically connected to the p-type conductive layer 32c. On the surface of the p-type conductive layer 32c, at least one n-type electrode recess 32d is formed which exposes a portion of the n-type conductive layer 32a, and the n-type electrode 33 is provided in the n-type electrode recess 32d. The bottom surface of the n-type electrode recess 32d is located in the surface or surface of the n-type conductive layer 32a. The n-type electrode recess 32d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess.

The semiconductor laminate 32 is disposed on the first surface of the substrate 31 toward the substrate 31 with the p-type conductive layer 32c. The surface of the n-type conductive layer 32a facing away from the substrate 31 is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer 35 is wrapped on the surface and the peripheral side of the semiconductor laminate 32 except the light-emitting surface, at least one p-type electrode and at least one n-type The electrode is exposed to the surface of the light reflecting layer 35. As an alternative embodiment, the light exit surface may also include some or all of the sides of the semiconductor stack 32. Further, the light reflecting layer 35 may also be wrapped onto the exposed portion of the first surface of the substrate 31.

At least one p-type current spreading layer 341 is provided in part or all of the surface of the p-type conductive layer 32c, at least one p-type electrode 34 is electrically connected to the p-type current spreading layer 341; or, on the surface of the n-type conductive layer 32a (ie, n At least one n-type current spreading layer 331 is provided in part or all of the surface of the electrode recess 32d, at least one n-type electrode 33 is electrically connected to the n-type current spreading layer 331; or, the p-type current spreading layer 341 and the n-type current spreading Layer 331 is set at the same time.

The first surface of the substrate 31 is provided with at least one p-type pad 342 and at least one n-type pad 332. The p-type pad 342 is electrically connected to at least one p-type electrode 34 exposed to the light reflecting layer, and the n-type pad 332 is electrically connected to the at least one n-type electrode 33 exposed to the light reflecting layer. The p-type electrode pad 342 and the n-type pad 332 are electrically connected to the p-type electrode 34 and the n-type electrode 33, respectively, to fix the semiconductor light-emitting wafer on the first surface of the substrate 31.

The substrate 31 is further provided with at least one p-type pad 343 electrically connected to the p-type pad 343 and at least one n-type pad 333 electrically connected to the n-type pad 333. The pad can be electrically connected to the outside. Moreover, the p-type pad 343 can be electrically connected to the p-type pad 343 through the p-type interconnect metal 344, and the n-type pad 333 can be electrically connected to the n-type pad 333 through the n-type interconnect metal 334. For the positions where the p-type pad 343 and the n-type pad 333 are disposed, the position where the p-type interconnect metal 344 and the n-type interconnect metal 334 pass, refer to the first and second embodiments, and details are not described herein. Alternatively, the p-type pad 343 is a p-type pin-shaped pad electrically connected through the substrate 31 and the p-type pad 343, and the n-type pad 333 is an n-type pin electrically connected through the substrate 31 and the n-type pad 333. Shaped pad.

The substrate 31 may be an insulating substrate, or a conductive substrate. When the substrate 31 is a conductive substrate, a substrate insulating layer is disposed between the substrate 31 and the conductive circuit. In the present embodiment, the substrate 31 is an insulating substrate. The first surface of the substrate 31 may be a smooth flat surface or a smooth surface with a concave-convex platform.

This embodiment is different from the first and second embodiments in that the n-type electrode recess 32d is an n-type electrode recess, and the recess has a trapezoidal cross section. The area of the light-emitting layer that is used to make the n-type electrode recess is generally smaller than the area where the n-type electrode step or the n-type electrode groove is formed, so that the light-emitting efficiency of the fabricated semiconductor light-emitting chip is relatively high. In addition, the n-type electrode recesses can be arranged more evenly, so that the distribution of current is more uniform, and the light-emitting layer 32b emits light more uniformly. The anti-attenuation performance of the semiconductor light-emitting chip is more excellent because there is no current concentration region.

In this embodiment, the light reflecting layer 35 is a non-metal based light reflecting layer which is wrapped on the surface and the peripheral side of the semiconductor laminate 32 outside the light emitting surface. The non-metal based light reflecting layer is not electrically conductive, and includes, but is not limited to, one or a combination of a Bragg reflection layer (DBR) and a total reflection layer (ODR). In this embodiment, the light reflecting layer 35 also covers part or all of the p-type current spreading layer 341, and the semiconductor layer stack 32 is not provided with an n-type current spreading layer. Of course, an n-type current spreading layer may also be provided, and the light reflecting layer 35 may also be wrapped on part or all of the n-type current spreading layer.

The embodiment is different from the first embodiment and the second embodiment in that at least one n-type electrode interconnection layer 335 is disposed on part or all of the surface of the light reflection layer 35. The n-electrode interconnection layer 335 is electrically connected to at least one of the n-type electrodes 33 and insulated from the p-type electrode 34. The n-type electrode 33 may include at least one first n-type electrode 33a and at least one second n-type electrode 33b electrically connected to the n-type electrode interconnection layer 335. The first n-type electrode 33a is located below the n-type electrode interconnection layer 335, and the through-light reflection layer 35 is disposed on the n-type electrode recess 32d; the second n-type electrode 33b is located above the n-type electrode interconnection layer 335, through the n-type electrode The interconnect layer 335 is electrically connected to the first n-type electrode 33a and the n-type conductive layer 32a. It can be understood that at least one p-type electrode interconnection layer (not shown) may be electrically connected to the p-type electrode 34 in part or all of the surface of the light reflection layer 35. The n-type electrode 33 is electrically connected to the n-type pad 332 through the second n-type electrode 33b.

In this embodiment, at least one insulating protective layer 36 is disposed above the light reflecting layer 35, and the n-type electrode interconnect layer 335 is located between the insulating protective layer 36 and the light reflecting layer 35. The insulating protective layer 36 covers the n-type electrode interconnect layer 335 and the light reflecting layer 35 not covered by the n-type electrode interconnect layer 335. The p-type electrode 34 and the n-type electrode 33 are exposed through the insulating protective layer 36, respectively. The n-type pad 332 and the p-type pad 342 are in contact with the insulating protective layer 36 and are electrically connected to the n-type electrode 53 and the p-type electrode 54, respectively.

In addition, the light reflecting layer 35 may also include a non-metal based reflective layer and a metal based reflective layer, wherein the non-metal based light reflecting layer is wrapped on the surface of the semiconductor laminate 32 outside the light exiting surface, and part of the p-type current spreading layer 341. Or all or part of the n-type current spreading layer. The metal-based light reflecting layer is between the non-metal based light reflecting layer and the n-type electrode interconnect layer 335. Alternatively, an n-type electrode interconnection layer 335 and/or a p-type electrode interconnection layer are formed in the light reflection layer 35, and the n-type electrode interconnection layer 335 and/or the p-type electrode interconnection layer may be mainly reflected by metal-based light. The layers are formed so that the fabrication of the usual n-type electrode interconnection layer and/or p-type electrode interconnection layer can be omitted, simplifying the process. Wherein, the metal-based light reflecting layer is electrically conductive, including but not limited to one or more combinations of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

Alternatively, the light reflecting layer 35 may be a metal based reflective layer, and a light transmitting insulating layer is disposed between the light reflecting layer 35 and the semiconductor stacked layer 32.

As shown in the fourth figure, the semiconductor light-emitting device with a light-reflecting layer according to the fourth embodiment of the present invention comprises a substrate 41 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 41. The semiconductor light-emitting wafer has at least one surface and/or side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 45 except for the light-emitting surface.

The light reflecting layer 45 includes, but is not limited to, one or more combinations of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 42, at least one n-type electrode 43, and at least one p-type electrode 44. The semiconductor stack 42 includes at least an n-type conductive layer 42a, a light-emitting layer 42b, and a p-type conductive layer 42c. The n-type electrode 43 is disposed on the semiconductor layer 42 and electrically connected to the n-type conductive layer 42a. The electrode 44 is disposed on the semiconductor stack 42 and is electrically connected to the p-type conductive layer 42c. On the surface of the p-type conductive layer 42c, at least one n-type electrode recess 42d is formed which exposes a portion of the n-type conductive layer 42a, and the n-type electrode 43 is provided in the n-type electrode recess 42d. The bottom surface of the n-type electrode recess 42d is located in or on the surface of the n-type conductive layer 42a. The n-type electrode recess 42d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess.

The semiconductor laminate 42 is disposed on the first surface of the substrate 41 toward the substrate 41 with the p-type conductive layer 42c. The surface of the n-type conductive layer 42a facing away from the substrate 41 is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer 45 is wrapped on the surface and the peripheral side of the semiconductor laminate 42 except the light-emitting surface, at least one p-type electrode 44 and at least one n The type electrode 43 is exposed to the surface of the light reflecting layer 45. As an alternative embodiment, the light exit surface may also include some or all of the sides of the semiconductor stack 42. In addition, the light reflecting layer 45 may also be wrapped onto the exposed portion of the first surface of the substrate 41.

The first surface of the substrate 41 is provided with at least one p-type pad 442 and at least one n-type pad 432. The p-type pad 442 is electrically connected to at least one p-type electrode 44 exposing the light-reflecting layer, and the n-type pad 432 is electrically connected to at least one n-type electrode 43 exposing the light-reflecting layer. The p-type electrode 442 and the n-type pad 432 are electrically connected to the p-type electrode 44 and the n-type electrode 43, respectively, and the semiconductor light-emitting wafer is fixed on the first surface of the substrate 41. The substrate 31 is further provided with at least one p-type pad 443 electrically connected to the p-type pad 443 and at least one n-type pad 433 electrically connected to the n-type pad 433. Moreover, the p-type pad 443 can be electrically connected to the p-type pad 443 through the p-type interconnect metal 444, and the n-type pad 433 can be electrically connected to the n-type pad 433 through the n-type interconnect metal 434. For the positions where the p-type pads 443 and the n-type pads 433 are disposed, the positions where the p-type interconnection metal 444 and the n-type interconnection metal 434 pass, refer to the first and second embodiments, and details are not described herein. Alternatively, the p-type pad 443 is a p-type pin-shaped pad electrically connected to the p-type pad 443 through the substrate 41, and the n-type pad 433 is an n-type pin electrically connected through the substrate 41 and the n-type pad 433. Shaped pad.

The substrate 41 may be an insulating substrate, or a conductive substrate. When the substrate 41 is a conductive substrate, a substrate insulating layer is disposed between the substrate 41 and the conductive circuit. In the present embodiment, the substrate 41 is an insulating substrate. The first surface of the substrate 41 is a smooth flat surface or a smooth surface with a concave-convex platform.

In the present embodiment, the light reflecting layer 45 is a metal-based light reflecting layer.

This embodiment differs from the third embodiment in that at least one light transmission is provided between the light reflecting layer 45 and the surface of the semiconductor laminate 42 outside the light emitting surface, the p-type current spreading layer and/or the n-type current spreading layer. Insulation layer 47. The light-transmissive insulating layer 47 wraps part or all of the surface of the semiconductor laminate 42 outside the light surface, and the surface of the semiconductor laminate 42 not covered by the light-transmitting insulating layer 47 can directly contact the light-reflecting layer 45. In order to prevent a short circuit between the p-type conductive layer 42c, the light-emitting layer 42b, and the n-type conductive layer 42a, the light-reflecting layer 45 is directly in contact with a portion or all of the surface of the p-type conductive layer 42c or a portion of the surface of the n-type conductive layer 42a. Parts or all, corresponding to the surface of the remaining light-emitting layer 42b and the surface of the n-type conductive layer 42a or the surface of the light-emitting layer and the surface of the p-type conductive layer 42c are covered with a light-transmitting insulating layer 47.

In this embodiment, the n-type conductive layer 42a is provided with an n-type current spreading layer 431, and the p-type conductive layer 42c is not provided with a p-type current spreading layer. It can be understood that the n-type current spreading layer may not be provided, or both may be provided at the same time.

Further, an insulating protective layer 46 is further provided on the light reflecting layer 45. The p-type electrode 44 and the n-type electrode 43 are exposed through the insulating protective layer 46, respectively. The insulating protective layer 46 covers part or all of the surface of the light reflecting layer 45, and mainly protects the light reflecting layer 45 from short circuit when the light reflecting layer 45 comes into contact with other conductors. The n-type pad 432 and the p-type pad 442 are in contact with the insulating protective layer 46 and are electrically connected to the n-type electrode 43 and the p-type electrode 44, respectively.

A part or all of the light-reflecting layer 45 and the p-type conductive layer 42c may have a light-transmitting conductive expansion layer (not shown) to improve the adhesion between the light-reflecting layer 45 and the p-type conductive layer 42c, and The ability of the current to expand on the surface of the p-type conductive layer 42c. The p-type electrode 44 is electrically connected to one or more of the light-shielding layer 45, the light-transmitting conductive expansion layer, and the p-type conductive layer 42c through the insulating protective layer 46.

In addition, at least one n-type current spreading layer (not shown) may be disposed between the transparent insulating layer 47 and the n-type conductive layer 42a to enhance the expansion capability of current on the surface of the n-type conductive layer. The n-type electrode 43 is electrically connected to the n-type current spreading layer through the light reflecting layer 45 and the light transmitting insulating layer 47.

As shown in FIG. 5, a semiconductor light-emitting device with a light-reflecting layer according to a fifth embodiment of the present invention includes a substrate 51 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 51. The semiconductor light-emitting wafer has at least one surface and/or a side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 55 except for the light-emitting surface.

The light reflecting layer 55 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 52, at least one n-type electrode 53, and at least one p-type electrode 54. The semiconductor layer stack 52 includes at least an n-type conductive layer 52a, a light-emitting layer 52b and a p-type conductive layer 52c. The n-type electrode 53 is disposed on the semiconductor layer 52 and electrically connected to the n-type conductive layer 52a. The electrode 54 is disposed on the semiconductor stack 52 and is electrically connected to the p-type conductive layer 52c. On the surface of the p-type conductive layer 52c, at least one n-type electrode recess 52d is formed which exposes a portion of the n-type conductive layer 52a, and the n-type electrode 53 is provided in the n-type electrode recess 52d. The bottom surface of the n-type electrode recess 52d is located in the surface or surface of the n-type conductive layer 52a. The n-type electrode recess 52d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess.

The semiconductor laminate 52 is disposed on the first surface of the substrate 51 toward the substrate 51 with the p-type conductive layer 52c. The surface of the n-type conductive layer 52a facing away from the substrate 51 is a light-emitting surface of the semiconductor light-emitting chip, and the light-reflecting layer 55 is wrapped on the surface and the peripheral side of the semiconductor layer 52 except the light-emitting surface, at least one p-type electrode 54 and at least one n The type electrode 53 is exposed to the surface of the light reflecting layer 55. As an alternative embodiment, the light exit surface may also include some or all of the sides of the semiconductor stack 52. Further, the light reflecting layer 55 may also be wrapped onto the exposed portion of the first surface of the substrate 51.

The first surface of the substrate 51 is provided with at least one p-type pad 542 and at least one n-type pad 532. The p-type pad 542 is electrically connected to at least one p-type electrode 54 exposed to the light reflecting layer, and the n-type pad 532 is electrically connected to at least one n-type electrode 53 exposed to the light reflecting layer. The p-type electrode pad 542 and the n-type pad 532 are electrically connected to the p-type electrode 54 and the n-type electrode 53, respectively, and the semiconductor light-emitting wafer is fixed on the first surface of the substrate 51. The substrate 31 is further provided with at least one p-type pad 543 electrically connected to the p-type pad 543 and at least one n-type pad 533 electrically connected to the n-type pad 533. Moreover, the p-type pad 543 can be electrically connected to the p-type pad 543 through the p-type interconnect metal 544, and the n-type pad 533 can be electrically connected to the n-type pad 533 through the n-type interconnect metal 534. For the positions where the p-type pads 543 and the n-type pads 533 are disposed, the positions where the p-type interconnect metal 544 and the n-type interconnect metal 534 pass, refer to the first and second embodiments, and details are not described herein. Alternatively, the p-type pad 543 is a p-type pin-shaped pad electrically connected to the p-type pad 543 through the substrate 51, and the n-type pad 533 is an n-type pin electrically connected through the substrate 51 and the n-type pad 533. Shaped pad.

The substrate 51 may be an insulating substrate, or a conductive substrate. When the substrate 51 is a conductive substrate, a substrate insulating layer is disposed between the substrate 51 and the conductive circuit. In the present embodiment, the substrate 51 is an insulating substrate. The first surface of the substrate 51 is a smooth flat surface or a smooth surface with a concave-convex platform.

This embodiment is different from the fourth embodiment in that the light reflecting layer 55 includes a non-metal based light reflecting layer 551 and a metal based light reflecting layer 552, wherein the metal based light reflecting layer 552 wraps the portion of the p type conductive layer 52c. Or all, the remaining portion of the p-type conductive layer 52c, the side and bottom surfaces of the n-type electrode recess 52d, and the side surface of the semiconductor stack 52 are surrounded by the non-metal-based light reflecting layer 551. The insulating protective layer 56 is covered on the light reflecting layer 55, and the n-type pad 532 and the p-type pad 542 are disposed on the insulating protective layer 56, and the n-type electrode 53 and the p-type electrode 54 are respectively penetrated through the insulating protective layer 56 and n-type soldered. Pad 532 and p-type pad 542 are electrically connected.

In this embodiment, the n-type conductive layer 52a is provided with an n-type current spreading layer 531, at least one n-type electrode 53 is electrically connected to the n-type current spreading layer 531, and the p-type conductive layer 52c is not provided with a p-type current. Expansion layer.

As shown in the sixth embodiment, the semiconductor light-emitting device with a light-reflecting layer of the sixth embodiment includes a substrate 61 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 61. The semiconductor light-emitting wafer has at least one surface and/or a side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 65 except for the light-emitting surface.

The light reflecting layer 65 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 62, at least one n-type electrode 63, and at least one p-type electrode 64. The semiconductor layer stack 62 includes at least an n-type conductive layer 62a, a light-emitting layer 62b and a p-type conductive layer 62c. The n-type electrode 63 is disposed on the semiconductor layer 62 and electrically connected to the n-type conductive layer 62a. The electrode 64 is disposed on the semiconductor stack 62 and is electrically connected to the p-type conductive layer 62c. The semiconductor laminate 62 is disposed on the first surface of the substrate 61 toward the substrate 61 with the p-type conductive layer 62c. On the surface of the p-type conductive layer 62c, at least one n-type electrode recess 62d is formed which exposes a portion of the n-type conductive layer 62a, and the n-type electrode 63 is provided in the n-type electrode recess 62d. The bottom surface of the n-type electrode recess 62d is located in or on the surface of the n-type conductive layer 62a. The n-type electrode recess 62d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess.

The first surface of the substrate 61 is provided with at least one p-type pad 642 and at least one n-type pad 632. The p-type pad 642 is electrically connected to at least one p-type electrode 64 exposed to the light reflecting layer, and the n-type pad 632 is electrically connected to at least one n-type electrode 63 exposed to the light reflecting layer. The p-type electrode 642 and the n-type pad 632 are electrically connected to the p-type electrode 64 and the n-type electrode 63, respectively, and the semiconductor light-emitting wafer is fixed on the first surface of the substrate 61. The substrate 31 is further provided with at least one p-type pad 643 electrically connected to the p-type pad 643 and at least one n-type pad 633 electrically connected to the n-type pad 633. Moreover, the p-type pad 643 can be electrically connected to the p-type pad 643 through the p-type interconnect metal 644, and the n-type pad 633 can be electrically connected to the n-type pad 633 through the n-type interconnect metal 634. The positions at which the p-type pads 643 and the n-type pads 633 are disposed, the positions at which the p-type interconnect metal 644 and the n-type interconnect metal 634 pass may be referred to the first and second embodiments, and are not described herein again. Alternatively, the p-type pad 643 is a p-type pin-shaped pad electrically connected to the p-type pad 643 through the substrate 61, and the n-type pad 633 is an n-type pin electrically connected through the substrate 61 and the n-type pad 633. Shaped pad.

The substrate 61 may be an insulating substrate, or a conductive substrate. When the substrate 61 is a conductive substrate, a substrate insulating layer is disposed between the substrate 61 and the conductive circuit. In the present embodiment, the substrate 61 is an insulating substrate. The first surface of the substrate 61 is a smooth flat surface or a smooth surface with a concave-convex platform.

This embodiment is different from the fifth embodiment in that the n-type electrode recess 62d is an n-type electrode recess or an n-type electrode recess having a rectangular cross section. The surface of the n-type conductive layer 62a facing away from the substrate 61 is the light-emitting surface of the semiconductor light-emitting chip, and the light-emitting surface may further include all of the peripheral sides of the semiconductor layer 62. The light-reflecting layer 65 is wrapped on the surface of the semiconductor layer 62 except the light-emitting surface. Upper; at least one p-type electrode 64 and at least one n-type electrode 63 are exposed on the surface of the light reflecting layer 65. As an alternative embodiment, the light reflecting layer 65 may also be wrapped onto the exposed portion of the first surface of the substrate 61.

In this embodiment, the light reflecting layer 65 is a metal-based light reflecting layer which covers part or all of the surface of the p-type conductive layer 62c or a part or all of the surface of the n-type conductive layer 62a, corresponding to the surface of the remaining light-emitting layer 62b. And the surface of the n-type conductive layer 62a or the surface of the light-emitting layer 62b and the surface of the p-type conductive layer 62a are covered with a light-transmitting insulating layer 67 to prevent the light-reflecting layer from passing between the p-type conductive layer 62c, the light-emitting layer 62b, and the n-type conductive layer 62a. 65 conductive short circuit.

In this embodiment, the n-type conductive layer 62a is provided with an n-type current spreading layer 631, at least one n-type electrode 63 is electrically connected to the n-type current spreading layer 631, and the p-type conductive layer 62c is not provided with a p-type current. Expansion layer. The light reflecting layer 65 wraps the entire surface of the side of the p-type conductive layer 62c of the semiconductor layer 62, and the light-transmitting insulating layer 67 is n-type wrapped between the light reflecting layer 65 and the semiconductor layer 62 in the n-type electrode recess 62d. The surface of the conductive layer 62a, the surface of the light-emitting layer 62b, and the n-type current spreading layer 631. It can be understood that the n-type current spreading layer 631 may not be provided.

Further, an insulating protective layer 66 is further disposed on the light reflecting layer 65. The p-type electrode 64 and the n-type electrode 63 are exposed through the insulating protective layer 66, respectively. The insulating protective layer 66 covers part or all of the surface of the light reflecting layer 65, and mainly protects the light reflecting layer 65 from short circuit when the light reflecting layer 65 is in contact with other conductors. The n-type pad 632 and the p-type pad 642 are in contact with the insulating protective layer 66 and are electrically connected to the n-type electrode 63 and the p-type electrode 64, respectively.

As shown in the seventh embodiment, the semiconductor light-emitting device with a light-reflecting layer according to the seventh embodiment of the present invention comprises a substrate 71 having a first surface and a second surface, and a semiconductor light-emitting chip disposed on the substrate. On the first surface of 71. The semiconductor light-emitting wafer has at least one surface and/or a side surface which is a light-emitting surface. The other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer 75 except for the light-emitting surface.

The light reflecting layer 75 includes, but is not limited to, one or a combination of a non-metal based light reflecting layer and a metal based light reflecting layer. Wherein, the non-metal-based light reflecting layer is not electrically conductive, including but not limited to one or a combination of a Bragg reflection layer (DBR) and an total reflection layer (ODR); the metal-based light reflecting layer is electrically conductive, including but not It is limited to one or a combination of Cu, Sn, Au, Pb, Al, Ag, Ni, Ti, W, Pt, Pd, and alloys thereof.

The semiconductor light emitting wafer includes at least one semiconductor stack 72, at least one n-type electrode 73, and at least one p-type electrode. The semiconductor laminate 72 includes at least an n-type conductive layer 72a, a light-emitting layer 72b and a p-type conductive layer 72c. The n-type electrode 73 is disposed on the semiconductor layer 72 and electrically connected to the n-type conductive layer 72a. The electrodes are disposed on the semiconductor stack 72 and are electrically connected to the p-type conductive layer 72c. The semiconductor laminate 72 is disposed on the first surface of the substrate 71 toward the substrate 71 with the p-type conductive layer 72c. On the surface of the p-type conductive layer 72c, at least one n-type electrode recess 72d is formed which exposes a portion of the n-type conductive layer 72a, and the n-type electrode 73 is provided in the n-type electrode recess 72d.

The bottom surface of the n-type electrode recess 72d is located in the surface or surface of the n-type conductive layer 72a. The n-type electrode recess 72d includes one or more of an n-type electrode step, an n-type electrode recess, and an n-type electrode recess. In the present embodiment, the n-type electrode recess 72d is an n-type electrode recess or an n-type electrode recess having a rectangular cross section.

The first surface of the substrate 71 is provided with at least one p-type pad 742 and at least one n-type pad 732. The p-type pad 742 is electrically connected to at least one p-type electrode exposed to the light reflecting layer, and the n-type pad 732 is electrically connected to the at least one n-type electrode 73 exposed to the light reflecting layer. The p-type electrode 742 and the n-type pad 732 are electrically connected to the p-type electrode and the n-type electrode 73, respectively, and the semiconductor light-emitting wafer is fixed on the first surface of the substrate 71.

The substrate 31 is further provided with at least one p-type pad 743 electrically connected to the p-type pad 743 and at least one n-type pad 733 electrically connected to the n-type pad 733. Moreover, the p-type pad 743 can be electrically connected to the p-type pad 743 through the p-type interconnect metal 744, and the n-type pad 733 can be electrically connected to the n-type pad 733 through the n-type interconnect metal 734. The positions at which the p-type pad 743 and the n-type pad 733 are disposed, the position at which the p-type interconnect metal 744 and the n-type interconnect metal 734 pass may be referred to the first and second embodiments, and are not described herein again. Alternatively, the p-type pad 743 is a p-type pin-shaped pad electrically connected through the substrate 71 and the p-type pad 743, and the n-type pad 733 is an n-type pin electrically connected through the substrate 71 and the n-type pad 733. Shaped pad.

The substrate 71 may be an insulating substrate or a conductive substrate. When the substrate 71 is a conductive substrate, a substrate insulating layer is disposed between the substrate 71 and the conductive circuit. In the present embodiment, the substrate 71 is an insulating substrate. The first surface of the substrate 71 is a smooth flat surface or a smooth surface with a concave-convex platform.

In this embodiment, the surface of the n-type conductive layer 72a facing away from the substrate 71 is the light-emitting surface of the semiconductor light-emitting chip, and the light-emitting surface may further include all of the surrounding sides of the semiconductor laminate 72. The light-reflecting layer 75 is wrapped around the light-emitting surface. On the surface of the semiconductor stack 72; at least one p-type electrode and at least one n-type electrode 73 are exposed on the surface of the light reflecting layer 75. As an alternative embodiment, the light reflecting layer 75 may also be wrapped onto the exposed portion of the first surface of the substrate 71.

The light reflecting layer 75 is a metal-based light reflecting layer which covers part or all of the surface of the p-type conductive layer 72c or a part or all of the surface of the n-type conductive layer 72a, corresponding to the surface of the remaining light-emitting layer 72b and n-type conductive The surface of the layer 72a or the surface of the light-emitting layer 72b and the surface of the p-type conductive layer 72a are covered with a light-transmitting insulating layer 77 to prevent the p-type conductive layer 72c, the light-emitting layer 72b, and the n-type conductive layer 72a from being electrically short-circuited by the light-reflecting layer 75.

In this embodiment, the n-type conductive layer 72a is provided with an n-type current spreading layer 731, at least one n-type electrode 73 is electrically connected to the n-type current spreading layer 731, and the p-type conductive layer 72c is not provided with p-type current spreading. Floor. The light reflecting layer 75 wraps the entire surface of the side of the p-type conductive layer 72c of the semiconductor laminate 72, and the light transmitting insulating layer 77 is wrapped around the surface of the n-type conductive layer 72a and the light emitting layer between the light reflecting layer 75 and the semiconductor layer 72. The 72b surface and the n-type current spreading layer 731. It can be understood that the n-type current spreading layer 731 may not be provided.

An insulating protective layer 76 is provided on the light reflecting layer 75. The p-type electrode and the n-type electrode 73 are exposed through the insulating protective layer 76, respectively. The n-type pad 732 and the p-type pad 742 are in contact with the insulating protective layer 76 and are electrically connected to the n-type electrode 73 and the p-type electrode, respectively.

This embodiment is different from the sixth embodiment in that at least one n-type electrode interconnection layer 735 and at least one p-type electrode interconnection layer 745 are provided in the insulating protection layer 76. The n-type electrode interconnection layer 735 is electrically connected to at least one n-type electrode 73 under the n-type electrode interconnection layer 735, and is electrically connected to at least one n-electrode 73 located above the n-type electrode interconnection layer 735; the p-type electrode is mutually The layer 745 is electrically connected to at least one p-type electrode under the p-type electrode interconnection layer 745, and is electrically connected to at least one p-electrode over the p-type electrode interconnection layer 745. The n-type electrode interconnection layer 735 and the p-type electrode interconnection layer 745 may also be provided with only one of them.

Specifically, in this embodiment, an n-type electrode interconnection layer 735 and a p-type electrode interconnection layer 745 are simultaneously provided, and the insulating protection layer 76 is formed into a plurality of layers and the n-type electrode interconnection layer 735 and the p-type electrode are mutually The layer 745 is set therein. The n-type electrode 73 may include at least one first n-type electrode 73a and at least one second n-type electrode 73b, the first n-type electrode 73a being located under the n-type electrode interconnection layer 735, penetrating below the n-type electrode interconnection layer 735. The insulating protective layer 76 is disposed on the n-type electrode recess 72d; the second n-type electrode 73b is located above the n-type electrode interconnect layer 735 through the insulating protective layer 76 over the n-type electrode interconnect layer 735 and the n-type pad 732 Conductive connection. The p-type electrode may include at least one first p-type electrode 74a and at least one second p-type electrode 74b, the first p-type electrode 74a being located under the p-type electrode interconnection layer 745, and insulating under the p-type electrode interconnection layer 745 The protective layer 76 is disposed on the p-type conductive layer 72c; the second p-type electrode 74b is disposed above the p-type electrode interconnect layer 745 through the insulating protective layer 76 over the p-type electrode interconnect layer 745 to conduct electricity with the p-type pad 742. connection. The n-type electrode interconnection layer 735 and the p-type electrode interconnection layer 745 are insulated from each other.

It can be seen from the above that the semiconductor light-emitting device of the present invention has high luminous efficiency, good light shape, and is widely applicable, and is particularly suitable for a projection type light source and device requiring a small emission angle.

In the above embodiments, the side surface of the semiconductor laminate is one or a combination of a plane perpendicular to or at an oblique angle, a roughened surface, and a structured surface, and the structure includes, but is not limited to, a concave-convex shape, a zigzag shape, and an arc shape. One or more combinations. In the above embodiment, the light emitting surface of the semiconductor light emitting chip may be wrapped by at least one passivation layer, at least one phosphor layer, at least one encapsulation layer, and at least one package. The passivation layer is made of a light-transmissive insulating material, including one or more of silicone, resin, glass, ceramic, oxide, and nitride; the phosphor layer includes a phosphor powder layer, a silicone powder doped with a phosphor powder, a resin layer, and a glass. One or more of the layers; the encapsulating layer comprises one or more of a silicone layer, a resin layer, and a glass layer; the package may be formed into different shapes to take light and collect light, or may be disposed outside the fluorescent layer Protect the fluorescent layer from the outside world.

It will be understood that each of the above technical features may be used in any combination without limitation.

The above descriptions are only examples of the present invention, and are not intended to limit the scope of the patents of the present invention. Any equivalent structure or equivalent process transformation using the contents of the present specification and drawings may be directly or indirectly applied to other related The technical field is equally included in the scope of patent protection of this creation.

11‧‧‧Substrate

15‧‧‧Light reflection layer

12‧‧‧Semiconductor laminate

12a‧‧‧n type conductive layer

12b‧‧‧Lighting layer

12c‧‧‧p type conductive layer

12d‧‧‧n type electrode depression

13‧‧‧n type electrode

14‧‧‧p-type electrode

141‧‧‧p type current expansion layer

131‧‧‧n type current expansion layer

132‧‧‧n type solder pads

142‧‧‧p type solder pad

133‧‧‧n type pad

143‧‧‧p-type pad

134‧‧‧n type interconnect metal

144‧‧‧p type interconnect layer metal

Claims (12)

A semiconductor light emitting device with a light reflecting layer, comprising: a substrate having a first surface and a second surface, wherein the first surface is provided with a semiconductor light emitting wafer; wherein the semiconductor light emitting chip has at least one surface or The side is a light-emitting surface, and other surfaces and sides of the semiconductor light-emitting wafer are surrounded by at least one light-reflecting layer except for the light-emitting surface. The semiconductor light-emitting device with a light-reflecting layer according to claim 1, wherein the light-reflecting layer comprises at least one selected from the group consisting of a non-metal-based light-reflecting layer and a metal-based light-reflecting layer. One of them. The semiconductor light-emitting device with a light-reflecting layer according to the invention of claim 2, wherein the semiconductor light-emitting chip comprises at least one semiconductor stack, the semiconductor stack comprising at least one n-type conductive layer, a light emitting layer and a p-type conductive layer; the semiconductor stack is provided with at least one n-type electrode electrically connected to the n-type conductive layer and at least one p-type electrode electrically connected to the p-type conductive layer; Having at least one n-type electrode recess exposing a portion of the n-type conductive layer on the surface of the p-type conductive layer, the n-type electrode being disposed in the n-type electrode recess; the semiconductor stack being electrically conductive with the p-type a layer disposed on the first surface of the substrate toward the substrate; and a surface of the n-type conductive layer facing away from the substrate is a light-emitting surface of the semiconductor light-emitting chip, the light-reflecting layer being wrapped At least one of the p-type electrode and at least one of the n-type electrodes expose the surface of the light reflecting layer on the surface and the peripheral side of the semiconductor laminate outside the light-emitting surface. The light-emitting layer-attached semiconductor light-emitting device of claim 3, wherein the light-emitting surface further comprises part or all of the side surfaces of the semiconductor laminate. The semiconductor light-emitting device with a light-reflecting layer according to claim 3, wherein an n-type electrode interconnection layer is formed in the light reflection layer, and the n-type electrode interconnection layer and at least one of the An n-type electrode is electrically connected; or a p-type electrode interconnection layer is formed in the light reflection layer, and the p-type electrode interconnection layer is electrically connected to at least one of the p-type electrodes; and the n-type electrode is mutually The tie layer and p-type electrode interconnect layers are insulated from each other. The semiconductor light-emitting device with a light-reflecting layer according to claim 3, wherein a part or all of the surface of the p-type conductive layer is provided with at least one p-type current spreading layer, at least one of the p-type electrodes Conductively connected to the p-type current spreading layer; and the light reflecting layer wrapping part or all of the p-type current spreading layer; or
And at least one of the n-type electrodes is electrically connected to the n-type current spreading layer; and the light reflecting layer is partially wrapped or partially All of the n-type current spreading layers. The semiconductor light-emitting device with a light-reflecting layer according to claim 6, wherein the p-type current spreading layer comprises one or more of a p-type light-transmitting current spreading layer and a p-type metal-based current-amplifying reflecting layer. Combining; the p-type light-transmitting current spreading layer comprises at least one selected from the group consisting of ZnO, ITO, and a heavily doped p-type conductive layer, the p-type metal-based current spreading reflective layer comprising At least one of the group consisting of a p-type metal diffusion barrier layer, a p-type conductivity expansion layer, a p-type light reflection layer, and a p-type contact layer;
The n-type current spreading layer includes at least one selected from the group consisting of an n-type light-transmitting current spreading layer and an n-type metal-based current-expanding reflective layer; the n-type light-transmitting current spreading layer includes And at least one selected from the group consisting of ZnO, ITO, and a heavily doped n-type conductive layer, the n-type metal-based current spreading reflective layer comprising an n-type metal diffusion barrier layer, p-type conductive extension At least one of the group consisting of a layer, a p-type light reflecting layer, and a p-type contact layer. The semiconductor light-emitting device with a light-reflecting layer according to claim 6, wherein at least one transparent insulating layer is disposed between the light-reflecting layer and the p-type current spreading layer or the n-type current spreading layer. . The semiconductor light-emitting device with a light-reflecting layer according to claim 3, wherein the first surface of the substrate is provided with at least one p-type pad and at least one n-type pad;
The p-type pad is electrically connected to the p-type electrode exposing the light reflecting layer, and the n-type pad is electrically connected to the n-type electrode exposing the light reflecting layer; or Providing at least one insulating protective layer on the light reflecting layer, at least one of the p-type electrodes exposing the insulating protective layer electrically connected to the p-type pad, and at least one of the n-type electrodes exposing the insulating A protective layer is electrically connected to the n-type pad. The semiconductor light-emitting device with a light-reflecting layer according to claim 9, wherein at least one n-type electrode interconnection layer is disposed in the insulating protection layer, and the n-type electrode interconnection layer and at least An n-type electrode underlying the n-type electrode interconnection layer is electrically connected, and is electrically connected to at least one of the n-electrodes located above the n-type electrode interconnection layer; or
Providing at least one p-type electrode interconnection layer in the insulating protective layer, the p-type electrode interconnection layer being electrically connected to at least one p-type electrode under the p-type electrode interconnection layer, and at least A p-electrode electrically connected above the p-type electrode interconnect layer; and the n-type electrode interconnect layer and the p-type electrode interconnect layer are insulated from each other. The semiconductor light-emitting device with a light-reflecting layer according to claim 9, wherein the substrate is further provided with at least one p-type pad and at least one n-type pad;
Positioning the p-type pad includes at least one selected from the group consisting of a first surface, a second surface, and a side surface of the substrate; the p-type pad passing through at least one p-type mutual The metal is electrically connected to the p-type pad, and the position through which the p-type interconnect metal passes includes a group selected from the first surface, the second surface, the side surface of the substrate, and the substrate At least one of; or, the p-type pad is a p-type pin-shaped pad electrically connected to the p-type pad through the substrate; and the position of the n-type pad is selected At least one of the group consisting of a first surface, a second surface, and a side surface of the substrate; the n-type pad is electrically connected to the n-type pad by at least one n-type interconnect metal, and The position through which the n-type interconnect metal passes includes at least one selected from the group consisting of a first surface, a second surface, a side surface of the substrate, and a group formed by the substrate; or the n-type solder The disk is an n-type pin-shaped pad electrically connected to the n-type pad through the substrate. The semiconductor light-emitting device with a light-reflecting layer according to claim 3, wherein the n-type electrode recess comprises a pit selected from an n-type electrode step, an n-type electrode recess, and an n-type electrode recess. At least one of the groups.