TWM272230U - Packaged chip capable of reducing electromagnetic interference - Google Patents

Packaged chip capable of reducing electromagnetic interference Download PDF

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Publication number
TWM272230U
TWM272230U TW094201846U TW94201846U TWM272230U TW M272230 U TWM272230 U TW M272230U TW 094201846 U TW094201846 U TW 094201846U TW 94201846 U TW94201846 U TW 94201846U TW M272230 U TWM272230 U TW M272230U
Authority
TW
Taiwan
Prior art keywords
chip
conductor layer
electromagnetic interference
lead frame
patent application
Prior art date
Application number
TW094201846U
Other languages
English (en)
Inventor
Chung-Shing Tz
Original Assignee
Domintech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Domintech Co Ltd filed Critical Domintech Co Ltd
Priority to TW094201846U priority Critical patent/TWM272230U/zh
Priority to US11/165,170 priority patent/US7119420B2/en
Publication of TWM272230U publication Critical patent/TWM272230U/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

M272230 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種可降低電磁干擾之封裝晶片，特別 指一種具有接地及屏蔽結構，可降低電氣雜訊干擾，並增 進速率之封裝晶片結構改良。 【先前技術】 按，任何電子產品運作使用時，均會產電磁波干擾（
Electromagnetic Interference, EMI)、雜訊（Noise，包括
如散彈雜訊、閃爍雜訊、突波雜訊、熱雜訊、分配雜訊等 )及高溫等情形，其中大部分雜訊的產生，係源於電磁波 干擾的情況，因而影響電子系統的穩定性；惟電磁波干擾 並不能完全克服，係必需透過該電子元件適當的電路規劃 或屏蔽、接地等結構設計，使電磁波干擾降低至標準數值 之下，以達成電磁相容設計目的。 習知的封裝晶片，通常為一晶墊上置設有一晶片，於 該晶片兩側設有可對外導通電性之導線架，其中該導線架 係為複數引腳排列構成，並選定於晶片其接點及 加7 複數引腳間設有金線連接，且於該晶片外部設有==性 的封膠體，藉該封膠體保護晶片、金線等内部元件，同日士 達成固定作用。上揭習知的晶片封裝，並無防止電磁波‘ 擾之結構設計’因此在降低電磁波干擾目的下，即難 合現今電子產品其電磁相容之高標準要求。 ' 付 【新型内容】 本創作^要目的’係在提供一種可降低電磁干擾 裝晶片，係藉以晶片整體封裝結構改良，除了夂 訊隔絕、降低電磁波干擾、增進傳輸速率等效=電= M272230 獲致節約封膠材料之效果。 依上述目的，本創作之實施内容係包括一晶片之電訊 接點面固設有一導線架，該導線架為二排或四排矩陣之排 列之複數引腳構成，於各引腳底面設有一外接電凸塊、 形導體、錐形導體或其他足以導電之結構體，令各引腳内 端以導線與晶片之電訊接點連接，而導線架外接電凸塊該 面係設有一絕緣性黏著層黏固一導體層，於導體層對應外 接電凸塊部位分別設有通孔，使所述外接電凸塊、球形 體、錐形導體或其他足以導電之結構體延伸出通孔外，並 令晶片至少一電訊接點與該導體層形成電性連接，藉此組 成该導體層可作為接地面或電源面之封裝晶片，進一步庐 致降低電磁干擾及增進速率之效果。 v又 【實施方式】 茲依附圖實施例將本創作之結構特徵及其他之作用 目的詳細說明如下： 曰如附圖所示’本創作所為之『可降低電磁干擾之封裝 晶片』’係包括-晶片！、一導線架2、複數導線3、一黏 著層4及一導體層5所組成，其中·· 晶片1，如第一圖所示，係為習知半導體材料製成之 電子7G件，於選定面設有複數電訊接點”； _導線架2，為金屬材料沖壓呈二排平行（如第四圖所 不）或四排矩陣陣列（如第五圖所示）之複數引腳21所構 ^，於各引腳21底面選定處分別設有_外接電凸塊22 (如 第一圖所示）’可令各外接電凸塊22形成對齊排列狀態； 導線3，係使該晶片之電訊接點”可與導線架2各 引腳21形成電性連接之金屬導體，例如金線等； 膠水等Γ =帶:為形成㈣之物質 M272230 導體層5 ’如第三圖所示，係可為一片狀金屬板或金 屬膜，於板面對應導線架2各引腳21之外接電凸塊22部位 分別設有通孔51 ; 藉此如第一圖所不，於晶片工之電訊接點j j該面固 設有-所述之導線架2，使該導線架2之外接電凸塊22位 於外側ϋ 7導線架2各引腳21内端以導線3分別與晶片 1之電訊接點11連接’而具有外接電凸塊22之導線架2該 面係設有一所述之黏著層4，用以該黏著層4黏固一導體 層5，恰使各該引腳21之外接電凸塊22延伸出通孔51外， 並令該晶片1至少一電訊接點11與該導體層5形成電性連 接，藉此組成導體層5可作為接地面（Gr_d帅⑽）或 電源面（Power p丨ane)之封裝晶片，進一步獲致電氣雜訊 隔絕、降低電磁波干擾、增進傳輸速率等效果。其中，晶 片1固設導線架2方式，係可使用如上述液態乾燥後可形 成黏固物質（如膠水）或膠帶等之另—黏著層4，，藉此完 成固定功能。 + ▲運用本創作可降低電磁干擾之封裝晶片結構改良，係 藉該導體層5所形成之為接地面（G_nd p丨ane)或電源 面（Power plane )，俾達成所述電氣雜訊隔絕、降低電磁 波干擾及增進傳輸速率等效果。另因本創作該導體層5可 應用金屬板實施完成，其藉以黏著層4黏固於導線架2外 側面狀態’恰可密封晶片丄電訊接㈣部位及導線3 (如 第一圖所示），故能同步獲致節省封膠材料之封裝效果。 2次’如第二圖至第四圖所示，本創作該導體層5亦 可選疋對應晶片1電訊接點11部位設有一鏤空部Μ，藉此 依上述方式依序組裝晶片1、導線架2、黏著層4及導體 曰5構成封裝晶片後，再經由導體層5之鏤空部針對晶 片1電訊接點11及各引腳21進行連結導線3，並令該晶片 M272230 1至少一電訊接點彳彳與該導體層5形成電性連接，即可於 導體層5之鏤空部52處實施一局部封膠體6，將該電訊接 點11及導線3等密封，達成保護作用，且能以該導體層5 進一步獲致電氣雜訊隔絕、降低電磁波干擾、增進傳輸速 率等效果。 復請參閱第一圖及第二圖所示，所述該晶片1至少一 電訊接點11與導體層5形成電性連接之方式，係可採以— 導電物7構成電性連接，例如應用一金屬導線連結於電訊 接點11與導體層5間，即能令導體層5作為接地面（Gr〇lJnd Plane)或電源面（Power p|ane)，俾獲致前述之效果。 參閱第六圖所示，本創作該導體層5之複數通孔51係 對應各引腳21之外接電凸塊22位置而設，是以各引腳21之 外接電凸塊22於形成相互交錯位置排列狀時，該導體層$ 之複數通孔51亦可對應形成相互交錯位置排列狀，使外接 電凸塊22可經由各通孔51外露與電路板等其他電子設備作 電性連接，俾達成防止電性連接時之焊錫溢流導致短路， 確保該封裝晶片安裝應用時的良品率。 另者’鈿述導線条2各引腳21底面之外接電△掩2 2，
W不，亦可於各引腳21底面結合有對應導體層5各通孔51 之球形導體23(如：錫球）或錐形導體24，或其他足以導電之 ，使該球形導體23或錐形導體24延伸出通孔
各種結構形態， 51外，並令晶片 連接’藉此亦組
M272230 ，並賜准專 法提出新型專利申請，惟懇請鈞局惠予詳審 利為禱，至感德便。
9 M272230 【圖式簡單說明】 • 第一圖為本創作封裝狀態之斷面示意圖。 • 圖為本創作導體層料鏤空部之封裝狀態斷面示 意圖。 第三圖為本創作局部構件分解狀態之立體示意圖。 - 第四圖為本創作二排引腳之封裝狀態示意圖。 第五圖為本創作四排引腳之封裝狀態示意圖。 第六圖為本創作外接電凸塊及導體層通孔形成交錯位 置排列狀之封裝狀態示意圖。 φ 第七圖為本創作外接電凸塊另一實施例示意圖之一。 第八圖為本創作外接電凸塊另一實施例示意圖之二。 【主要元件符號說明】 電訊接點11 ; 引腳21 ; 球形導體23 ; 導線3， 導體層5 ; 鏤空部52 ; 導電物7 ; 晶片1 ; 導線架2 ; 外接電凸塊22 ; 錐形導體24 ; 黏著層4、4 ’ ； 通孔51 ; • 封膠體6 ;

Claims (1)

  1. M272230 九、申請專利範圍： 1、一種可降低電磁干擾之封裝晶片，包括一晶片、複數 排列狀引腳所構成之導線架，於導線架各引腳一面分 別设有外接電凸塊，其特徵在於： 晶片之電訊接點面固設有一導線架，使導線架之 外接電凸塊位於外側，並令導線架各引腳以導線分別 與晶片構成電性連接，且導線架之外接電凸塊該面係 設有一黏著層固設一導體層；該導體層係為一板體^ 於板面對應各引腳外接電凸塊部位分別設有通孔，使 各外接電凸塊延伸出導體層之通孔外；並令晶片至少 一電訊接點與該導體層形成電性連接，以組成可降低 電磁干擾之封裝晶片者。 2、 如申請專利範圍第2項所述可降低電磁干擾之封裝 晶片，其中，該晶片至少一電訊接點與導體層形成電 性連接之方式，包括可採以一導電物構成電性連接， 使導體層可作為接地面（Gr〇undp丨ane)或電源面（ Power plane) 〇 3、 如申請專利範圍第i項所述可降低電磁干擾之封裝 晶片，其中，該導體層之通孔包括可為複數相互對齊 排列狀；並包括可為相互交錯位置排列狀。 4、 =申請專利範圍第i項所述可降低電磁干擾之封裝 晶片，其中，該導體層包括可選定對應晶片之電訊接 點σ卩位δ又有一鏤空部，並鏤空部設有封膠體。 、如申請專利範圍第丨項所述可降低電磁干擾之封裝晶 片，、其中，該外接電凸塊包括可為球形導體、錐形^ 體或其他足以導電之結構形態。
TW094201846U 2005-02-01 2005-02-01 Packaged chip capable of reducing electromagnetic interference TWM272230U (en)

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US8589832B2 (en) * 2007-08-24 2013-11-19 International Business Machines Corporation On chip shielding structure for integrated circuits or devices on a substrate and method of shielding

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