TWM262839U - Wafer glue-coating structure for wafer packaging - Google Patents

Wafer glue-coating structure for wafer packaging Download PDF

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Publication number
TWM262839U
TWM262839U TW093212582U TW93212582U TWM262839U TW M262839 U TWM262839 U TW M262839U TW 093212582 U TW093212582 U TW 093212582U TW 93212582 U TW93212582 U TW 93212582U TW M262839 U TWM262839 U TW M262839U
Authority
TW
Taiwan
Prior art keywords
wafer
glue
printing
packaging
layer
Prior art date
Application number
TW093212582U
Other languages
Chinese (zh)
Inventor
Yau-Chi Fei
Chang-Hua Chen
Original Assignee
D Tek Semicon Technology Co Lt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by D Tek Semicon Technology Co Lt filed Critical D Tek Semicon Technology Co Lt
Priority to TW093212582U priority Critical patent/TWM262839U/en
Publication of TWM262839U publication Critical patent/TWM262839U/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

M262839 八 、新型說明: 【新型所屬之技術領域】 造㈠,tit係ΐ關於一種用於晶片封裝之晶圓塗膠構 /…、有改善傳統晶片封裝技術之能力争 正面塗膠方法印刷黏膠於晶圓上’可以== 曰曰固 ίί進行’再將晶圓切割後貼附於基材上,i後通 度古提昇生產良率’節省工時=ΐ具; iti:有大效果之創作’可用於大多數晶片封裝生 【先前技術】 般相關業界賴知的,晶片封裝生產線量產能力 ^升疋近年來各種之晶丨封裝及紅廠商積極研發及建 =項目,其所使用之技術方式如生產流程改善或新材料 3用等等可適用於各種晶片封裝之場所,以使得降低成 成本需求得以達成;目前為止生產流程改善可以 »:书重要的改善項目,因為晶片封裝的機台多為精密 工業專Η製做之機械,略有更改,往往代價高昂,但是可 以配合固有的機台特性做出週邊流程之改善,相對成本較 低而且成效顯著。 在1C基板方面(包括BGA(球型栅狀陣列基板)、 CSP(晶片規格封裝基板)、Flip chip(覆晶基板)三大類), ’、中C基板進年成長幅度大;近年來台灣、南韓及大陸 等地並積極擴充增層基板的產量及持續投資雷射鑽孔機 M262839 設備,使其增加基板生產上的競爭力。未來由於可 、, 子產品輕薄短小之需求趨勢,將促使電路板朝向纟攜式屯 微孔技術發展,加上小型封裝技術的進步,也# &M262839 8. Description of the new type: [Technical field to which the new type belongs] Tit is related to a wafer coating structure used for chip packaging / ..., capable of improving traditional chip packaging technology, competing for front side coating method, printing adhesive On the wafer, 'can == say 固 固 ίί', and then the wafer is cut and attached to the substrate, and after that, it improves the production yield and saves man-hours = tools; iti: has a great effect "Creation" can be used for most chip packaging productions [Previous technology] Generally relevant industry knows, the volume production capacity of chip packaging production lines ^ liters in recent years a variety of crystals 丨 packaging and red manufacturers actively research and development and construction = projects, the use of Technical methods such as improved production processes or new materials can be applied to various chip packaging places, so that the reduction of cost requirements can be achieved; so far, production process improvements can be made »: important improvement items of the book, because the chip packaging machine Most of the machines are made by precision industry. They are slightly changed and often expensive, but they can be improved in accordance with the inherent machine characteristics and the relative cost is relatively low. And the results are significant. In terms of 1C substrates (including BGA (ball grid array substrate), CSP (chip-size package substrate), and Flip chip (chip-on-chip substrates), the three major categories), 'C-substrates have grown significantly in recent years; in recent years, Taiwan, South Korea and the mainland have actively expanded the production of multilayer substrates and continued to invest in laser drilling machine M262839 equipment to increase their competitiveness in substrate production. In the future, due to the trend of light, thin and short sub-products, the circuit board will be driven toward the development of portable micro-hole technology, coupled with the advancement of small-scale packaging technology, also # &

1文件高階1C 片看好。 預期未來 基板的需求提高,連帶使小尺寸晶片封裝前 為了滿足手機板、通訊產品及汽車工業的需求, 小尺寸晶片封裝將會再持續發展。 BGA、CSP與Flip chip構裝結構雖然變 、文1匕不少,叙 傳統Lead frame型構裝比較最大的差異在於 大量應用;從基板、Solder mask、封裳材料都,柯料的1 file high-end 1C films are optimistic. It is expected that the demand for substrates will increase in the future. In order to meet the needs of mobile phone boards, communication products and the automotive industry before small-scale chip packaging, small-size chip packaging will continue to develop. Although the structure of the BGA, CSP and Flip chip structures has changed a lot, the biggest difference between the traditional Lead frame structure is the large number of applications; from the substrate, Solder mask, and seal materials, the

Polyimide、BT、Epoxy等有機材料的縱影。〜可以發現 的相關製程觀察,其技術内涵極為豐富; «這些材料 液態封膠配方開發、構裝產品應用與可I & 電錢等)、 術。無論對原材料開發者(化學品礙)、基 /刀 廠)、或封裝設計與製造者(半導體廠、封H 4 ^ ^ 〃 ·…i…… ’瞭解這些 製作(包括如原材料開發、壓合、蝕刻、 可分為基板 J晋層、Φ ^、 析等技 者(基板 材料及其製程’進一步適當的設計遍還田 、用材料,廡Η 尤其製程 終極BGA、CSP與Flip chip構裝的應疋旱握 之改善更是台灣科技業的專長。 / 如第一 Α圖或第一 Β圖所示,-羽各 在習知之晶;4其祐扣 裝生產線中,有一種晶片基板組合件,+曰曰片基板封 τ 具具有兩層或一層 裝配晶片之需求(彼此構造類似),且該兩片 曰 16等零件通常為以薄膠膜17黏合,品Α Α 舶 σ 而一般為 IC(IntegralPolyimide, BT, Epoxy and other organic materials. ~ The relevant process observations that can be found have extremely rich technical connotations; «These materials are the development of liquid sealant formulations, the application of structural products and the ability to charge electricity, etc.). Regardless of raw material developer (chemical barrier), base / knife factory), or package design and manufacturer (semiconductor factory, package H 4 ^ ^ 〃 · ... i ... 'Understand these productions (including such as raw material development, lamination) , Etching, can be divided into the substrate J Jin layer, Φ ^, analysis and other technicians (substrate material and its process' further appropriate design throughout the field, using materials, especially the final process BGA, CSP and Flip chip structure The improvement of Yinghan's dry grip is Taiwan's expertise. / As shown in the first picture A or the first picture B, the feathers are in the knowing crystal; 4 In the Qichu buckling production line, there is a wafer substrate assembly The + + substrate needs to have two or one layers of assembled wafers (the structures are similar to each other), and the two pieces of components such as 16 are usually bonded with a thin film 17 and the product Α Α σ and generally IC (Integral

Circuit)晶片配置,該圖中之結構為上層晶片14以薄膜膠 17(fihn type ^ #16 ’且下層晶片16再以薄膠 6 M262839 膜17黏合基材18,並且在黏合後打上接線(一般為金 線),進-步加以灌封裝材料1〇及沾附焊錫19,以形成完 整的晶片封裝零件’然而薄膜膠17在貼附於基材Μ的過 程中極易產生空洞’且貼附之過程須使用較高精度之機 具,要貼附對位精準,因此成本較高,因此為適應產品特 性’生產流程安排常難以達成高效能操作晶片封裝機台之 目標。 口此為使生產之成本能夠降低,且能持續高效率運 作,有必要配合實際狀態研發新生產流程而以印刷黏膠方# 式將黏膠直接以印刷方式直接塗佈於晶圓上,再進入晶片 封裝生產線使得組農良率提高,因為在晶圓切割成晶片後 貼附於基材或其它層晶片時係為具有壓力之貼合方式使 得空洞被壓合消失;並且因為使用印刷方式上膠,對位精 度而而成本低成本與良率皆可提升,配合進一步架構各週 邊機具,並符合工業工程之流程排配原理,因此尋找出一 種更方便之技藝使得本創作能夠具有處理多方面各種之 狀況能力’因此研發出本創作來達成上述之需求。 _ 【新型内容】 本創作之主要目的在於提供一種晶片封裝之晶圓塗 膠構造(一),也就是新生產流程方法產生之構造,而且可 以成本低廉之架構及以配合相關之較方便專用週邊自動 機施行,可用於多種晶片封裝產品之應用場所,可以提供 低成本南品質之效果。 7 M262839 為了達成上述目的,本創作將習知之 方式塗上黏膠,避開習之薄膠膜的不易處 ® =刷 機來完成晶片封袭,更經濟地定= 有皿於實際應用之晶片封裝構造,盘 用價值。 /、自知杨比較更具實 本創作包含:晶圓,具有正面及背面,且該正 半導體電路層;及印刷膠層,位於該晶圓之正面;其^ 半導體電路層為複數個區塊所形成’且各該區塊間二 許切割間隔;其中各區塊具有無膠區。 /、令令 為了使f審查委員能更進-步瞭解本創作之特 技術内容’請參_下有關本創作之詳細朗,狹 ^内容僅提供參考與說日㈣,並非絲對本創作加以限制 【實施方式】 請參考以下所述為本創作運作原理,其中本創作為利 用黏膠印刷塗佈於晶圓之上原理,以方便在晶圓切割成晶 片後進行晶片貼合的生產流程,進一步以簡單的方式來^ 述本創作之流程即為:晶圓製成、印刷黏膠、裁切成晶片 後層疊於基材上、打連接線(一般為金線)、封裝,且印刷 對位減少累積對位誤差以助於對位精度,故晶片對基材而 言放置對位容易,加上週邊配合輔助機台,能節省成本地 定義出有益於實際應用之晶片封裝生產系統。 請參考第四圖為本創作實施之印刷塗膠步驟,其中晶 M262839 圓2〇之正面係具有一印刷工具34(如網板或鋼板),係可 用刮刀30對晶圓表面印刷黏膠32,以形成印刷膠層 24此為本創作之方法與習知技術之最大不同點。 明參考第二圖為本創作實施之晶圓2()之表面外觀說 明j般而δ,晶圓表面係具有複數個區塊20,並且每 區,26具有半導體電路,因此該晶圓2〇可被切割成複 數個曰:片’其中為使區塊26得到適當的保護不被切割刀 八1襄須叹置切割間隔28 ;且定位標記29可做為印刷 黏膠32蚪之定位;本創作之基本構造適用於多種半導體_ 產品之晶圓,使得本創作可以廣泛應用。 —本創作用於晶片封裝之晶圓黏合構造如第二圖所 不’因為切割晶圓20的方便考量,一般位於晶圓2〇正面 21之+導體電路層22上塗佈的印刷膠層24應該設置無 ^切f間隔28,及位於區塊26的中央區域或邊緣的接 線區,·此外,印刷膠層24亦可增設於晶圓2〇之背面], 以用於疊合其它晶片之用。 於曰=:第2為本創作較佳實施例之狀況,為-種用· =!之=黏合構造’其中構造包含:晶圓,具有 具有半導體電路層;及印刷膠層, ,π ^ Τ莓丰導體電路層為複數個區塊所, 形成,且各該區塊間具有容許厅 無膠區。本創作之重點為建構 /、中各£塊具有 可方便裁切成晶片後用二1特別特徵之晶圓構造’ 為明白顯示出本創作的次要特徵,本創作依其特性可 9 M262839 分為以下各種實施狀態 態或有膠狀態,以防止㈣中/切割間隔—般可為無膠狀 刀°】刀具影響塗膠精产·又 晶圓可具有定位標記 ” a _,又其中該 為人工^ 印刷塗膠工具之定位,亦可 马人工疋位不需要定位 印刷所形成,以方便其中該印刷膠層可為網板 員來施行·赤豆由兮商之現存設備或熟悉技術人 現存1及::二P刷膠層為鋼板印刷所形成,以方便 之實作專長技術應用;為求晶片之堆 二亦可有印刷膠層,以使該晶片可以 可為20.㈣,:進一 IS其中該印刷膠層厚度 艾進步该印刷膠層厚度較佳可為 30-50/zm(含40_此—常用標準值);為使現存設備刀具 可派上用場’其中該㈣間格所在之材料可容許鑽石刀切 開;為求接線(打金線)之方便,其中其中各該區塊之無膠 區具有接線區,且其中該接線區位於區塊的中央區域或邊 緣區域。 以一整條晶片(或晶粒)封裝生產配置的先後順序而 言,其中該印刷塗膠係位於封裝生產線之中段,該晶圓於 塗膠後,係先經過裁切之動作再經過夹持工具取起再壓合 於基材上,因此利用本創作構造有利於對位壓合及低成本 印刷’使生產成本得以降低,而大量生產時會使得良率提 幵明顯’尤其是一般具晶片封裝生產線之代工或製造廠 商,往往是24小時連續操作至一批次工件完成才停止產 線,因此產能改善效果顯著。 須知本創作具有以下之優點: M262839 ι·對位精準,良率提昇··此點係由晶圓印刷黏膠及壓 合於基材之上得到驗證,可減少定位誤差,進而提升取置 機之良率,使得經濟效果達成。 2·空洞減少,良率提昇··晶圓壓合時,本創作經高壓 減少空洞於黏膠中產生。 然 3·製程機器設備成本低··製程方便施行使設備 減少而易於取得。Circuit) chip configuration, the structure in the figure is that the upper wafer 14 is bonded to the substrate 18 with a thin film adhesive 17 (fihn type ^ # 16 ', and the lower wafer 16 is bonded to the substrate 18 with a thin adhesive 6 M262839 film 17, and is wired after bonding (general (Gold wire), further encapsulating the encapsulation material 10 and attaching the solder 19 to form a complete chip package part 'however, the film adhesive 17 is extremely easy to generate voids during the process of attaching to the substrate M' and attaching The process must use high-precision equipment, and it must be attached and aligned accurately, so the cost is high. Therefore, in order to adapt to the product characteristics, it is often difficult to arrange the production process to achieve the goal of efficiently operating the chip packaging machine. The cost can be reduced, and the operation can continue to be highly efficient. It is necessary to cooperate with the actual state of research and development of new production processes and print the adhesive directly on the wafer in a printing method #, and then enter the wafer packaging production line to make the group The yield rate is improved because the pressure is applied when the wafer is cut into wafers and attached to the substrate or other layers of wafers, so that the holes are pressed and disappeared; and because printing is used, Glue type, alignment accuracy and low cost and yield can be improved. With the further construction of peripheral equipment, and in line with the principle of process arrangement of industrial engineering, we have found a more convenient technique to enable this creation to be processed. A variety of conditions and capabilities' Therefore, this creation has been developed to meet the above-mentioned needs. _ [New content] The main purpose of this creation is to provide a wafer coating structure for wafer packaging (1), which is the production of a new production process method Structure, and it can be implemented with a low-cost structure and related more convenient dedicated peripheral automata, which can be used in a variety of chip packaging products applications, and can provide the effect of low-cost South quality. 7 M262839 In order to achieve the above purpose, this creation Apply the conventional method with adhesive, to avoid the difficult parts of the thin film of the ® ® = brush machine to complete the chip sealing, more economical = = there is a chip packaging structure in actual application, disk value. Zhi Yang is more practical. This includes: wafers, with front and back, and the positive semiconductor circuit layer. And a printed adhesive layer, which is located on the front side of the wafer; its semiconductor circuit layer is formed by a plurality of blocks', and there are two cutting intervals between each of the blocks; wherein each block has an adhesive-free area. / 、 令令 为To enable the review committee to further understand the special technical content of this creation 'Please refer to the detailed description of this creation below. The content is provided for reference and explanation only, not to limit this creation. [Implementation method] Please Refer to the following for the principle of this creative operation, which is based on the principle of using adhesive printing and coating on the wafer to facilitate the production process of wafer bonding after the wafer is cut into wafers. ^ The process of this creation is as follows: wafer making, printing adhesive, cutting into wafers and laminating on the substrate, connecting wires (generally gold wires), packaging, and printing alignment to reduce accumulated alignment errors In order to help the alignment accuracy, the wafer is easy to align to the substrate. With the peripheral auxiliary equipment, the cost-effective wafer packaging production system can be defined. Please refer to the fourth picture for the printing and gluing steps implemented in this creation. The front of the crystal M262839 circle 20 has a printing tool 34 (such as a stencil or steel plate), which can be used to print the adhesive 32 on the wafer surface with a scraper 30. Forming the printed adhesive layer 24 is the biggest difference between this method of creation and the conventional technique. The reference to the second figure is the description of the surface appearance of the wafer 2 () implemented by the author. The wafer surface has a plurality of blocks 20, and each block 26 has a semiconductor circuit. Therefore, the wafer 2 It can be cut into a plurality of pieces: "In order to prevent the block 26 from being properly protected by the cutting knife, the cutting interval is set at 28; and the positioning mark 29 can be used as the position of the printing adhesive 32"; The basic structure of the creation is suitable for a variety of semiconductor _ product wafers, making this creation widely applicable. —The wafer bonding structure used for chip packaging is not the same as the second picture. Because of the convenience of cutting the wafer 20, it is generally located on the front side of the wafer 20 + the printed circuit layer 22 coated on the conductor circuit layer 22 A non-cutting gap 28 should be provided, and a wiring area located at the central area or edge of the block 26. In addition, a printed adhesive layer 24 can also be added on the back of the wafer 20] for stacking other wafers. use. Yu Yue =: The second is the status of the preferred embodiment of the creation, which is-a kind of use = =! Of = bonding structure 'wherein the structure includes: a wafer with a semiconductor circuit layer; and a printing adhesive layer, π ^ Τ The berry Feng conductor circuit layer is formed by a plurality of blocks, and there is a glue-free area in the hall between each block. The focus of this creation is to construct a wafer structure with a special feature that can be easily cut into wafers after being cut into wafers. In order to clearly show the secondary characteristics of this creation, this creation can be 9 M262839 points according to its characteristics. It is the following various implementation states or glued state to prevent the centering / cutting interval-generally it can be a gel-free knife °] The tool affects the glue production and the wafer can have positioning marks "a _, and which should be Manual ^ The positioning of printing and coating tools can also be formed by manual positioning without printing, so that the printing adhesive layer can be performed by the screen board member. Red beans are provided by Xishang's existing equipment or skilled technicians. 1 And: The two P brushed adhesive layers are formed by steel printing to facilitate the practical application of technical expertise; in order to find the second stack of wafers, there can also be a printed adhesive layer so that the wafer can be 20. The thickness of the printing adhesive layer can be improved. The thickness of the printing adhesive layer can be preferably 30-50 / zm (including 40_this—commonly used standard value); in order to make existing equipment tools come in handy Material allows diamond knife to cut; The convenience of wiring (gold wire), in which the glue-free area of each block has a wiring area, and where the wiring area is located in the central or edge area of the block. It is produced in a whole chip (or die) package In terms of the order of configuration, the printing and gluing system is located in the middle of the packaging production line. After the wafer is coated, it is first cut and then picked up by the clamping tool and then pressed onto the substrate. The use of this creative structure is conducive to alignment and low-cost printing, 'reducing production costs, and large-scale production will make the yield increase significantly', especially the general foundry or manufacturer with a chip packaging production line, often 24 Hours of continuous operation until the completion of a batch of workpieces before stopping the production line, so the productivity improvement effect is significant. It should be noted that this creation has the following advantages: M262839 ι · Precise alignment, improved yield · This point is made by wafer printing adhesive and The lamination is verified on the substrate, which can reduce the positioning error, and then improve the yield of the placement machine, so that the economic effect is achieved. 2 · Reduced voids, improved yield · Wafer pressure , The creation of voids present in the viscose reduced by high pressure. 3. However, the low cost of the process equipment ·· convenient process and apparatus for reducing the purposes of making readily available.

4.製程簡化··可減少傳統貼膠膜設備之人力及工時 惟以上所述僅為本創作之較佳可行實_,非因此 本創作之翻範圍,故舉凡制本創作㈣書或圖式 所為之等效化學結構變化,均同料包含於摘作 内,以保障創作者之權益,於此陳明。 【圖式簡單說明】 第-Α圖:為習知之晶片封裝截面之一示意圖. 第一B圖:為習知之晶片封裝截面之二示意圖;4. Simplified manufacturing process. It can reduce the manpower and man-hours of traditional film-adhesive equipment. However, the above is only a good and feasible practice for this creation. It is not because of the scope of this creation. The equivalent chemical structure change of the formula is included in the excerpt with the same material to protect the rights and interests of the creator. [Brief description of the drawings] Figure -A: a schematic diagram of a conventional chip package cross-section. Figure B: a schematic diagram of a conventional chip package cross-section;

圓黏 第二圖:為本創作較佳實施例—種用於晶片封裝之晶 合構造示意圖; :二圖:為本創作使用之晶圓外觀示意圖;及 四圖:為本創作進行塗膠時之示意圖。 【主要元件符號說明】 封裂材料 1 接線 12 M262839 上層晶片 14 下層晶片 16 薄膠膜 17 基材 18 焊錫 19 晶圓 20 正面 21 半導體電路層 22 背面 23 印刷膠層 24 區塊 26 切割間隔 28 定位標記 29 刮刀 30 黏膠 32 印刷工具 34The second image of the circular stick: a preferred embodiment of this creation—a schematic diagram of a crystal structure used for chip packaging; the second image: a schematic diagram of the appearance of a wafer used in this creation; and the fourth image: when the glue is applied for this creation The schematic. [Description of main component symbols] Sealing material 1 Wiring 12 M262839 Upper wafer 14 Lower wafer 16 Thin adhesive film 17 Substrate 18 Solder 19 Wafer 20 Front surface 21 Semiconductor circuit layer 22 Back surface 23 Printing adhesive layer 24 Block 26 Cutting interval 28 Positioning Marking 29 Squeegee 30 Adhesive 32 Printing tools 34

1212

Claims (1)

M262839 九、申請專利範圍: 1、一種用於晶片封裝之晶圓塗膠構造( 包含: (),其構造 晶圓,具有正面及背面,且該正 層;及 ,、有+導體電路 印刷膠層,位於該 晶圓之正面; 其中該半導體電路層為複數個區塊所形成· 其中各區塊具有無膠區。 塗^、如申請專職圍第1項所述料晶片封卜曰鬥 、,構造(―)’其中該晶圓具有定位標記。x a曰圓 塗ml、如申請專職_ 1項所述用於晶片封h曰m ’、>構造(一),其中該印刷膠層為網板印刷所形^。日曰固 塗膠4構、=申請專利範圍第1項所述用於晶片封裝之曰圓 膠構M — ),其中該印刷膠層為鋼板印刷所形成之曰曰囫 塗膠L、、生如申請專利範圍第1項所述用於晶片封裳之曰圓 夕k(—) ’其中該印刷膠層厚度為10_150"m。曰曰 6、如申請專利範圍第1項述 塗膠構造( 貝R用於曰曰片封裝之晶圓 7 ) /、中各该區塊之無膠區具有接線區。 塗膠構範圍第1項所述用於晶片封裝之晶圓 域。 ,/、中该接線區位於區塊的中央或邊緣區 13M262839 9. Scope of patent application: 1. A wafer coating structure for wafer packaging (including: ()), the structured wafer has front and back surfaces, and the positive layer; and, + conductor circuit printing glue Layer, which is located on the front side of the wafer; where the semiconductor circuit layer is formed by a plurality of blocks, each of which has a glue-free area. Structure (―) 'where the wafer has a positioning mark. Xa is a round coating ml, used for wafer sealing as described in the application for full-time _ 1 m, and structure (a), wherein the printed adhesive layer is Screen printing ^. Japanese and Japanese solid coating 4 structure, = round plastic structure M —) for chip packaging described in the first patent application scope, wherein the printing adhesive layer is formed by steel plate printing The glue L, and the raw material are used for wafer sealing as described in Item 1 of the scope of the patent application, and the thickness of the printing glue layer is 10_150 " m. 6. As described in item 1 of the scope of the patent application, the glue-coated structure (being used for wafer packaging of wafers 7) /, the glue-free area of each of the blocks has a wiring area. Wafer area for wafer packaging as described in item 1 of the coated structure range. , /, The wiring area is located in the center or edge area of the block 13
TW093212582U 2004-08-06 2004-08-06 Wafer glue-coating structure for wafer packaging TWM262839U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424508B (en) * 2009-05-27 2014-01-21 Cofsip Technology Inc The process of soft film cladding sealant

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424508B (en) * 2009-05-27 2014-01-21 Cofsip Technology Inc The process of soft film cladding sealant

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