TWI841096B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a metal layer, a semiconductor layer, an insulating layer and a buffer layer. The substrate has a recess. The metal layer is located in the recess of the substrate. The semiconductor layer is located in the recess of the substrate and on the metal layer, in which the bottom of the semiconductor layer directly contacts the metal layer. The insulating layer is located in the recess of the substrate and on the semiconductor layer. The buffer layer extends from the position between the semiconductor layer and the metal layer, through the sidewall of the semiconductor layer, to the sidewall of the insulating layer, such that the buffer layer has an L-shaped cross section.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

In dynamic random access memory (DRAM), gate induced drain leakage (GIDL) is a serious and difficult to eliminate problem, because making the saturation current (I _D,SAT ) of the transistor better may cause gate induced drain leakage, and this leakage current will seriously affect the memory write-back. When the source/drain doping density becomes higher, the contact between the word line gate conductor and the drain will become larger, and the electric field between the two will increase, which will easily lead to a larger gate induced drain leakage current.

The traditional solution is to reduce the density of drain doping and then overlap the gate and drain, but this will affect the memory drive current and lead to poor write-back performance. Another traditional approach is to use a dual work function array structure in the word line, but the dual work function array structure will cause different resistivities due to different materials, causing time differences in signal transmission. Therefore, when the word line length becomes longer and the operating frequency of the gate voltage switch switching becomes higher, the dual work function array structure will easily experience resistance-capacitance delay (RC delay).

One technical aspect of the present disclosure is a semiconductor device.

According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a metal layer, a semiconductor layer, an isolation layer and a buffer layer. The substrate has a groove, and the metal layer is located in the groove of the substrate. The semiconductor layer is located in the groove of the substrate and on the metal layer, wherein the bottom of the semiconductor layer is in direct contact with the metal layer. The isolation layer is located in the groove of the substrate and on the semiconductor layer. The buffer layer extends from a position between the semiconductor layer and the metal layer through the side wall of the semiconductor layer to the side wall of the isolation layer, so that the buffer layer has an L-shaped cross-section.

In one embodiment of the present disclosure, the buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion, the bottom of the semiconductor layer is located in the horizontal portion of the buffer layer, and the vertical portion contacts the sidewall of the semiconductor layer and the sidewall of the isolation layer.

In one embodiment of the present disclosure, the horizontal portion of the buffer layer has an opening, and the bottom of the semiconductor layer is located in the opening of the horizontal portion.

In one embodiment of the present disclosure, the material of the metal layer includes tungsten.

In one embodiment of the present disclosure, the material of the semiconductor layer includes polysilicon.

In one embodiment of the present disclosure, the material of the isolation layer includes silicon nitride.

In one embodiment of the present disclosure, the semiconductor device further includes an insulating layer located in the groove of the substrate, between the substrate and the metal layer, and between the substrate and the buffer layer.

Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming an insulating layer in a groove of a substrate; forming a metal layer in the groove of the substrate; forming a buffer layer in the groove of the substrate and on the metal layer, wherein the buffer layer is formed along the top surfaces of the insulating layer and the metal layer; etching the buffer layer to form an opening so that it has an L-shaped cross-section; forming a semiconductor layer on the buffer layer and the metal layer so that the bottom of the semiconductor layer is located in the opening and directly contacts the metal layer; and forming an isolation layer on the semiconductor layer.

In one embodiment of the present disclosure, etching the buffer layer to form the opening includes forming two spacers opposite to each other in the groove and on the buffer layer; etching the buffer layer using the two spacers as masks to form the opening; and removing the two spacers.

In one embodiment of the present disclosure, etching the buffer layer to form the opening is performed using a dry etching method.

In the above-mentioned embodiment of the present disclosure, since the buffer layer has an opening, the bottom of the semiconductor layer can directly contact the metal layer below, thereby achieving the effect of directly short-circuiting the semiconductor layer and the metal layer. With such a configuration, although the semiconductor layer and the metal layer have different resistivities, they are electrically connected and conductive to each other, which can avoid the time difference in signal transmission between the two layers, thereby avoiding the resistance and capacitance delay of the dual work function array structure under high-frequency operation.

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. Referring to FIG. 1 , the semiconductor device 100 includes a substrate 110, a metal layer 120, a semiconductor layer 130, an isolation layer 140, and a buffer layer 150. The substrate 110 has a groove 112, and the metal layer 120 is located in the groove 112 of the substrate 110. The semiconductor layer 130 is located in the groove 112 of the substrate 110 and is located on the metal layer 120, wherein the bottom 132 of the semiconductor layer 130 is in direct contact with the metal layer 120. The isolation layer 140 is located in the groove 112 of the substrate 110 and is located on the semiconductor layer 130.

The buffer layer 150 extends from a position between the semiconductor layer 130 and the metal layer 120 through the sidewall 134 of the semiconductor layer 130 to the sidewall 142 of the isolation layer 140, so that the buffer layer 150 has an L-shaped cross-section. The buffer layer 150 has a horizontal portion 152 and a vertical portion 154 adjacent to the horizontal portion 152. The bottom 132 of the semiconductor layer 130 is located in the horizontal portion 152 of the buffer layer 150, and the vertical portion 154 contacts the sidewall 134 of the semiconductor layer 130 and the sidewall 142 of the isolation layer 140. The horizontal portion 152 of the buffer layer 150 has an opening 156, and the bottom 132 of the semiconductor layer 130 is located in the opening 156 of the horizontal portion 152. The semiconductor device 100 further includes an insulating layer 160 located in the groove 112 of the substrate 110 and between the substrate 110 and the metal layer 120 and between the substrate 110 and the buffer layer 150.

That is, in this embodiment, a portion of the vertical portion 154 of the buffer layer 150 is located between the semiconductor layer 130 and the insulating layer 160, and the remaining portion of the vertical portion 154 is located between the isolation layer 140 and the insulating layer 160, and the vertical portion 154 of the buffer layer 150 directly contacts the insulating layer 160. The horizontal portion 152 of the buffer layer 150 is located on the top surface of the metal layer 120 and directly contacts the top surface of the metal layer 120. The bottom 132 of the semiconductor layer passes through the opening 156 to directly contact and electrically connect with the metal layer 120, and the remaining portion of the semiconductor layer 130 is located above the horizontal portion 152 of the buffer layer 150. Therefore, as shown in FIG. 1 , the buffer layer 150 presents two L-shaped cross-sections, which are located at two sides of the groove 112 respectively.

In the present embodiment, the material of the substrate 110 includes silicon (Si), and the material of the metal layer 120 includes tungsten (W) or titanium nitride (TiN). The material of the semiconductor layer 130 includes polysilicon (Poly Silicon). The material of the isolation layer 140 includes silicon nitride (SiN). The material of the buffer layer 150 may be silicon dioxide (SiO ₂ ), but in some embodiments, the material of the buffer layer 150 may also use a high dielectric constant dielectric material (high κ dielectric, such as silicon nitride), but it is not intended to limit the present disclosure. The comparison benchmark for the so-called "high dielectric constant" here is silicon dioxide (κ=3.9), and the κ of silicon nitride is 7 to 8. The use of a high dielectric constant material for the buffer layer 150 can reduce the excessive drop in saturation current. At the same time, such a dual work function array structure can reduce the electric field on the drain side to avoid gate-induced drain leakage current.

Specifically, since the buffer layer 150 of the semiconductor device 100 has the opening 156, the bottom 132 of the semiconductor layer 130 is located in the opening 156 and the bottom 132 of the semiconductor layer 130 is in direct contact with the metal layer 120. In this way, a short circuit occurs between the semiconductor layer 130 and the metal layer 120. Because the bottom 132 of the semiconductor layer 130 is in direct contact with the metal layer 120, the two are electrically connected and conductive, thereby avoiding the time difference in signal transmission between the metal layer 120 and the semiconductor layer 130, thereby avoiding the resistance and capacitance delay caused by the traditional buffer layer separating the two layers of conductors with different resistivities when the dual work function array structure operates at high frequencies.

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated and should be described first. In the following description, a method for manufacturing the semiconductor device 100 will be described.

FIG. 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. First, in step S1, the method for manufacturing a semiconductor device includes forming an insulating layer in a groove of a substrate. Then, in step S2, a metal layer is formed in the groove of the substrate. Then, in step S3, a buffer layer is formed in the groove of the substrate and on the metal layer, wherein the buffer layer is formed along the top surface of the insulating layer and the metal layer. Then, in step S4, the buffer layer is etched to form an opening so that it has an L-shaped cross-section. Then in step S5, a semiconductor layer is formed on the buffer layer and the metal layer, so that the bottom of the semiconductor layer is located in the opening and directly contacts the metal layer. In the subsequent step S6, an isolation layer is formed on the semiconductor layer.

In some embodiments, the method for manufacturing a semiconductor device is not limited to the above-mentioned steps S1 to S6. For example, in some embodiments, other steps may be further included between two successive steps, or other steps may be further included before step S1, and other steps may be further included after step S5.

In the following description, each step of the method for manufacturing the semiconductor device will be described in detail.

FIG. 3 to FIG. 10 illustrate cross-sectional views of the intermediate process of the manufacturing method of the semiconductor device 100 of FIG. 1. Referring to FIG. 3 and FIG. 4, first, a groove 112 may be formed in the substrate 110. Then, an insulating layer 160 is formed in the groove 112 of the substrate 110. The insulating layer 160 may be formed by oxidizing the silicon in the silicon substrate 110 using a high temperature oxidation process, but is not limited to this method.

5 , after the insulating layer 160 is formed, the metal layer 120 may be formed in the groove 112 of the substrate 110. The metal layer 120 is located on the insulating layer 160. The metal layer 120 may be formed by physical vapor deposition (PVD), but is not limited to this method.

6 , after the metal layer 120 is formed, a buffer layer 150 is formed in the groove 112 of the substrate 110 and on the metal layer 120, wherein the buffer layer 150 is formed along the insulating layer 160 and the top surface of the metal layer 120. The buffer layer 150 formed at this time is a continuous coating layer, and the buffer layer 150 is also formed on the upper surface of the substrate 110 at the same time.

Referring to FIG. 7 , two spacers 170 are then formed in the groove 112 and on the buffer layer 150. The material of the spacer 170 may be silicon dioxide, but is not limited to this material. For example, the spacer 170 may also be a patterned photoresist or other material. The two spacers 170 may be formed by a patterning process so that there is a gap between them. The two spacers 170 may be used as masks in a subsequent etching step.

Referring to FIG. 8 , after the spacers 170 are formed, the buffer layer 150 is etched using the two spacers 170 as a mask to form an opening 156. The opening between the two spacers 170 allows a portion of the buffer layer 150 to be exposed, so that the exposed portion of the buffer layer 150 not covered by the two spacers 170 can be etched to form the opening 156. In addition, the buffer layer 150 above the substrate 110 outside the groove 112 can be removed by etching. In the present embodiment, the buffer layer 150 is etched to form the opening 156 using a dry etching method, but is not limited to this method.

9, after the opening 156 is formed, the two spacers 170 are removed. After the spacers 170 are removed, the buffer layer 150 having an L-shaped cross-section is left, and the horizontal portion 152 thereof has the opening 156. After the opening 156 of the buffer layer 150 is formed, a portion of the metal layer 120 is exposed.

Referring to FIG. 10 , after the spacer 170 (see FIG. 7 ) is removed, the semiconductor layer 130 is formed on the buffer layer 150 and the metal layer 120 in FIG. 8 , so that the bottom 132 of the semiconductor layer 130 is located in the opening 156 and directly contacts the metal layer 120. Since the opening 156 is etched out of the buffer layer 150 in the previous step, when the semiconductor layer 130 is formed, the semiconductor layer 130 can directly contact the metal layer 120 through the opening 156. This design allows the semiconductor layer 130 and the metal layer 120 having two different materials to be directly connected, and there will be no resistance and capacitance delay under high operating frequency due to the different resistivity of the two. By directly contacting the bottom 132 of the semiconductor layer 130 with the metal layer 120, the time difference of the signal transmission between the metal layer 120 and the semiconductor layer 130 can be avoided, thereby avoiding the resistance and capacitance delay caused by the traditional buffer layer separating the two layers of conductors with different resistivity under high-frequency operation of the dual-function array structure. The dual-function array structure of this embodiment can reduce the electric field size on the drain side to avoid the gate-induced drain leakage current.

Referring to FIG. 10 and FIG. 1, after the semiconductor layer 130 is formed, an isolation layer 140 is formed on the semiconductor layer 130. After this step is completed, the semiconductor device 100 of FIG. 1 is manufactured. By etching the buffer layer 150 to form an opening 156, the bottom 132 of the semiconductor layer 130 can directly contact the metal layer 120 through the opening 156, thereby avoiding the time difference of the signal being transmitted in the metal layer 120 and the semiconductor layer 130, thereby avoiding the resistance and capacitance delay caused by the traditional buffer layer separating the two layers of conductors with different resistivity under high frequency operation of the traditional dual work function array structure.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100:Semiconductor device

110: Substrate

112: Groove

120:Metal layer

130:Semiconductor layer

132: Bottom

134: Side wall

140: Isolation layer

142: Side wall

150: Buffer layer

152: Horizontal

154: Vertical part

156: Open

160: Insulation layer

170: Spacer

S1,S2,S3,S4,S5,S6: Steps

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the disclosure. FIG. 2 illustrates a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure. FIGS. 3 to 10 illustrate cross-sectional views of the method for manufacturing the semiconductor device of FIG. 1 at intermediate stages.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor devices

110: Substrate

112: Groove

120:Metal layer

130:Semiconductor layer

132: Bottom

134: Side wall

140: Isolation layer

142: Side wall

150: Buffer layer

152: Horizontal part

154: Vertical part

156: Open mouth

160: Insulation layer

Claims (10)

A semiconductor device comprises: a substrate, wherein the substrate has a groove; a metal layer, located in the groove of the substrate; a semiconductor layer, located in the groove of the substrate and on the metal layer, wherein a bottom of the semiconductor layer is in direct contact with the metal layer; an isolation layer, located in the groove of the substrate and on the semiconductor layer; and a buffer layer, having an opening located at the contact surface between the semiconductor layer and the metal layer, wherein the buffer layer extends from both sides of the opening respectively and is located on a side wall of the semiconductor layer and a side wall of the isolation layer, so that the buffer layer has an L-shaped cross-section. A semiconductor device as described in claim 1, wherein the buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion, the bottom of the semiconductor layer is located in the horizontal portion of the buffer layer, and the vertical portion contacts the side wall of the semiconductor layer and the side wall of the isolation layer. A semiconductor device as described in claim 2, wherein the bottom of the semiconductor layer is located in the opening of the horizontal portion. A semiconductor device as described in claim 1, wherein the material of the metal layer includes tungsten. A semiconductor device as described in claim 1, wherein the material of the semiconductor layer includes polysilicon. A semiconductor device as described in claim 1, wherein the material of the isolation layer includes silicon nitride. The semiconductor device as described in claim 1 further includes: an insulating layer located in the groove of the substrate, between the substrate and the metal layer, and between the substrate and the buffer layer. A method for manufacturing a semiconductor device includes: forming an insulating layer in a groove of a substrate; forming a metal layer in the groove of the substrate; forming a buffer layer in the groove of the substrate and on the metal layer, wherein the buffer layer is formed along the top surface of the insulating layer and the metal layer; etching the buffer layer to form an opening so that it has an L-shaped cross-section; forming a semiconductor layer on the buffer layer and the metal layer so that a bottom of the semiconductor layer is located in the opening and directly contacts the metal layer; and forming an isolation layer on the semiconductor layer. The method for manufacturing a semiconductor device as described in claim 8, wherein etching the buffer layer to form the opening comprises: forming two spacers opposite to each other in the groove and on the buffer layer; etching the buffer layer using the two spacers as masks to form the opening; and removing the two spacers. A method for manufacturing a semiconductor device as described in claim 8, wherein etching the buffer layer to form the opening is performed using a dry etching method.

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