CN117373996A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor structure and a method for fabricating the same, which relates to the technical field of semiconductors, wherein the semiconductor structure comprises a substrate, the substrate is provided with an active region, and the active region comprises a source region and a drain region; the grid electrode is arranged on the active region and provided with a first extending direction and a second extending direction; the source contact plug is connected with the source region, and the projection size of one side of the source contact plug, which is close to the grid electrode, in the second extending direction is smaller than the projection size of the source contact plug in the first extending direction; the drain contact plug is connected with the drain region, and the projection size of one side of the drain contact plug, which is close to the grid electrode, in the second extending direction is smaller than the projection size of the drain contact plug in the first extending direction. In the semiconductor structure and the manufacturing method thereof, the contact area of the source contact plug and the source region as well as the contact area of the drain contact plug and the drain region are increased, the contact resistance of the semiconductor structure is reduced, but the coupling capacitance between the source contact plug and the grid and between the drain contact plug and the grid is unchanged.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.

Background

In the semiconductor structure, in order to achieve conduction between semiconductor devices, the source and drain of the transistor are electrically connected to an external circuit through a source contact plug and a drain contact plug, respectively. As the size of the transistor is reduced, the contact areas of the source contact plug, the drain contact plug, and the transistor are reduced, resulting in an increase in the contact resistance of the transistor to a level that is difficult to support the current requirements of the transistor. However, increasing the contact areas of the source contact plug, the drain contact plug, and the transistor may increase the coupling capacitance between the source contact plug, the drain contact plug, and the transistor, reduce the response speed of the transistor, and cause delay of the transistor.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a semiconductor structure and a method of fabricating the same.

According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:

a substrate having an active region, the active region comprising a source region and a drain region;

the grid electrode is arranged on the active region and positioned between the source region and the drain region, and the grid electrode is provided with a first extending direction and a second extending direction on a plane parallel to the substrate, and the first extending direction is perpendicular to the second extending direction;

A source contact plug connected with the source region;

a drain contact plug connected to the drain region;

the projection size of one side of the source contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the source contact plug in the first extending direction, and/or the projection size of one side of the drain contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the drain contact plug in the first extending direction.

Wherein the source contact plug includes:

at least one first source contact portion, an included angle is formed between the extending direction of the first source contact portion and the second extending direction.

Wherein, the contained angle between the extending direction of the first source contact portion and the second extending direction is 90 °.

Wherein each of the first source contacts includes a first side adjacent to the gate, and a horizontal distance between the first side and the gate is the same.

Wherein each of the first source contacts includes a first side adjacent to the gate, the first side and the gate being at different horizontal distances.

Wherein the projection of the first source contact part on the substrate is in a strip shape or a trapezoid shape;

When the projection of the first source contact part on the substrate is trapezoid, the projection of the first side surface on the substrate corresponds to the short side of the trapezoid.

Wherein the source contact plug includes:

the included angle between the extending direction of the second source electrode contact part and the second extending direction is 90 degrees, the second source electrode contact part is arranged on one side, far away from the grid electrode, of the first source electrode contact part, and at least one first source electrode contact part is connected with at least one second source electrode contact part.

Wherein a projection of the second source contact onto the substrate is located within the source region.

And the projection part of the second source contact part on the substrate covers part of the top surface of the source region, and the other part covers the substrate adjacent to the source region.

The drain contact plug comprises at least one first drain contact portion, and at least one first drain contact portion and at least one first source contact portion are symmetrically arranged relative to the grid electrode.

The drain contact plug comprises at least one first drain contact portion and at least one second drain contact portion, wherein at least one first drain contact portion and at least one first source contact portion are symmetrically arranged relative to the grid electrode, and at least one second drain contact portion and at least one second source contact portion are symmetrically arranged relative to the grid electrode.

According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method of manufacturing a semiconductor structure comprising:

providing an initial structure, wherein the initial structure comprises a substrate and a grid electrode, the substrate comprises an active region, the active region comprises a source region and a drain region, the grid electrode is arranged on the active region and positioned between the source region and the drain region, the grid electrode has a first extending direction and a second extending direction on a plane parallel to the substrate, and the first extending direction is perpendicular to the second extending direction;

forming a source contact plug connected with the source region;

forming a drain contact plug connected with the drain region;

the projection size of one side of the source contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the source contact plug in the first extending direction, and/or the projection size of one side of the drain contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the drain contact plug in the first extending direction.

Wherein forming a source contact plug includes:

at least one first source contact portion is formed, and an included angle is formed between the extending direction of the first source contact portion and the second extending direction.

Wherein forming a drain contact plug includes:

and forming at least one second source contact part, wherein the second source contact part extends along the second extending direction, the second source contact part is arranged on one side of the first source contact part far away from the grid electrode, and at least one first source contact part is connected with at least one second source contact part.

Wherein forming a drain contact plug includes:

at least one first drain contact is formed, and an included angle is formed between the extending direction of the first drain contact and the second extending direction.

Wherein forming a drain contact plug includes:

and forming at least one second drain contact part, wherein the second drain contact part extends along the second extending direction, the second drain contact part is arranged on one side of the first drain contact part far away from the grid electrode, and at least one first drain contact part is connected with at least one second drain contact part.

In the semiconductor structure and the manufacturing method thereof provided by the embodiment of the disclosure, the contact area of the source contact plug and the source region and the contact area of the drain contact plug and the drain region are increased, the contact resistance of the semiconductor structure is reduced, but the coupling area between the source contact plug and the grid electrode and the coupling area between the drain contact plug and the grid electrode are unchanged, and adverse effects on the performance of the semiconductor caused by the increase of the coupling capacitance between the source contact plug and the grid electrode and the coupling capacitance between the drain contact plug and the grid electrode are avoided.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 2 is a cross-sectional view of section A-A of fig. 1.

Fig. 3 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 4 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 5 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 6 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 7 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 8 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 9 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 10 is a cross-sectional view of section B-B of fig. 9.

Fig. 11 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 12 is a top view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 13 is a cross-sectional view of section C-C of fig. 12.

Fig. 14 is a flowchart illustrating a method of fabricating a semiconductor structure, according to an example embodiment.

Fig. 15 is a schematic diagram of an initial structure shown according to an exemplary embodiment.

Fig. 16 is a top view illustrating formation of a first trench and a second trench according to an example embodiment.

Fig. 17 is a top view illustrating the formation of a first trench and a second trench according to an exemplary embodiment.

Reference numerals:

100. a substrate; 110. an active region; 111. a source region; 112. a drain region; 130. a gate; 140. an interlayer dielectric layer; 200. a source contact plug; 210. a first source contact; 211. a first side; 212. a second side; 220. a second source contact; 300. a drain contact plug; 310. a first drain contact; 311. a third side; 312. a fourth side; 320. a second drain contact; 400. an initial structure; 500. a first trench; 510. a first sub-trench; 520. a third sub-trench; 600. a second trench; 610. a second sub-trench; 620. a fourth sub-trench;

D1, a first extending direction; d2, a second extending direction; l1, a first distance; l2, a second distance; α1, a first included angle; α2, first included angle.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In a typical semiconductor structure, a transistor includes a gate electrode and source and drain electrodes located on both sides of the gate electrode, and the gate electrode of the transistor is used to control the on and off of a current path between the source and drain electrodes. The source and drain of the transistor are typically located in the substrate and are covered by a dielectric layer during the fabrication of the semiconductor structure. Therefore, the transistor needs to be additionally provided with a source contact plug and a drain contact plug, which penetrate through the dielectric layer and are respectively connected with the source and the drain of the transistor, so that the transistor is connected with an external circuit through the source contact plug and the drain contact plug.

Since the source and drain of a transistor are typically symmetrically disposed on both sides of the gate, in current semiconductor structures, source and drain contact plugs are typically also symmetrically disposed on both sides of the gate. As the size of the transistor is continuously reduced, the sizes of the source contact plug and the drain contact plug are also reduced, so that the contact resistances of the source contact plug, the drain contact plug and the transistor are increased, the current requirement of the transistor is difficult to support, and the performance of the semiconductor structure is deteriorated. However, increasing the size of the source contact plug and the drain contact plug may generate a larger coupling capacitance between the source contact plug and the gate and between the drain contact plug and the gate, and the coupling capacitance increases to affect the response speed of the transistor to the signal, which may cause a problem of response delay of the transistor.

The exemplary embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same, in which the dimensions of a source contact plug and a drain contact plug in a first extension direction are increased, the dimensions of the source contact plug and the drain contact plug in a second extension direction are smaller, one ends of the source contact plug and the drain contact plug, which are smaller in dimensions, are disposed toward a gate electrode, the contact area of the source contact plug and a source region and the contact area of the drain contact plug and a drain region are increased, and the contact resistance of the semiconductor structure is reduced, but the coupling area between the source contact plug and the gate electrode and the coupling area between the drain contact plug and the gate electrode are unchanged, thereby avoiding adverse effects on the semiconductor performance due to the coupling capacitance of the source contact plug and the gate electrode, and the drain contact plug and the gate electrode.

In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, as shown in fig. 1 and 2, the semiconductor structure includes a substrate 100, the substrate 100 having an active region 110, the active region 110 including a source region 111 and a drain region 112. The semiconductor structure further includes a gate 130, a source contact plug 200, and a drain contact plug 300, the gate 130 being disposed on the active region 110 between the source region 111 and the drain region 112, the gate 130 having a first extension direction D1 and a second extension direction D2 on a plane parallel to the substrate 100, the first extension direction D1 being perpendicular to the second extension direction D2. The source contact plug 200 is connected to the source region 111, and a projection size of a side of the source contact plug 200, which is close to the gate 130, in the second extension direction D2 is smaller than a projection size of the source contact plug 200 in the first extension direction D1. Drain contact plug 300 is connected to drain region 112, and the projected size of the side of drain contact plug 300 adjacent to gate 130 in second extension direction D2 is smaller than the projected size of drain contact plug 300 in the first extension direction.

As shown in fig. 1 and 2, the gate 130 is disposed on the active region 110, the active region 111 is disposed in the active region 110 on one side of the gate 130, the top surface of the active region 110 extends downward, and the drain region 112 is disposed in the active region 110 on the other side of the gate 130, and the top surface of the active region 110 extends downward. In a plane parallel to the substrate 100, the gate 130 extends in a first extension direction D1 and a second extension direction D2, and the gate 130 passes through the active region 110 in the second extension direction D2.

In this embodiment, source contact plug 200 is disposed on source region 111 in contact with source region 111, drain contact plug 300 is disposed on drain region 112 in contact with drain region 112, and source contact plug 200 and drain contact plug 300 may be disposed symmetrically or asymmetrically with respect to gate 130. As shown in fig. 1 and 2, the side of the source contact plug 200 having a smaller projection is disposed toward the gate 130, and the coupling area between the source contact plug 200 and the gate 130 is smaller. The side of the drain contact plug 300, on which the projection is smaller, is disposed toward the gate electrode 130, and the coupling area between the drain contact plug 300 and the gate electrode 130 is smaller.

The semiconductor structure of the present embodiment increases the dimensions of the source contact plug 200 and the drain contact plug 300 in the first extending direction D1, and respectively sets the side of the source contact plug 200 and the drain contact plug 300 with smaller projection dimensions toward the gate 130, so as to avoid increasing the coupling area between the source contact plug 200 and the gate 130 and the coupling area between the drain contact plug 300 and the gate 130, thereby reducing the contact resistance of the semiconductor structure, and ensuring that the coupling capacitance between the source contact plug 200 and the gate 130 and between the drain contact plug 300 and the gate 130 is not increased, and ensuring that the semiconductor structure has good response speed.

In this embodiment, as shown in fig. 1 to 7, the source contact plug 200 includes at least one first source contact 210, and a first included angle α1 is formed between an extension direction of the first source contact 210 and a second extension direction. The first included angle α1 may be an acute angle, a right angle, or an obtuse angle. The first angle α1 is, for example, 30 °, 45 °, 60 °, 90 °, 120 °, 135 °, or 150 °.

The coupling capacitance between the source contact plug 200 and the gate 130 and the coupling area between the source contact plug 200 and the gate 130 are positively correlated, and the coupling area between the source contact plug 200 and the gate 130 is the projected area formed on the gate 130 on the side of the gate 130 where the source contact plug 200 is close to. In this embodiment, by transferring the first included angle α1, the projected area formed on the gate 130 at the side of the gate 130 close to the source contact plug 200 is smaller than the actual area at the side of the gate 130 close to the source contact plug 200, so that the coupling capacitance between the source contact plug 200 and the gate 130 can be reduced, and the delay effect of the coupling capacitance between the source contact plug 200 and the gate 130 on the semiconductor structure can be reduced.

As shown in fig. 1-7, in some embodiments, the source contact plug 200 includes more than two first source contacts 210, for example, the source contact plug 200 may include two first source contacts 210, three first source contacts 210, five first source contacts 210, or six first source contacts 210. The source contact plug 200 is formed by connecting two or more first source contact portions 210 in parallel, and the first source contact portions 210 are connected in parallel, so that the total resistance of the source contact plug 200 can be reduced, and the operating current of the semiconductor structure can be increased.

According to an exemplary embodiment, as shown in fig. 1 to 7, the drain contact plug 300 includes at least one first drain contact portion 310, and the extending direction of the first drain contact portion 310 has a second included angle α2 with the second extending direction D2. The second included angle α2 may be an acute angle, a right angle, or an obtuse angle. Illustratively, the second included angle α2 may be 30 °, 45 °, 60 °, 90 °, 120 °, 135 °, or 150 °. The first angle α1 and the second angle α2 may be the same or different.

Through the transfer of the second included angle α2, the projected area formed on the gate 130 at the side of the gate 130 close to the drain contact plug 300 is smaller than the actual area at the side of the gate 130 close to the drain contact plug 300, so that the coupling capacitance between the drain contact plug 300 and the gate 130 can be reduced, and the delay effect of the coupling capacitance between the drain contact plug 300 and the gate 130 on the semiconductor structure can be reduced.

As shown in fig. 1 to 7, the drain contact plug 300 includes more than two first drain contacts 310, for example, the drain contact plug 300 may include two first drain contacts 310, three first drain contacts 310, five first drain contacts 310, or six first drain contacts 310. In the semiconductor structure of this embodiment, the drain contact plug 300 is formed by the first drain contact portions 310 arranged in parallel, and the first drain contact portions 310 are connected in parallel, so that the total resistance of the drain contact plug 300 can be reduced, which is beneficial to improving the working current of the semiconductor structure.

In the present embodiment, as shown in fig. 1 to 7, the number of the first source contact portions 210 of the source contact plug 200 is the same as the number of the first drain contact portions 310 of the drain contact plug 300, for example, the source contact plug 200 includes three first source contact portions 210, and the drain contact plug 300 includes three first drain contact portions 310; alternatively, the source contact plug 200 includes four first source contact portions 210, and the drain contact plug 300 includes four first drain contact portions 310. Moreover, the first included angle α1 and the second included angle α2 are equal, for example, the first included angle α1 and the second included angle α2 may be 15 °, 25 °, 55 ° or 90 °. The at least one first drain contact 310 and the at least one first source contact 210 are symmetrically disposed with respect to the gate 130.

It is understood that in other embodiments, the number of the first source contact portions 210 of the source contact plug 200 and the number of the first drain contact portions 310 of the drain contact plug 300 may be different, and the first included angle α1 and the second included angle α2 may be different. For example, the source contact plug 200 includes four first source contacts 210, and the drain contact plug 300 includes three first drain contacts 310, and for another example, the first angle α1 is 60 °, and the second angle α2 is 45 °.

In some examples, referring to fig. 3-7, the angle between the extension direction of the first source contact 210 and the second extension direction D2 is 90 °. That is, the first source contact 210 extends along the first extending direction D1, the first source contact 210 is disposed perpendicular to the gate 130 at one side of the gate 130, and the first included angle α1 is equal to 90 °.

Each first source contact 210 includes a first side 211 proximate to the gate 130 and a second side 212 distal from the gate 130. The projection of each first source contact 210 formed on the substrate 100 is located within the source region 111. As shown in fig. 3, in some examples, a projection of the second side 212 formed on the substrate 100 is located within the source region 111. In other examples, as shown in fig. 4, the projection of the second side 212 formed on the substrate 100 is flush with the edge of the source region 111 remote from the gate 130.

As shown in fig. 3 to 7, the projected size of the first side surface 211 in the second extension direction D2 is smaller than the projected size of the first source contact 210 in the first extension direction D1, increasing the contact resistance of the first source contact 210 and the source region 111, and decreasing the contact resistance of the source contact plug 200 and the gate 130, so as to increase the operating current of the semiconductor structure.

In some examples, as shown in fig. 3-6, the projection of the first source contact 210 on the substrate 100 is in the shape of a bar.

In other examples, as shown in fig. 7, the projection of the first source contact 210 on the substrate 100 is trapezoidal, the projection of the first side 211 on the substrate 100 corresponds to a short side of the trapezoid, and the projection of the second side 212 on the substrate 100 corresponds to a long side of the trapezoid. The projection of the first source contact 210 on the substrate 100 is trapezoidal, and the size of the first source contact 210 gradually increases along the direction away from the gate 130, so that the contact area between the first source contact 210 and the source region 111 can be further increased, the contact resistance between the source contact plug 200 and the source region 111 can be reduced, and the coupling capacitance between the source contact plug 200 and the gate 130 can not be increased.

In some examples, as shown in fig. 1, 3, 4, and 7, when the source contact plug 200 includes a plurality of first source contacts 210, horizontal distances between the first sides 211 of the plurality of first source contacts 210 and the gate 130 are the same. The source contact plug 200 includes four first source contacts 210, each of which has a horizontal distance L1 from the gate 130 to the first source contact 210, and each of which has an equal projected area on the substrate 100.

In some examples, as shown in fig. 5 and 6, the horizontal distances between the first sides 211 of the plurality of first source contacts 210 and the gate 130 are different, and the horizontal distance between one or more of the plurality of first source contacts 210 and the gate 130 is greater than the horizontal distance between the remaining first source contacts 210 and the gate 130 to reduce the coupling capacitance between a portion of the first source contacts 210 and the gate 130.

The present example is described with the source contact plug 200 including four first source contacts 210. As shown in fig. 5 and 6, the horizontal distance between two first source contacts 210 of the four first source contacts 210 and the gate 130 is a first distance L1, and the horizontal distance between the other two first source contacts 210 and the gate 130 is a second distance L2, and the first distance and the second distance L2 are different. In some examples, as shown in fig. 5, the projected area of each first source contact 210 formed on the substrate 100 is the same. In other examples, as shown in fig. 6, the projected area of each first source contact 210 formed on the substrate 100 is different to fully utilize the top surface area of the source region 111 and increase the contact area of a portion of the first source contact 210 and the source region 111.

In some embodiments, as shown with reference to fig. 3-7, the angle between the extension direction of the first drain contact 310 and the second extension direction D2 is 90 °. That is, the first drain contact 310 extends along the first extending direction D1, the first drain contact 310 is disposed perpendicular to the gate 130 at the other side of the gate 130, and the second included angle α2 is equal to 90 °.

Referring to fig. 3-7, each first drain contact 310 includes a third side 311 adjacent to the gate 130 and a fourth side 312 remote from the gate 130. A projection of each first drain contact 310 formed on substrate 100 is located within drain region 112. Wherein the projection of fourth side 312 onto substrate 100 is located within drain region 112 or the projection of fourth side 312 onto substrate 100 is flush with the edge of drain region 112 away from gate 130.

The projected size of the third side surface 311 in the second extending direction D2 is smaller than the projected size of the first drain contact portion 310 in the first extending direction D1, which increases the size of the first drain contact portion 310 in the first extending direction D1, increases the contact resistance between the first drain contact portion 310 and the drain region 112, and further decreases the contact resistance between the drain contact plug 300 and the gate 130, so as to increase the operating current of the semiconductor structure.

In some examples, as shown in fig. 3-6, the projection of the first drain contact 310 on the substrate 100 is in the shape of a bar.

In other examples, as shown in fig. 7, the projection of the first drain contact 310 on the substrate 100 is trapezoidal, the projection of the third side 311 on the substrate 100 corresponds to the short side of the trapezoid, and the projection of the fourth side 312 on the substrate 100 corresponds to the long side of the trapezoid. When the drain contact plug 300 includes the plurality of first drain contacts 310, the horizontal distances between the third sides 311 of the plurality of first drain contacts 310 and the gate 130 may be the same or different, and the projected areas of the plurality of first drain contacts 310 formed on the substrate 100 may be the same or different.

In the semiconductor structure of this embodiment, the drain contact plug 300 includes a plurality of first drain contact portions 310, and the third side 311 with the smaller area of the first drain contact portions 310 is disposed towards the gate 130, so as to increase the contact area between the drain contact plug 300 and the drain region 112, reduce the contact resistance of the semiconductor structure, ensure that the operating current of the semiconductor structure can meet the operating requirement during the operation of the semiconductor structure, and avoid the increase of the coupling capacitance caused by the increase of the coupling area between the drain contact plug 300 and the gate 130, and reduce the delay effect of the coupling capacitance between the drain contact plug 300 and the gate 130 on the semiconductor structure.

In an exemplary embodiment of the present disclosure, as shown in fig. 8 to 13, a semiconductor structure is provided, and the semiconductor structure in this embodiment includes all the structures of the semiconductor structure in the above-described embodiment. The difference between this embodiment and the above-described embodiment is that, in this embodiment, as shown in fig. 8, 9, 11, and 12, the source contact plug 200 includes at least one first source contact 210 and at least one second source contact 220. The first extending direction of each first source contact 210 and the second extending direction D2 have a first included angle α1 therebetween, and the first included angle α1 may be an acute angle, a right angle, or an obtuse angle. The first source contact 210 includes a first side 211 proximate to the gate 130 and a second side 212 distal from the gate 130. The second source contact 220 extends along the second extending direction D2, the second source contact 220 is disposed on a side of the first source contact 210 away from the gate 130, and at least one first source contact 210 is connected to at least one second source contact 220. For example, the source contact plug 200 may include a first source contact 210 and a second source contact 220, the second side 212 of the first source contact 210 being connected to the second source contact 220. Alternatively, the source contact plug 200 may include six first source contacts 210, two second source contacts 220, wherein the second sides 212 of three first source contacts 210 are connected to one of the second source contacts 220, and the second sides 212 of the other three first source contacts 210 are connected to the other second source contact 220.

When the source contact plug 200 includes a plurality of first source contact portions 210, the plurality of first source contact portions 210 are disposed at intervals in the second extending direction D2. As shown in fig. 8, 9, 11, and 12, the source contact plug 200 includes four first source contact portions 210 and one second source contact portion 220, and an angle between an extending direction of the first source contact portion 210 and the second extending direction D2 is 90 °, that is, the first source contact portion 210 extends along the first extending direction D1, and the first angle α1 is equal to 90 °. The four first source contact portions 210 are disposed at intervals along the second extending direction D2, and the second side 212 of each first source contact portion 210 is connected to the second source contact portion 220.

In this embodiment, the projection of the first source contact 210 on the substrate 100 is stripe-shaped or trapezoid-shaped. As shown in fig. 8, 9, and 11, the projection of the first source contact 210 on the substrate 100 is stripe-shaped. As shown in fig. 12, the projection of the first source contact 210 on the substrate 100 is trapezoidal, the projection of the first side 211 on the substrate 100 corresponds to the short side of the trapezoid, the projection of the second side 212 on the substrate 100 corresponds to the long side of the trapezoid, and the second side 212 is connected to the second source contact 220.

In some examples, as shown in fig. 8, 9, and 11, a projection of the second source contact 220 formed on the substrate 100 is located within the source region 111. For example, referring to fig. 8, a projection of the second source contact 220 formed on the substrate 100 away from the side of the gate 130 is located within the source region 111. Or, referring to fig. 9, 10 and 11, the projection of the side of the second source contact 220 away from the gate 130 on the substrate 100 coincides with the edge of the source region 111 away from the gate 130, so as to fully utilize the top surface area of the source region 111, so that the contact area between the second source contact 220 and the source region 111 is larger, which is helpful to further reduce the contact area between the source contact plug 200 and the source region 111, increase the working current in the working state of the semiconductor structure, and ensure that the working current of the semiconductor structure can meet the working requirements of the semiconductor structure.

In other examples, as shown in fig. 12, a projected portion of the second source contact 220 on the substrate 100 covers a portion of the top surface of the source region 111, and another portion covers the substrate 100 adjacent to the source region 111. For example, as shown in fig. 13, a portion of the structure of the second source contact 220 extends into the substrate 100 in contact with a portion of the sidewall of the source region 111. The contact area between the second source contact 220 and the source region 111 includes the contact area between the second source contact 220 and the top surface of the source region 111 and the contact area between the second source contact 220 and the sidewall of the source region 111, and in this embodiment, the available area of the source region 111 is fully utilized to maximize the total contact area between the source contact plug 200 and the source region 111, minimize the contact resistance between the source contact plug 200 and the source region 111, and the total contact area between the source contact plug 200 and the source region 111 does not increase the coupling capacitance between the source contact plug 200 and the gate 130.

As shown in fig. 8 to 13, in the present embodiment, the drain contact plug 300 includes at least one first drain contact portion 310 and at least one second drain contact portion 320. The first drain contact 310 has a second included angle α2 between the extending direction of the first drain contact 310 and the second extending direction D2, the first drain contact 310 includes a third side 311 close to the gate 130 and a fourth side 312 far away from the gate 130, the second drain contact 320 extends along the second extending direction D2, the second drain contact 320 is disposed on a side of the first drain contact 310 far away from the gate 130, and at least one first drain contact 310 is connected to at least one second drain contact 320.

In some embodiments, the first angle α1 and the second angle α2 are equal, and the source contact plug 200 and the drain contact plug 300 are symmetrically disposed with respect to the gate 130. As shown in fig. 8-13, at least one first drain contact 310 and at least one first source contact 210 are symmetrically disposed with respect to the gate 130, and at least one second drain contact 320 and at least one second source contact 220 are symmetrically disposed with respect to the gate 130. It is understood that in other embodiments, the source contact plug 200 and the drain contact plug 300 may be asymmetrically disposed.

In the present embodiment, as shown in fig. 8 to 13, the angle between the extending direction of each first drain contact portion 310 and the second extending direction D2 is 90 °, that is, the first drain contact portion 310 extends along the first extending direction D1, and the second angle α2 is equal to 90 °. When the drain contact plug 300 includes a plurality of first drain contact portions 310, the plurality of first drain contact portions 310 are disposed at intervals in the second extending direction D2. As shown in fig. 8, 9, 11, and 12, the drain contact plug 300 includes four first drain contact portions 310 and one second drain contact portion 320, the four first drain contact portions 310 being disposed apart in the second extending direction D2, and a fourth side 312 of each first drain contact portion 310 being connected to the second drain contact portion 320.

In this embodiment, the projection of the first drain contact 310 on the substrate 100 is stripe-shaped or trapezoid-shaped. As shown in fig. 8, 9 and 12, the projection of the first drain contact 310 on the substrate 100 is stripe-shaped. As shown in fig. 11, when the projection of the first drain contact 310 on the substrate 100 is trapezoidal, the projection of the third side 311 on the substrate 100 corresponds to the short side of the trapezoid, the projection of the fourth side 312 on the substrate 100 corresponds to the long side of the trapezoid, and the fourth side 312 is connected with the second drain contact 320, so that the third side 311 with the nearest area of the first drain contact 310 is disposed towards the gate 130, and the coupling capacitance between the first drain contact 310 and the gate 130 is reduced, and the coupling capacitance between the drain contact plug 300 and the gate 130 is further reduced.

In some examples, as shown in fig. 8, 9, and 11, a projection of second drain contact 320 formed on substrate 100 is located within drain region 112. The projection of the side of second drain contact 320 away from gate 130 onto substrate 100 coincides with the edge of drain region 112 away from gate 130. In other examples, as shown in fig. 12 and 13, a projection of the second drain contact 320 on the substrate 100 covers a portion of the top surface of the source region 111, another portion covers the substrate 100 adjacent to the source region 111, and a portion of the structure of the second drain contact 320 extends into the substrate 100 and is in contact connection with a portion of the sidewall of the drain region 112.

The layout of the source contact plug 200 and the drain contact plug 300 of the semiconductor structure of this embodiment is more reasonable, and increases the contact area between the source contact plug 200 and the source region 111 and the contact area between the drain contact plug 300 and the drain region 112, so that the coupling capacitance between the source contact plug 200, the drain contact plug 300 and the gate 130 is kept unchanged or reduced, and the semiconductor structure has smaller contact resistance, and the semiconductor structure is less affected by the coupling capacitance, so that the working performance of the semiconductor structure can be improved, the delay problem of the semiconductor structure can be improved, and the response speed of the semiconductor structure can be improved.

According to an exemplary embodiment, this embodiment is an explanation of the above embodiment, and the semiconductor structure in this embodiment includes all the structures of the semiconductor structure in the above embodiment. As shown in fig. 2, 10 and 13, the semiconductor structure of the present embodiment further includes an interlayer dielectric layer 140, where the interlayer dielectric layer 140 covers the substrate 100 and the gate 130, and the source contact plug 200 is connected to the source region through the interlayer dielectric layer 140, and the drain contact plug 300 is connected to the drain region 112 through the interlayer dielectric layer 140.

The semiconductor structure of the present embodiment can be applied to a dynamic random access memory (Dynamic Random Access Memory, DRAM). However, it is also applicable to Static Random-Access Memory (SRAM), flash EPROM (flash EPROM), ferroelectric Memory (Ferroelectric Random-Access Memory, FRAM), magnetic Random-Access Memory (MRAM), phase change Random-Access Memory (PRAM), and the like.

In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, as shown in fig. 14, fig. 14 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, and fig. 15 to 17 are schematic views of various stages of the method for fabricating a semiconductor structure, and the method for fabricating a semiconductor structure is described below according to fig. 15 to 17 and with reference to fig. 1 to 13.

The semiconductor structure is not limited in this embodiment, and a Dynamic Random Access Memory (DRAM) will be described as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.

As shown in fig. 14, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

step S110: providing an initial structure, wherein the initial structure comprises a substrate and a grid electrode, the substrate comprises an active region, the active region comprises a source region and a drain region, the grid electrode is arranged on the active region and is positioned between the source region and the drain region, the grid electrode is provided with a first extending direction and a second extending direction on a plane parallel to the substrate, and the first extending direction is perpendicular to the second extending direction.

As shown in fig. 15, the initial structure 400 includes the substrate 100. In this embodiment, the substrate 100 may be a semiconductor substrate, which may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-on-Insulator (GOI) substrate, or the like.

As shown in fig. 15, the substrate 100 includes an active region 110. The gate 130 has a first extending direction D1 and a second extending direction D2 on a plane parallel to the substrate 100, the first extending direction D1 being perpendicular to the second extending direction D2, and the gate 130 passes through the active region 110 in the second extending direction D2. The active region 110 includes a source region 111 and a drain region 112, and the source region 111 and the drain region 112 are disposed at both sides of the gate electrode 130 in the first extension direction D1.

As shown in fig. 15, the initial structure 400 of the present embodiment further includes an interlayer dielectric layer 140, where the interlayer dielectric layer 140 covers the gate 130 and the substrate 100, and the top surface of the interlayer dielectric layer 140 is a plane, and the top surface of the interlayer dielectric layer 140 is higher than the top surface of the gate 130. In this embodiment, the material of the interlayer dielectric layer 140 may include silicon oxide, silicon nitride or silicon oxynitride.

Step S120: and forming a source contact plug connected with the source region.

Step S130: and forming a drain electrode contact plug which is connected with the drain region.

In this embodiment, the source contact plug and the drain contact plug may be formed by the following implementations:

as shown in fig. 16 or 17, referring to fig. 15, a portion of interlayer dielectric layer 140 is removed, forming a first trench 500 and a second trench 600, first trench 500 being located above source region 111 and exposing a portion of the top surface of source region 111, and second trench 600 being located above drain region 112 and exposing a portion of the top surface of drain region 112.

Then, a conductive material may be deposited by any one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition process (Physical Vapor Deposition, PVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), or sputtering (sputtering), and the conductive material fills the first trench 500 to form the source contact plug 200, and the conductive material fills the second trench 600 to form the drain contact plug 300. The material of the source contact plug 200 may include at least one of Titanium (or an alloy thereof), tantalum (or an alloy thereof), tungsten (or an alloy thereof), and the material of the drain contact plug 300 is the same as the material of the source contact plug 200.

Referring to fig. 1 to 13, the source contact plug 200 is connected to the source region 111, and a projection size of a side of the source contact plug 200 near the gate 130 in the second extension direction D2 is smaller than a projection size of the source contact plug 200 in the first extension direction D1. Drain contact plug 300 is connected to drain region 112, and the projected size of the side of drain contact plug 300 adjacent to gate 130 in second extension direction D2 is smaller than the projected size of drain contact plug 300 in the first extension direction.

The semiconductor structure formed by the embodiment reduces the coupling capacitance between the source contact plug and/or the drain contact plug and the grid electrode, and can improve the response speed of the semiconductor structure.

According to an exemplary embodiment, this embodiment includes all the steps of the foregoing embodiment, and is different from the foregoing embodiment in that in the process of etching and removing a portion of the interlayer dielectric layer 140, as shown in fig. 16, at least one first sub-trench 510 is formed above the source region 111, and a first included angle α1 is formed between an extension direction of each first sub-trench 510 and the second extension direction D2, and at least one first sub-trench 510 forms the first trench 500. Meanwhile, at least one second sub-trench 610 is formed above drain region 112, each second sub-trench 610 having a second angle α2 between the extending direction and second extending direction D2, at least one second sub-trench 610 forming second trench 600.

Referring to fig. 1 to 7, the conductive material is filled into the first sub-trenches 510 to form first source contacts 210 in each of the first sub-trenches 510, an extending direction of the first source contacts 210 has a first angle α1 with a second extending direction D2, and at least one of the first source contacts 210 constitutes a source contact plug 200.

Meanwhile, referring to fig. 1 to 7, a conductive material is filled into the second sub-trenches 610, and a first drain contact portion 310 is correspondingly formed in each of the second sub-trenches 610, and a second angle α2 is formed between an extension direction of the first drain contact portion 310 and the second extension direction D2, and at least one of the first drain contact portions 310 constitutes a drain contact plug 300.

According to an exemplary embodiment, the present embodiment includes all the steps of the above embodiment, and the present embodiment is different from the above embodiment in that the present embodiment further includes the steps of:

as shown in fig. 17, a portion of interlayer dielectric layer 140 is etched away, at least one third sub-trench 520 is formed over source region 111, and at least one fourth sub-trench 620 is formed over drain region 112, each third sub-trench 520 extending in second extension direction D2 and exposing a portion of the top surface of source region 111, and fourth sub-trench 620 extending in second extension direction D2 and exposing a portion of the top surface of drain region 112. The at least one first sub-trench 510 and the at least one third sub-trench 520 form a first trench 500, and the at least one second sub-trench 610 and the at least one fourth sub-trench 620 form a second trench 600.

As shown in fig. 17, at least one third sub-trench 520 is provided at a side of the at least one first sub-trench 510 remote from the gate 130, and the at least one first sub-trench 510 communicates through the at least one third sub-trench 520. At least one fourth sub-trench 620 is disposed at a side of the at least one second sub-trench 610 remote from the gate 130, and the at least one second sub-trench 610 communicates through the at least one fourth sub-trench 620.

In this embodiment, referring to fig. 8-13, in the process of depositing the conductive material, a portion of the conductive material fills the third sub-trench 520 to form the second source contact 220, the second source contact 220 extends along the second extending direction D2, the second source contact 220 is disposed on a side of the first source contact 210 away from the gate 130, and at least one first source contact 210 is connected to at least one second source contact 220. A portion of the conductive material is filled into the fourth sub-trench 620 to form a second drain contact 320, the second drain contact 320 extends along the second extending direction D2, the second drain contact 320 is disposed at a side of the first drain contact 310 away from the gate 130, and at least one first drain contact 310 is connected to at least one second drain contact 320.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (16)

1. A semiconductor structure, the semiconductor structure comprising:

a substrate having an active region, the active region comprising a source region and a drain region;

the grid electrode is arranged on the active region and positioned between the source region and the drain region, and the grid electrode is provided with a first extending direction and a second extending direction on a plane parallel to the substrate, and the first extending direction is perpendicular to the second extending direction;

a source contact plug connected with the source region;

a drain contact plug connected to the drain region;

the projection size of one side of the source contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the source contact plug in the first extending direction, and/or the projection size of one side of the drain contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the drain contact plug in the first extending direction.

2. The semiconductor structure of claim 1, wherein the source contact plug comprises:

at least one first source contact portion, an included angle is formed between the extending direction of the first source contact portion and the second extending direction.

3. The semiconductor structure of claim 2, wherein an angle between the extension direction of the first source contact and the second extension direction is 90 °.

4. The semiconductor structure of claim 3, wherein each of the first source contacts includes a first side proximate the gate, a horizontal distance between the first side and the gate being the same.

5. The semiconductor structure of claim 3, wherein each of the first source contacts includes a first side proximate the gate, a horizontal distance between the first side and the gate being different.

6. The semiconductor structure of claim 4 or 5, wherein a projection of the first source contact onto the substrate is stripe-shaped or trapezoid-shaped;

when the projection of the first source contact part on the substrate is trapezoid, the projection of the first side surface on the substrate corresponds to the short side of the trapezoid.

7. The semiconductor structure of claim 2, wherein the source contact plug comprises:

the included angle between the extending direction of the second source electrode contact part and the second extending direction is 90 degrees, the second source electrode contact part is arranged on one side, far away from the grid electrode, of the first source electrode contact part, and at least one first source electrode contact part is connected with at least one second source electrode contact part.

8. The semiconductor structure of claim 7, wherein a projection of the second source contact onto the substrate is located within the source region.

9. The semiconductor structure of claim 7, wherein a projected portion of the second source contact on the substrate covers a portion of a top surface of the source region and another portion covers the substrate adjacent to the source region.

10. The semiconductor structure of claim 2, wherein the drain contact plug comprises at least one first drain contact, at least one of the first drain contact and at least one of the first source contact being symmetrically disposed with respect to the gate.

11. The semiconductor structure of any of claims 7-9, wherein the drain contact plug comprises at least one first drain contact and at least one second drain contact, the at least one first drain contact and the at least one first source contact being symmetrically disposed with respect to the gate, the at least one second drain contact and the at least one second source contact being symmetrically disposed with respect to the gate.

12. The manufacturing method of the semiconductor structure is characterized by comprising the following steps of:

providing an initial structure, wherein the initial structure comprises a substrate and a grid electrode, the substrate comprises an active region, the active region comprises a source region and a drain region, the grid electrode is arranged on the active region and positioned between the source region and the drain region, the grid electrode has a first extending direction and a second extending direction on a plane parallel to the substrate, and the first extending direction is perpendicular to the second extending direction;

forming a source contact plug connected with the source region;

forming a drain contact plug connected with the drain region;

the projection size of one side of the source contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the source contact plug in the first extending direction, and/or the projection size of one side of the drain contact plug, which is close to the grid, in the second extending direction is smaller than the projection size of the drain contact plug in the first extending direction.

13. The method of fabricating a semiconductor structure of claim 12, wherein forming a source contact plug comprises:

At least one first source contact portion is formed, and an included angle is formed between the extending direction of the first source contact portion and the second extending direction.

14. The method of fabricating a semiconductor structure of claim 13, wherein forming a drain contact plug comprises:

and forming at least one second source contact part, wherein the second source contact part extends along the second extending direction, the second source contact part is arranged on one side of the first source contact part far away from the grid electrode, and at least one first source contact part is connected with at least one second source contact part.

15. The method of fabricating a semiconductor structure of claim 12, wherein forming a drain contact plug comprises:

at least one first drain contact is formed, and an included angle is formed between the extending direction of the first drain contact and the second extending direction.

16. The method of fabricating a semiconductor structure of claim 15, wherein forming a drain contact plug comprises:

and forming at least one second drain contact part, wherein the second drain contact part extends along the second extending direction, the second drain contact part is arranged on one side of the first drain contact part far away from the grid electrode, and at least one first drain contact part is connected with at least one second drain contact part.