TWI841063B - Memory device and forming method thereof - Google Patents

Abstract

The present disclosure provides a memory device including a substrate and a bit line on the substrate, in which the bit line includes a capping layer being the topmost layer in a material stack of the bit line and a metal layer below the capping layer, and a top surface width of the metal layer is smaller than a bottom surface width. The memory device also includes a bit line spacer conformally covering a sidewall of the bit line, a contact structure neighboring the bit line, a contact spacer covering a sidewall of the contact structure, a capacitor above the contact structure, and an air gap between the bit line structure spacer and the contact spacer, in which an upper air gap width of the air gap is larger than a lower air gap width.

Description

Memory device and method of forming the same

The present disclosure relates to memory devices, and more particularly to memory devices having air gaps and methods of forming the same.

The critical dimension (CD) of the minimum characteristic of memory devices is constantly shrinking, which in turn reduces the overall size of memory devices and increases the component density of memory devices. However, as the spacing between closely arranged components decreases, the parasitic capacitance between components tends to increase. Therefore, how to form an air gap between device components to effectively reduce parasitic capacitance is an important development project for memory devices.

According to some embodiments of the present disclosure, a memory device includes a substrate, a bit line located on the substrate, wherein the bit line includes a cap layer located at the topmost layer in a material stack of the bit line, and a metal layer located below the cap layer, wherein the top surface width of the metal layer is smaller than the bottom surface width. The memory device also includes a bit line spacer layer conformally covering the sidewalls of the bit line, a contact structure adjacent to the bit line, a contact spacer layer covering the sidewalls of the contact structure, a capacitor located above the contact structure, and an air gap between the bit line spacer layer and the contact spacer layer, wherein the upper air gap width of the air gap is greater than the lower air gap width.

In some embodiments, the air gap has an upper air gap width at a location flush with the top surface of the metal layer and a lower air gap width at a location flush with the bottom surface of the metal layer.

In some embodiments, the upper air gap width tapers to the lower air gap width along the sloped sidewalls of the metal layer.

In some implementations, the difference between the upper air gap width and the lower air gap width is between 5 nm and 15 nm.

In some embodiments, the difference between the upper air gap width and the lower air gap width is equal to half the difference between the top width and the bottom width of the metal layer.

In some implementations, the width of the capping layer is equal to the top width of the metal layer.

In some embodiments, the contact structure includes a unit contact and a pad layer on the unit contact, and an interface between the unit contact and the pad layer is flush with an interface between the metal layer and the capping layer.

According to some embodiments of the present disclosure, a method for forming a memory device includes forming bit lines on a substrate, wherein each bit line includes a metal layer, and the top width of the metal layer is smaller than the bottom width. The method also includes forming a bit line spacer layer to cover the sidewalls of the bit line, filling a sacrificial material between adjacent bit line spacer layers, and etching the sacrificial material to form a sacrificial layer, wherein the bit line spacer layer is located between the bit line and the sacrificial layer, and the upper width of the sacrificial layer is greater than the lower width. The method also includes forming a contact spacer layer to cover the sidewalls of the sacrificial layer, wherein the sacrificial layer is located between the bit line spacer layer and the contact spacer layer. The method further includes forming a contact structure between adjacent inter-contact spacer layers, wherein the contact structure contacts the inter-contact spacer layers. The method further includes removing the sacrificial layer to form an air gap between the inter-bitline spacer layer and the inter-contact spacer layer.

In some embodiments, forming the bit lines includes forming a material stack of each bit line on a substrate, wherein the material stack includes a first material layer, a metal layer on the first material layer, and a second material layer on the metal layer. Forming the bit lines also includes etching the material stack to form the bit lines, wherein the width of the first material layer is equal to the bottom width of the metal layer, and the width of the second material layer is equal to the top width of the metal layer.

In some implementations, the sum of twice the upper width of the sacrificial layer and the top width of the metal layer is equal to the sum of twice the lower width of the sacrificial layer and the bottom width of the metal layer.

According to the above implementation, the memory device formed by the present disclosure includes an air gap between the bit line spacer layer and the contact spacer layer. Since the top surface width of the metal layer in the bit line is smaller than the bottom surface width, the air gap corresponding to the bit line can have an upper air gap width greater than a lower air gap width, thereby increasing the air gap volume between the bit line and the capacitor to reduce the parasitic capacitance between the bit line and the capacitor.

In order to implement different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeatedly refer to numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terminology, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to facilitate describing the relationship of one element or feature to another element or feature as depicted in the figures. Spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure provides a memory device and a method for forming the same, wherein the memory device includes a bit line, a contact structure adjacent to the bit line, a capacitor above the contact structure, and an air gap between the bit line spacer and the contact spacer. The metal layer in the bit line has a top width that is smaller than a bottom width, so that the upper width of the bit line is smaller than the lower width. Therefore, the air gap around the bit line can have an upper air gap width that is larger than a lower air gap width, thereby reducing parasitic capacitance between the bit line and the capacitor.

According to some embodiments of the present disclosure, FIG. 1A shows a cross-sectional view of a memory device 10. The memory device 10 includes a substrate 100, a bit line 110 disposed on the substrate 100, a bit line spacer 120 conformally covering a sidewall of the bit line 110, a contact structure 130 adjacent to the bit line 110, a contact spacer 140 covering a sidewall of the contact structure 130, a capping layer 150 covering the bit line spacer 120 and the contact spacer 140, an air gap 160 disposed between the bit line spacer 120 and the contact spacer 140, and a capacitor 170 disposed above the contact structure 130. The upper air gap width of the air gap 160 is greater than the lower air gap width, thereby increasing the volume of the air gap 160 between the bit line 110 and the capacitor 170, thereby reducing the parasitic capacitance between the bit line 110 and the capacitor 170.

Specifically, the substrate 100 serves as a supporting platform, so that the bit lines 110 and the contact structures 130 are arranged in a staggered manner on the substrate 100. In some embodiments, the substrate 100 can be, for example, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or other semiconductor substrates, wherein the insulator can be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The substrate 100 can be doped, for example, with a p-type dopant, an n-type dopant, or undoped. The semiconductor material of the substrate 100 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors or combinations thereof. The substrate 100 may also be formed of other materials, such as sapphire, tin indium oxide, etc.

In some embodiments, the substrate 100 may include a suitable conductive path therein to allow the current signal to be transmitted to the bit line 110 or the contact structure 130. For example, the substrate 100 may include a contact 102 disposed below the bit line 110, and the contact 102 is electrically connected to the bit line 110. The substrate 100 may also include a contact 104 disposed below the contact structure 130, and the contact 104 is electrically connected to the contact structure 130. In some embodiments, the contacts 102 and 104 in the substrate 100 may include suitable conductive materials, such as metal, metal silicide, metal nitride, the like, or a combination thereof, for effectively transmitting current signals to the bit line 110 and the contact structure 130. In some embodiments, the top surface of the substrate 100 may include a dielectric layer 106 for protecting an active area (AA) in the substrate 100.

The upper width of the bit line 110 on the substrate 100 is smaller than the lower width, so that the bit line 110 has a varying width in the X direction. It is worth noting that the "upper" in this article is used to refer to a position higher than the work function region (such as the metal layer 116) of the bit line 110. In contrast, the "lower" is used to refer to a position lower than the work function region of the bit line 110.

In order to clearly illustrate the width variation of the bit line 110, FIG. 1B shows a partial enlarged view of the region A of the memory device 10 in FIG. 1A. Referring to FIG. 1A and FIG. 1B, a plurality of material layers arranged along the Z direction form a material stack of the bit line 110, wherein the material stack includes a first material layer 112, a second material layer 114, a metal layer 116, and a cap layer 118 located at the topmost layer in order from the top surface of the substrate 100. The first material layer 112, the second material layer 114, and the metal layer 116 can collectively provide the read and write current signal functions of the bit line 110, wherein the metal layer 116 can directly contact the bottom surface of the cap layer 118. The capping layer 118 isolates the metal layer 116 and other components subsequently formed on the bit line 110 to protect the stacking structure formed by the first material layer 112, the second material layer 114 and the metal layer 116.

In the bit line 110, the metal layer 116 has a varying width in the X direction. As shown in FIG. 1B, the top surface of the metal layer 116 has a top surface width W1, and the bottom surface of the metal layer 116 has a bottom surface width W2, and the top surface width W1 is smaller than the bottom surface width W2. In some embodiments, the top surface width W1 may be between 5nm and 10nm, and the bottom surface width W2 may be between 15nm and 20nm. Since the bottom surface width W2 of the metal layer 116 gradually decreases from the bottom surface to the top surface width W1 of the top surface, the metal layer 116 may have a sidewall that is not perpendicular to the top surface of the substrate 100. For example, the metal layer 116 may have inclined straight sidewalls on the X-Z plane shown in FIG. 1B , so that the metal layer 116 has a trapezoidal shape. In some other examples, the sidewalls of the metal layer 116 may have a curvature.

Other material layers of the bit line 110 have widths in the X direction corresponding to the metal layer 116. Specifically, the widths of the material layers below the metal layer 116 (e.g., the first material layer 112 and the second material layer 114) in the X direction are the same as the bottom width W2 of the metal layer 116, and the widths of the material layers above the metal layer 116 (e.g., the cap layer 118) in the X direction are the same as the top width W1 of the metal layer 116. In other words, the bit line 110 has a varying width in the X direction, and the top width W1 of the upper portion of the bit line 110 is smaller than the bottom width W2 of the lower portion.

The material stack of the bit line 110 may have different material layer combinations depending on the design of the memory device 10 or the adhesion between the materials. For example, the first material layer 112 may include a dielectric material or a conductive material, such as silicon oxide, silicon nitride, a high-k dielectric material, polysilicon, the like, or a combination thereof. The second material layer 114 may include a conductive material, such as doped or undoped polysilicon, metal nitride, metal silicide, the like, or a combination thereof. The metal layer 116 may be, for example, a single metal, a metal compound, or an alloy thereof, such as copper, silver, aluminum, titanium, or the like. The cap layer 118 may include a dielectric material, such as silicon oxide, silicon nitride, the like, or a combination thereof.

It should be understood that the bit line 110 shown in FIG. 1A includes a cap layer 118, a metal layer 116, and two material layers below the metal layer 116, but the memory device disclosed herein is not limited thereto. In other embodiments, the bit line 110 may include other numbers of additional material layers in addition to the metal layer 116 and the cap layer 118, and the bit line 110 may have a different material stacking sequence than that shown in FIG. 1A. For example, a bit line formed by swapping the first material layer 112 and the second material layer 114 compared to the bit line 110 shown in FIG. 1A is also within the scope of consideration of the present disclosure.

The bit line spacer layer 120 conformally covers the sidewalls of the bit line 110 to protect the bit line 110. Specifically, the bit line spacer layer 120 has a uniform thickness on the sidewalls of the bit line 110, so the bit line spacer layer 120 includes a first portion covering the first material layer 112 and the second material layer 114 and being perpendicular to the top surface of the substrate 100, a second portion covering the metal layer 116 but not perpendicular to the top surface of the substrate 100, and a third portion covering the cap layer 118 and being perpendicular to the top surface of the substrate 100. In other words, the first portion, the second portion, and the third portion that continuously cover the bit line 110 form a bent bit line spacer layer 120.

In some embodiments, the bit line spacer layer 120 may have an appropriate thickness to protect the structure of the bit line 110. For example, the thickness of the bit line spacer layer 120 may be between 4 nm and 8 nm, and uniformly cover the sidewalls of the first material layer 112, the second material layer 114, the metal layer 116, and the capping layer 118. In some embodiments, the material forming the bit line spacer layer 120 may be a suitable dielectric material, such as silicon nitride, a low-k dielectric material, or a combination thereof. The bit line spacer layer 120 may be a dielectric material of a single-layer structure, a double-layer structure, or a multi-layer structure, and the multi-layer structure of the bit line spacer layer 120 may include different material compositions.

The contact structure 130 is located between adjacent bit lines 110, so that the bit lines 110 and the contact structure 130 are arranged alternately on the substrate 100. The contact structure 130 is electrically connected to the capacitor 170 above it, wherein the capacitor 170 can serve as a memory cell of the memory device 10. In other words, the contact structure 130 serves as a conductive path of the memory device 10 in the Z direction, so that the current signal can be transmitted between the substrate 100 and the capacitor 170. As shown in FIG. 1A, the contact structure 130 can extend into the active area in the substrate 100, so that the bottom surface of the contact structure 130 is lower than the top surface of the substrate 100.

In some embodiments, the contact structure 130 may include a cell contact 132 and a pad layer 134 on the cell contact 132. For example, the cell contact 132 may be formed of polysilicon, doped polysilicon, metal, the like, or a combination thereof, and the pad layer 134 may include metal, metal silicide, metal nitride, or other suitable materials. The contact structure 130 may further include a barrier layer (not specifically shown) located on the side surface and the bottom surface of the cell contact 132, wherein the barrier layer is interposed between the cell contact 132 and the substrate 100. In some embodiments, the distance between the top surface of the cell contact 132 and the substrate 100 may be the same as the distance between the top surface of the metal layer 116 and the substrate 100, so that the interface between the cell contact 132 and the pad layer 134 is flush with the interface between the metal layer 116 and the capping layer 118.

The contact spacer 140 covers the sidewalls of the contact structure 130 to protect the contact structure 130. Specifically, the contact spacer 140 has a uniform thickness on the sidewalls of the contact structure 130, so that the contact spacer 140 can conformally cover the contact structure 130. In an embodiment in which the contact structure 130 extends into the substrate 100, the contact spacer 140 can be located on the substrate 100 without being formed between the contact structure 130 and the substrate 100.

In some embodiments, the contact spacer layer 140 may have an appropriate thickness to protect the structure of the contact structure 130. For example, the thickness of the contact spacer layer 140 may be between 4 nm and 8 nm, and evenly cover the sidewalls of the unit contact 132 and the pad layer 134. In some embodiments, the material forming the contact spacer layer 140 may be a suitable dielectric material, such as silicon nitride, a low dielectric constant dielectric material, or a combination thereof. The contact spacer layer 140 may be a dielectric material of a single-layer structure, a double-layer structure, or a multi-layer structure, and the multi-layer structure of the contact spacer layer 140 may include different material compositions. In some embodiments, the material forming the bit line spacer layer 120 and the contact spacer layer 140 may be the same material. For example, the bit line spacer layer 120 and the contact spacer layer 140 may be formed of silicon nitride.

The bit line spacer layer 120 and the contact spacer layer 140 are spaced apart in the X direction, so when the cap layer 150 covers the top surfaces of the bit line spacer layer 120 and the contact spacer layer 140, an air gap 160 may be formed between the bit line spacer layer 120 and the contact spacer layer 140. A gas may be filled in the air gap 160 to reduce parasitic capacitance between components surrounding the air gap 160. In some embodiments, the cap layer 150 covers the bit line 110 and the bit line spacer layer 120 and the contact spacer layer 140 on both sides of the bit line 110, and exposes the top surface of the contact structure 130. In some embodiments, the cap layer 150 may include silicon nitride, silicon oxide, silicon nitride carbon oxide, or other suitable dielectric materials. In some embodiments, the cap layer 150 may be a horizontal film as shown in FIG. 1A , but in other embodiments, the cap layer 150 may include a portion extending into the air gap 160 , or the cap layer 150 may be an interlayer dielectric layer having a thickness sufficient to surround the capacitor 170 , and the present disclosure is not limited thereto.

The bit line 110 has a variable width in the X direction, resulting in the air gap 160 also having a variable width in the X direction. Specifically, referring to FIG. 1A and FIG. 1B , the upper width of the bit line 110 is smaller than the lower width, resulting in the upper air gap width W3 of the air gap 160 being larger than the lower air gap width W4. Since the air gap 160 has a larger upper air gap width W3, a larger air gap volume is provided between the upper portion of the bit line 110 and the capacitor 170, and thus the air gap 160 can more significantly reduce the parasitic capacitance between the bit line 110 and the capacitor 170.

More specifically, the air gap 160 has a uniform upper air gap width W3 between the top surface of the bit line 110 and the top surface of the metal layer 116. As the air gap 160 extends downward from the top surface of the metal layer 116 to the bottom surface of the metal layer 116, the upper air gap width W3 tapers to a lower air gap width W4 along the inclined sidewall of the metal layer 116. Between the bottom surface of the metal layer 116 and the top surface of the substrate 100, the air gap 160 has a uniform lower air gap width W4. In other words, the width of the air gap 160 varies with the width of the bit line 110 , so that the air gap 160 has a larger upper air gap width W3 at a position flush with the top surface of the metal layer 116 , and has a smaller lower air gap width W4 at a position flush with the bottom surface of the metal layer 116 .

In some embodiments, the upper air gap width W3 and the lower air gap width W4 can be matched with the top surface width W1 and the bottom surface width W2 of the metal layer 116, so that the sidewall of the air gap 160 adjacent to the contact spacer layer 140 is perpendicular to the top surface of the substrate 100. Specifically, the difference between the upper air gap width W3 and the lower air gap width W4 can be equal to half the difference between the top surface width W1 and the bottom surface width W2 of the metal layer 116. In such an embodiment, adjacent contact spacer layers 140 can be kept equidistant, thereby forming a vertical sidewall of the air gap 160.

In some embodiments, the difference between the upper air gap width W3 and the lower air gap width W4 may be between about 5 nm and about 15 nm. For example, the air gap 160 may have, for example, an upper air gap width W3 of about 9 nm and a lower air gap width W4 of about 3 nm, wherein the difference between the upper air gap width W3 and the lower air gap width W4 is about 6 nm. If the difference between the air gap widths is less than 5 nm, the upper portion of the air gap 160 may be too narrow to significantly reduce the parasitic capacitance between the bit line 110 and the capacitor 170; if the difference between the air gap widths is greater than 15 nm, the air gap 160 may cause the upper portion of the bit line 110 to be too thin, making the structure of the bit line 110 easily damaged.

It should be understood that in order to clearly illustrate the structure of the memory device 10, some components of the memory device 10 are shown in Figures 1A and 1B, but the implementation method of the present disclosure can also be applied to memory devices including additional components (such as word lines, interlayer dielectric layers, interconnect layers, etc.) or omitting some components (such as dielectric layer 106).

According to some embodiments of the present disclosure, FIGS. 2A to 2J illustrate cross-sectional views of a memory device at various stages of a manufacturing process. For ease of explanation, the manufacturing process shown in FIGS. 2A to 2J will be used as an example to form a memory device 10, however, those skilled in the art should understand that the process shown in FIGS. 2A to 2J may also be applied to form other memory devices within the scope of the present disclosure. Unless otherwise specified, when FIGS. 2A to 2J are illustrated as a series of steps of an embodiment, the order in which these steps are described should not be limited. For example, a portion of the steps may be performed in a different order than the embodiment described, may occur simultaneously, may not be required, and/or may be repeated. Furthermore, additional steps may be performed before, during, or after the steps depicted to form the memory device.

First, referring to FIG. 2A , a plurality of bit lines 110 are formed on a substrate 100. Specifically, a first material layer 112, a second material layer 114, a metal layer 116, and a cap layer 118 are sequentially formed on the top surface of the substrate 100, thereby forming a material stack of the bit lines 110. The sidewalls of the material layers of the bit lines 110 may be aligned with each other, so that the bit lines 110 have straight sidewalls and are perpendicular to the top surface of the substrate 100. In an embodiment in which the substrate 100 includes the contacts 102 and the contacts 104, the bit lines 110 may be located on the contacts 102, and the contacts 104 may be distributed between adjacent bit lines 110.

2B , the sidewall of the bit line 110 is etched to form a bit line 110 having an upper width smaller than a lower width. Specifically, an anisotropic etching process is performed on the material stack of the bit line 110, so that the upper etching amount of the bit line 110 is greater than the lower etching amount. In some embodiments, the anisotropic etching process can be, for example, a dry etching process using plasma.

More specifically, the etching process can selectively etch the metal layer 116 and the cap layer 118 in the bit line 110, while having substantially no etching effect on the first material layer 112 and the second material layer 114 below the metal layer 116. In addition, the etching process can cause different etching amounts on the top surface and the bottom surface of the metal layer 116, resulting in the metal layer 116 having a top surface width smaller than a bottom surface width after etching. Therefore, after the etching process, the first material layer 112 and the second material layer 114 below the metal layer 116 and the bottom surface of the metal layer 116 can maintain the original width of the bit line 110, and the width of the capping layer 118 above the metal layer 116 is the same as the top surface width of the metal layer 116.

Referring to FIG. 2C , a bit line spacer layer 120 is formed to cover the sidewalls of the bit line 110. Specifically, the bit line spacer layer 120 is conformally deposited on the sidewalls of the bit line 110 to protect the bit line 110 in subsequent processes, thereby increasing device reliability. In some embodiments, the bit line spacer layer 120 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

In some embodiments, the bit line spacer layer 120 may be first deposited on the top surface of the substrate 100, the sidewalls of the bit line 110, and the top surface of the bit line 110, thereby forming the bit line spacer layer 120 that conformally covers the bit line 110. Then, the bit line spacer layer 120 extending in the horizontal direction (i.e., the X direction in FIG. 2C ) is selectively removed, so that the bit line spacer layer 120 covers the sidewalls of the bit line 110 and exposes the top surface of the bit line 110. Since the capping layer 118 located at the topmost layer in the bit line 110 can protect other material layers below, the bit line spacer layer 120 on the top surface of the bit line 110 can be removed, thereby reducing the overall thickness of the device.

Referring to FIG. 2D , a sacrificial material 200 is filled between adjacent bit line spacer layers 120. Specifically, the sacrificial material 200 is deposited between adjacent bit line spacer layers 120, wherein the sacrificial material 200 directly contacts the bit line spacer layers 120 on both sides. The height of the sacrificial material 200 in the Z direction is the same as that of the bit line 110, so that the sacrificial material 200 fills the gap between the bit line spacer layers 120. In some embodiments, the composition of the sacrificial material 200 may include a suitable dielectric material, and the composition of the sacrificial material 200 may be different from that of the bit line spacer layer 120 and the subsequently formed contact spacer layer 140, thereby resulting in etching selectivity between the sacrificial material 200 and the bit line spacer layer 120 and between the sacrificial material 200 and the contact spacer layer 140. For example, in an embodiment where the bit line spacer layer 120 and the contact spacer layer 140 are formed of silicon nitride, the sacrificial material 200 may include silicon oxide.

In some embodiments, the sacrificial material 200 may be formed using a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition (PVD), etc. In some embodiments, the sacrificial material 200 may be first deposited to cover the bit line 110 and the bit line spacer 120, so that the top surface of the sacrificial material 200 is higher than the top surface of the bit line 110 and the bit line spacer 120. Then, a planarization process such as chemical mechanical polishing (CMP) is performed to make the top surface of the sacrificial material 200 flush with the top surface of the bit line 110.

Referring to FIG. 2E , a photoresist layer 210 is formed on the top surface of the sacrificial material 200. Specifically, the material of the photoresist layer 210 is first deposited to cover the top surface of the sacrificial material 200. After exposure and development processes, a photoresist layer 210 having a pattern is formed on the top surface of the sacrificial material 200 and has an opening 215 that exposes a portion of the top surface of the sacrificial material 200. The pattern of the photoresist layer 210 corresponds to the air gap 160 formed subsequently, so the width W5 of the photoresist layer 210 in the X direction may correspond to the upper air gap width of the air gap 160 (e.g., the upper air gap width W3 shown in FIG. 1B ). In some embodiments, the width W5 of the photoresist layer 210 may be between 7 nm and 12 nm.

2F , a sacrificial layer 202 is formed on the sidewalls of the bit line spacer layer 120. Specifically, the photoresist layer 210 is used as a mask, and an etching process is performed on the sacrificial material 200 to extend the opening 215 in FIG. 2E into the sacrificial material 200. The etching process may stop at the top surface of the substrate 100, thereby exposing the top surface of the substrate 100. In an embodiment in which the dielectric layer 106 is included on the top surface of the substrate 100, the etching process may stop at the top surface of the dielectric layer 106. After the etching process, the sacrificial material 200 is separated into a plurality of sacrificial layers 202, wherein the sacrificial layers 202 cover the sidewalls of the bit line spacer layer 120 along the Z direction. In other words, the bit line spacer layer 120 is sandwiched between the bit line 110 and the sacrificial layer 202. In some embodiments, after etching the sacrificial material 200, the photoresist layer 210 may be removed using, for example, a stripping process to expose the top surface of the sacrificial layer 202, as shown in FIG. 2G.

In some embodiments, the sacrificial layer 202 is formed by an anisotropic etching process using the photoresist layer 210 as a mask, so that the sidewall of the sacrificial layer 202 away from the bit line 110 can be perpendicular to the top surface of the substrate 100. Since the photoresist layer 210 is used as an etching mask, the upper portion of the sacrificial layer 202 has a width W5 that is the same as the width of the photoresist layer 210. When the sacrificial layer 202 extends to the lower portion of the bit line 110, since the lower portion of the bit line 110 has a greater width than the upper portion of the bit line 110, the lower portion of the sacrificial layer 202 is correspondingly reduced to a width W6 in the X direction. In some implementations, the lower width W6 of the sacrificial layer 202 may correspond to the lower air gap width of the air gap 160 (eg, the lower air gap width W4 shown in FIG. 1B ). For example, the lower width W6 of the sacrificial layer 202 may be between 1 nm and 5 nm.

More specifically, both sides of the bit line 110 may include a sacrificial layer 202 covering the bit line spacer layer 120, and the sacrificial layer 202 on both sides has vertical sidewalls away from the bit line 110. For the upper portion of the bit line 110 and the lower portion of the bit line 110, the sum of the widths of the bit line 110, the bit line spacer layer 120 on both sides, and the sacrificial layer 202 on both sides in the X direction may be the same. In other words, the sum of twice the upper width W5 of the sacrificial layer 202 and the top width of the metal layer 116 (such as the top width W1 shown in FIG. 1B ) may be equal to the sum of twice the lower width W6 of the sacrificial layer 202 and the bottom width of the metal layer 116 (such as the bottom width W2 shown in FIG. 1B ).

2H , a contact spacer layer 140 is formed to cover the sidewalls of the sacrificial layer 202. Specifically, the contact spacer layer 140 is deposited on the sidewalls of the sacrificial layer 202 so that the sacrificial layer 202 is sandwiched between the bit line spacer layer 120 and the contact spacer layer 140. In some embodiments, the contact spacer layer 140 may be formed using a deposition process similar to that used to form the bit line spacer layer 120, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, etc. In some embodiments, the bit line spacer layer 120 and the contact spacer layer 140 may be deposited using the same material, such as silicon nitride.

In some embodiments, the contact spacer layer 140 may be first deposited on the top surface of the substrate 100, the sidewalls of the sacrificial layer 202, the top surface of the sacrificial layer 202, the top surface of the bit line spacer layer 120, and the top surface of the bit line 110, so as to conformally cover the structure in FIG. 2G. Then, the contact spacer layer 140 extending in the horizontal direction (i.e., the X direction in FIG. 2H) is selectively removed, so that the contact spacer layer 140 covers the sidewalls of the sacrificial layer 202 and exposes the top surface of the sacrificial layer 202.

2I , a contact structure 130 is formed between adjacent contact spacers 140. Specifically, a suitable deposition or electroplating process may be used to form the contact structure 130 so that the contact structure 130 fills the gap between the contact spacers 140 and directly contacts the contact spacers 140 on both sides. Next, a planarization process may be performed so that the height of the contact structure 130 in the Z direction is the same as that of the bit line 110, so that the contact structure 130, the contact spacer 140, the sacrificial layer 202, the bit line spacer 120, and the bit line 110 have coplanar top surfaces.

In some embodiments, forming the contact structure 130 may include filling the material of the unit contact 132 between the contact spacer layer 140, and performing a planarization process so that the top surface of the unit contact 132 is flush with the top surface of the metal layer 116. Then, filling the material of the pad layer 134 on the top surface of the unit contact 132, and performing a planarization process so that the top surface of the pad layer 134 is flush with the top surface of the cap layer 118. In some embodiments, before forming the contact structure 130, the substrate 100 may be etched to form an opening (not specifically shown) extending into the substrate 100. Next, the material of the contact structure 130 is deposited in the opening, thereby causing the bottom surface of the contact structure 130 to be lower than the top surface of the substrate 100, as shown in FIG. 2I .

2J, the sacrificial layer 202 is removed to form an air gap 160 between the bit line spacer layer 120 and the contact spacer layer 140. Specifically, the sacrificial layer 202 is removed using an etching process to form a gap between the bit line spacer layer 120 and the contact spacer layer 140. Since the material of the bit line spacer layer 120 and the contact spacer layer 140 is different from the material of the sacrificial layer 202, the etching process can selectively etch the sacrificial layer 202, while having substantially no etching effect on the bit line spacer layer 120 and the contact spacer layer 140. In some embodiments, the etching process can be wet etching. After removing the sacrificial layer 202 , a capping layer 150 may be deposited on the bit line spacer layer 120 and the contact spacer layer 140 , thereby forming an air gap 160 .

The air gap 160 formed by removing the sacrificial layer 202 has a profile similar to that of the sacrificial layer 202, such that the upper air gap width of the air gap 160 is greater than the lower air gap width, thereby increasing the volume of the air gap 160 between the upper portion of the bit line 110 and the contact structure 130. After the capacitor 170 is subsequently formed above the contact structure 130, the air gap 160 can reduce the parasitic capacitance between the bit line 110 and the capacitor 170, thereby increasing the reliability of the memory device 10. In addition, since the air gap 160 is derived from the removed sacrificial layer 202 and the width variation of the sacrificial layer 202 is derived from etching the upper portion of the bit line 110, the upper air gap width of the air gap 160 can be increased without affecting other device sizes, thereby maintaining the device density of the memory device 10.

According to the above-mentioned implementation mode of the present disclosure, the memory device of the present disclosure includes a bit line whose upper width is smaller than the lower width, and an air gap whose upper air gap width is larger than the lower air gap width corresponding to the width change of the bit line. Since there is an increased air gap width between the upper part of the bit line and the capacitor, the air gap can particularly reduce the parasitic capacitance between the bit line and the capacitor, thereby increasing the reliability of the memory device. The method of forming a memory device of the present disclosure increases the air gap width by reducing the width of the bit line, thereby reducing the parasitic capacitance between the bit line and the capacitor without affecting the device size and component density.

The features of some embodiments are summarized above so that those skilled in the art can better understand the perspective of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

10: Memory device

100: Substrate

102,104: Contacts

106: Dielectric layer

110: Bit line

112: First material layer

114: Second material layer

116:Metal layer

118: Covering

120: Bit line spacing layer

130: Contact structure

132: Unit contact

134:Pad layer

140: Contact spacer

150: Covering

160: Air gap

170:Capacitor

200: Sacrificial Materials

202: Sacrifice layer

210: Photoresist layer

215: Open

A: Area

W1: Top width

W2: Bottom width

W3: Upper air gap width

W4: Lower air gap width

W5,W6: Width

X,Z: Direction

Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale, in accordance with standard practices in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A illustrates a cross-sectional view of a memory device according to some embodiments of the present disclosure. FIG. 1B illustrates a partial enlarged view of the memory device in FIG. 1A. FIGS. 2A to 2J illustrate cross-sectional views of a memory device at various stages of a manufacturing process according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

10: Memory device

100: Substrate

102,104: Contacts

106: Dielectric layer

110: Bit line

112: First material layer

114: Second material layer

116:Metal layer

118: Covering layer

120: Bit line spacing layer

130: Contact structure

132: Unit contact

134:Pad layer

140: Contact spacer layer

150: Covering layer

160: Air gap

170:Capacitor

A: Area

X,Z: Direction

Claims (10)

A memory device comprises: a substrate; a bit line located on the substrate, wherein the bit line comprises: a cap layer located at the topmost layer in a material stack of the bit line; and a metal layer located below the cap layer, wherein a top surface width of the metal layer is smaller than a bottom surface width; and a bit line spacer layer conformally covering the bit line. A side wall of a bit line; a contact structure adjacent to the bit line; a contact spacer layer covering a side wall of the contact structure; a capacitor located above the contact structure; and an air gap between the bit line spacer layer and the contact spacer layer, wherein an upper air gap width of the air gap is greater than a lower air gap width. A memory device as described in claim 1, wherein the air gap has the upper air gap width at a position flush with a top surface of the metal layer, and has the lower air gap width at a position flush with a bottom surface of the metal layer. A memory device as described in claim 1, wherein the upper air gap width tapers to the lower air gap width along an inclined side wall of the metal layer. A memory device as described in claim 1, wherein the difference between the upper air gap width and the lower air gap width is between 5nm and 15nm. A memory device as described in claim 4, wherein the difference between the upper air gap width and the lower air gap width is equal to half the difference between the top surface width and the bottom surface width of the metal layer. A memory device as described in claim 1, wherein a width of the cap layer is equal to the top width of the metal layer. A memory device as described in claim 1, wherein the contact structure includes a unit contact and a pad layer on the unit contact, and an interface between the unit contact and the pad layer is flush with an interface between the metal layer and the cap layer. A method for forming a memory device includes: forming a plurality of bit lines on a substrate, wherein each of the bit lines includes a metal layer, a top surface width of the metal layer is smaller than a bottom surface width; forming a plurality of bit line spacer layers to cover a plurality of sidewalls of the bit lines; filling a sacrificial material between adjacent bit line spacer layers; etching the sacrificial material to form a plurality of sacrificial layers, wherein the bit line spacer layers are located between the bit lines and the sacrificial layers, and an upper width of the sacrificial layers is less than a bottom surface width. The invention relates to a method for forming a plurality of contact spacer layers to cover the plurality of side walls of the sacrificial layers, wherein the sacrificial layers are located between the bit line spacer layers and the contact spacer layers; forming a contact structure between the adjacent contact spacer layers, wherein the contact structure contacts the contact spacer layers; and removing the sacrificial layers to form a plurality of air gaps between the bit line spacer layers and the contact spacer layers, wherein an upper air gap width of the air gaps is greater than a lower air gap width. The method as described in claim 8, wherein forming the bit lines comprises: forming a material stack for each of the bit lines on the substrate, wherein the material stack comprises a first material layer, the metal layer on the first material layer, and a second material layer on the metal layer; and etching the material stack to form the bit lines, wherein a width of the first material layer is equal to the bottom width of the metal layer, and a width of the second material layer is equal to the top width of the metal layer. The method as described in claim 8, wherein the sum of twice the upper width of the sacrificial layers and the top width of the metal layer is equal to the sum of twice the lower width of the sacrificial layers and the bottom width of the metal layer.

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