CN115643751A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115643751A CN115643751A CN202110815765.0A CN202110815765A CN115643751A CN 115643751 A CN115643751 A CN 115643751A CN 202110815765 A CN202110815765 A CN 202110815765A CN 115643751 A CN115643751 A CN 115643751A
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Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein a plurality of bit lines which are arranged in parallel at intervals are formed on the substrate; forming a contact plug between adjacent bit lines, and forming a metal silicide layer on the upper surface of the contact plug; the upper surface of the contact plug is lower than the upper surface of the bit line, and a gap is formed between the metal silicide layer and the bit line; forming a contact pad on the metal silicide layer, wherein the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure; the contact pad portion extends into the gap, and the length of the part of the contact pad extending into the gap is less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit line. The semiconductor structure can reduce contact resistance, parasitic capacitance and electric leakage risk, improve the electrical performance of the semiconductor structure and improve the yield of the semiconductor structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
A Dynamic Random Access Memory (DRAM) is a semiconductor Memory commonly used in electronic devices such as computers, and is composed of a plurality of Memory cells. Wherein, the memory cell includes: a storage capacitor, and a transistor electrically connected to the storage capacitor. The transistor includes a gate electrode, a source region, and a drain region. The gate of the transistor is used to electrically connect to a word line. The source region of the transistor is used to constitute a bit line contact region to be electrically connected to a bit line through a bit line contact structure. The drain region of the transistor is used to constitute a storage node contact region to be electrically connected to the storage capacitor through the storage node contact structure.
However, as the size of the DRAM is smaller, the size of the storage node contact structure is also reduced, so that a larger contact resistance is easily generated between the transistor and the storage capacitor, which results in a slow speed of the DRAM and even a failure of a device (e.g., a chip) in which the DRAM is located. Therefore, how to reduce the contact resistance between the transistor and the storage capacitor and improve the performance of the DRAM device has become an urgent technical problem to be solved in the current advanced semiconductor manufacturing process.
Disclosure of Invention
Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce contact resistance inside the semiconductor structure, effectively reduce the risk of leakage of the storage node contact structure, and reduce the parasitic capacitance between the storage node contact structure and the bit line. Thereby improving the electrical performance of the semiconductor structure and improving the yield of the semiconductor structure.
To achieve the above objects, in one aspect, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, which includes the following steps.
A substrate is provided, and a plurality of bit lines arranged at intervals in parallel are formed on the substrate.
Contact plugs are formed between adjacent bit lines, and a metal silicide layer is formed on upper surfaces of the contact plugs. The upper surface of the contact plug is lower than the upper surface of the bit line, and a gap is formed between the metal silicide layer and the bit line.
And forming a contact pad on the metal silicide layer, wherein the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure. The contact pad portion extends into the gap, and the length of the part of the contact pad extending into the gap is less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit line.
In another aspect, some embodiments of the present disclosure provide a semiconductor structure prepared by the method according to some embodiments.
The semiconductor structure includes: a substrate and a storage node contact structure. A plurality of bit lines are formed on the substrate and arranged at intervals in parallel. The storage node contact structure includes a contact plug, a metal silicide layer and a contact pad. The contact plug is positioned between adjacent bit lines, and the upper surface of the contact plug is lower than the upper surfaces of the bit lines. The metal silicide layer is located on the upper surface of the contact plug, and an air gap is formed between the metal silicide layer and the bit line. The contact pad is located on the metal silicide layer, and part of the contact pad extends to between the metal silicide layer and the bit line and is located above the air gap.
In one example, the semiconductor structure further comprises: a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned on the surface of the bit line and positioned between the bit line and the storage node contact structure. The second dielectric layer is positioned on the surface of the first dielectric layer, is positioned between the first dielectric layer and the storage node contact structure and is positioned below the air gap.
In the semiconductor structure and the manufacturing method thereof provided by the embodiment of the disclosure, a gap is formed between the metal silicide layer and the bit line, and the contact pad partially extends into the gap, so that a larger contact area can be formed between the contact pad and the metal silicide layer, and an air gap is reserved between the metal silicide layer and the bit line. Therefore, the contact resistance between the contact pad and the contact plug can be reduced, the risk of electric leakage of the storage node contact structure is reduced by using the air gap, and the parasitic capacitance between the storage node contact structure and the bit line is reduced. Thereby effectively improving the electrical performance of the semiconductor structure and improving the yield of the semiconductor structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic top view of a semiconductor structure provided in one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;
FIG. 3 is an enlarged view of an I region of the semiconductor structure shown in FIG. 2;
FIG. 4 is an enlarged view of another I region of the semiconductor structure shown in FIG. 2;
FIG. 5 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S11 of the manufacturing method shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the structure obtained in step S12 of the manufacturing method shown in FIG. 5;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S13 of the manufacturing method shown in FIG. 5;
fig. 9 is a flowchart of a method for forming a metal silicide layer in a semiconductor structure according to an embodiment;
FIG. 10 is a schematic cross-sectional view of the structure obtained in step S121 of the manufacturing method shown in FIG. 9;
FIG. 11 is a schematic cross-sectional view of a structure provided in an embodiment after a second dielectric layer is directly formed on the sidewalls of the bit lines;
fig. 12 is a schematic cross-sectional view of the structure obtained in step S122 in the manufacturing method shown in fig. 9;
FIG. 13 is a schematic cross-sectional view of the structure obtained in step S123 of the manufacturing method shown in FIG. 9;
FIG. 14 is a schematic cross-sectional view of the structure after removing a portion of the first dielectric layer and a portion of the bit line sidewalls, according to one embodiment;
fig. 15 is a schematic cross-sectional view of the structure obtained in step S124 in the manufacturing method shown in fig. 9;
FIG. 16 is a cross-sectional view of a metal layer provided in one embodiment;
FIG. 17 is a cross-sectional view of another metal layer provided in an embodiment;
FIG. 18 is a schematic cross-sectional view of the structure obtained in step S125 of the manufacturing method shown in FIG. 9;
FIG. 19 is a schematic cross-sectional view of the structure obtained in step S126 of the manufacturing method shown in FIG. 9;
fig. 20 is a schematic cross-sectional view of a metal silicide layer provided in an embodiment;
FIG. 21 is a schematic cross-sectional view of another metal silicide layer provided in an embodiment;
FIG. 22 is a flow chart of a method for fabricating a contact pad in a semiconductor structure provided in one embodiment;
FIG. 23 is a diagram illustrating a process for fabricating a contact pad in a semiconductor structure, in accordance with one embodiment;
fig. 24 is a diagram illustrating a process for fabricating a contact pad in another semiconductor structure provided in an embodiment.
Description of reference numerals:
100-semiconductor structure, 1-substrate, 10-shallow trench isolation structure, 11-insulating layer, 2-active region, 3-bit line,
31-bit line structure, 32-sidewall structure, 321-first silicon nitride layer, 322-silicon oxide layer, 323-second silicon nitride layer,
4-buried gate word line, 5-storage node contact structure, 51-contact plug, 52-metal silicide layer,
53-contact pad, 531-adhesion layer, 532-pad conductive layer, 6-first dielectric layer, 7-second dielectric layer,
l-gap, G-air gap, S 1 Upper surface of contact plug, S 2 -an upper surface of the bit line,
S 3 upper surface of the second dielectric layer, H G Height of air gap, H L -the height of the gap is such that,
L 1 -the length of the portion of the contact pad extending into the gap, 510-the layer of contact plug material,
H C height of contact plug, H W -height of bit line, 512-metal layer, V-void.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Referring to fig. 1 and 2, an embodiment of the present disclosure provides a semiconductor structure 100. The semiconductor structure 100 includes: a substrate 1, and a storage node contact structure 5 disposed on the substrate 1.
In one example, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
In one example, a shallow trench isolation structure 10 is provided within the substrate 1. The shallow trench isolation structure 10 isolates a plurality of active regions 2 arranged in an array in the substrate 1, and the active regions 2 include source regions and drain regions (not shown in fig. 1).
Optionally, the shallow trench isolation structure 10 is silicon oxide (SiO) 2 ) And (6) an isolation structure.
Optionally, the material of the active region 2 is polysilicon (poly), and the source region and the drain region of the active region 2 are doped regions of polysilicon.
In one example, as shown in fig. 1, a substrate 1 is formed thereon with a plurality of bit lines 3 arranged in parallel at intervals and a plurality of buried gate word lines 4 arranged in parallel at intervals. The embedded gate word lines 4 extend along a first direction, the bit lines 3 extend along a second direction, and an included angle between the first direction and the second direction is greater than 0 ° and less than or equal to 90 °. The active region 2 crosses over the two buried gate word lines 4, a source region of the active region 2 is located between the two buried gate word lines 4 crossed by the active region 2, and a drain region of the active region 2 is located outside the two buried gate word lines 4 crossed by the active region 2.
Alternatively, as shown in fig. 2, the bit line 3 includes a bit line structure 31 and a sidewall structure 32. The bit line structure 31 includes: a conductive portion coupled corresponding to the source region of the active region 2, and an insulating portion covering the top surface of the conductive portion. The sidewall structures 32 include at least one dielectric layer. The material of the insulating portion and the dielectric layer is, for example, silicon oxide (SiO) 2 ) Or silicon nitride (Si) x N y ) At least one of (1). The conductive portion may have a single-layer structure or a stacked-layer structure, and the material of the conductive portion includes, for example, at least one of polysilicon or metal.
In addition, optionally, as shown in fig. 2, the bottom of some bit line structures 31 extends into the substrate 1 and is coupled to the corresponding source region, the peripheral side of the bottom of the bit line structure 31 is further provided with an insulating layer 11 filled in the substrate 1, and the material of the insulating layer 11 is, for example, silicon oxide (SiO) for example 2 ) Or silicon nitride (Si) x N y ) At least one of (1).
With continued reference to fig. 2, the storage node contact structure 5 includes a contact plug 51, a metal silicide layer 52, and a contact pad 53. Contact plug 51 is located between adjacent bit lines 3, and upper surface S of contact plug 51 1 Lower than the upper surface S of the bit line 3 2 . The metal silicide layer 52 is located on the upper surface of the contact plug 51, and an air gap G is formed between the metal silicide layer 52 and the bit line 3. Contact pad 53 is situated on metal silicide layer 52 and extends partially between metal silicide layer 52 and bit line 3 and over air gap G.
Here, the upper surface of the contact plug 51 includes the upper surface S of the contact plug 51 1 . For example, the upper surface of the contact plug 51 is the upper surface S of the contact plug 51 1 Alternatively, the upper surface of the contact plug 51 is the upper surface S of the contact plug 51 1 And an upper surface S 1 Adjacent side surfaces.
In one example, the contact plug 51 of the storage node contact structure 5 is correspondingly coupled to the drain region of the active region 2, and the material of the contact plug 51 is, for example, polysilicon. Fig. 1 illustrates only the distribution of the active region 2, the bit line 3, and the buried gate word line 4, and does not illustrate the storage node contact structure 5. Thus, the orthographic projection position of the storage node contact structure 5 on the substrate 1 can be understood from the foregoing.
In one example, the contact plug 51 is a polysilicon layer, and the metal silicide layer 52 is a cobalt silicide (CoSi) layer.
In the embodiment of the present disclosure, the metal silicide layer 52 has a gap with the bit line 3, so that the contact pad 53 may partially extend into the gap to ensure a larger contact area between the contact pad 53 and the metal silicide layer 52, and so that an air gap G remains between the metal silicide layer 52 and the bit line 3. Thereby advantageously reducing the contact resistance between the contact pad 53 and the contact plug 51, reducing the risk of leakage of the storage node contact structure 5 using the air gap G, and reducing the parasitic capacitance between the storage node contact structure 5 and the bit line 3. Thereby effectively improving the electrical performance of the semiconductor structure 100 and increasing the yield of the semiconductor structure 100.
Height H of air gap G G The settings can be selected according to actual requirements. In one example, as shown in FIG. 3, the height H of the air gap G G Is the height H of the gap L between the metal silicide layer 52 and the bit line 2 L 20 to 80 percent of the total weight of the composition. For example, the height H of the air gap G G Is the height H of the gap L between the metal silicide layer 52 and the bit line 2 L 20%, 40%, 60% or 80%.
In one example, with continued reference to fig. 3, the semiconductor structure 100 further includes: a first dielectric layer 6 and a second dielectric layer 7. The first dielectric layer 6 is located on the surface of the bit line 3 and between the bit line 3 and the storage node contact structure 5. For example, the first dielectric layer 6 is located on the surface of the sidewall structure 32 of the bit line 3. The second dielectric layer 7 is located on the surface of the first dielectric layer 6, between the first dielectric layer 6 and the storage node contact structure 5, and below the air gap G.
Optionally, the first dielectric layer 6 includes a silicon nitride layer, and the second dielectric layer 7 includes a silicon oxide layer. However, the first dielectric layer 6 and the second dielectric layer 7 are not limited to this.
In another example, referring to fig. 4, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction away from the bit line structure 31. Based on this, in the case where the thickness of the second silicon nitride layer 323 satisfies the use requirement, the second silicon nitride layer 323 may be used as the first dielectric layer 6 in the foregoing example. That is, in this example, the semiconductor structure 100 includes the second dielectric layer 7, and the second dielectric layer 7 is located on the surface of the sidewall structure 32 of the bit line 3. The material of the second dielectric layer 7 is different from the material of the outermost dielectric layer in the sidewall structures 32 of the bit line 3. For example, the outermost dielectric layer in the sidewall structure 32 of the bit line 3 is the second silicon nitride layer 323, and the second dielectric layer 7 is a silicon oxide layer.
It will be appreciated that the metal silicide layer 52 may be prepared by metallization of a polysilicon material. As such, the shape of the metal silicide layer 52 is related to the shape of the metallization in the polysilicon material.
In one example, as shown in fig. 3, the upper surface S of the contact plug 51 1 And the upper surface S of the second dielectric layer 7 3 The metal silicide layer 52 is located on the upper surface S of the contact plug 51 1 . That is, the polysilicon material is higher than the upper surface S of the second dielectric layer 7 3 The portion of the lying plane is entirely metallized to constitute a metal silicide layer 52. The polysilicon material is positioned on the upper surface S of the second dielectric layer 7 3 The portion on and below the flat surface constitutes the contact plug 51. Thus, the upper surface S of the contact plug 51 1 Is a plane, the upper surface of the contact plug 51 is the upper surface S of the contact plug 51 1 。
In another example, as shown in fig. 4, the upper surface S of the contact plug 51 is contacted 1 Is higher than the upper surface S of the second dielectric layer 7 3 The metal silicide layer 52 covers the surface of the portion of the contact plug 51 above the second dielectric layer 7. That is, the polysilicon material is higher than the upper surface S of the second dielectric layer 7 3 Of parts of planeThe surface is metallized to form a metal silicide layer 52. The unmetallized portions of the polysilicon material constitute contact plugs 51. As such, the upper surface of the contact plug 51 is convex, and the upper surface of the contact plug 51 includes the upper surface S of the contact plug 51 1 And on the upper surface S of the second dielectric layer 7 3 Above the plane and with the upper surface S of the contact plug 51 1 Adjacent side surfaces.
In one example, as shown in fig. 3 and 4, the contact pad 53 includes: an adhesive layer 531 and a pad conductive layer 532. The adhesion layer 531 is located on the surface of the bit line 3 after removing part of the sidewall and the surface of the metal silicide layer 52, and the adhesion layer 531 partially extends between the metal silicide layer 52 and the bit line 3. The pad conductive layer 532 is positioned on the surface of the adhesive layer 531.
Here, the surface of the bit line 3 after removing part of the sidewall refers to: the surface of the sidewall structure 32 of the bit line 3 after the material is partially removed. This allows the gap between adjacent bitlines 3 to be of a larger dimension than before the sidewalls of the unremoved portions to ensure a larger orthographic area of contact pad 53 on substrate 1. Thereby facilitating to ensure that the storage node contact structure 5 has good conductivity even after further shrinking the DRAM size.
Alternatively, as shown in fig. 3, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323, which are stacked in a direction away from the bit line structure 31. The top surface of the first dielectric layer 6 is flush or substantially flush with the top surface of the metal suicide layer 52. The foregoing removing of a portion of the sidewall of the bit line 3 includes removing a portion or all of the material of the second silicon nitride layer 323 and the silicon oxide layer 322 above the plane of the top surface of the metal silicide layer 52. As such, a portion of the surface of the adhesion layer 531 may be in direct contact with the surface of the first silicon nitride layer 321.
Alternatively, as shown in fig. 4, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323, which are stacked in a direction away from the bit line structure 31. The second silicon nitride layer 323 may be used as the first dielectric layer 6 in the foregoing example. The second dielectric layer 7 is located on the surface of the second silicon nitride layer 323. The foregoing removing of a portion of the sidewall of the bit line 3 includes removing a portion or all of the material of the second silicon nitride layer 323 and the silicon oxide layer 322 above the plane of the top surface of the metal silicide layer 52. For example, all material of the second silicon nitride layer 323 above the plane of the top surface of the metal silicide layer 52 is removed such that the top surface of the second silicon nitride layer 323 is flush or substantially flush with the top surface of the metal silicide layer 52. A portion of the silicon oxide layer 322 above the plane of the top surface of the metal silicide layer 52 is removed. As such, a portion of the surface of the adhesion layer 531 may be in direct contact with the surface of the first silicon nitride layer 321.
Further, the adhesion layer 531 may optionally include, but is not limited to, a titanium nitride (TiN) layer.
Optionally, the pad conductive layer 532 includes a metal layer. The material of the pad conductive layer 532 is, for example, at least one of tungsten (W), cobalt (Co), molybdenum (Mo), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), and lanthanum (La).
Referring to fig. 5, an embodiment of the present disclosure provides a method for fabricating a semiconductor structure 100 in some embodiments described above. The preparation method comprises the following steps.
S11: a substrate is provided, and a plurality of bit lines arranged at intervals in parallel are formed on the substrate.
S12: contact plugs are formed between adjacent bit lines, and a metal silicide layer is formed on upper surfaces of the contact plugs. The upper surface of the contact plug is lower than the upper surface of the bit line, and a gap is formed between the metal silicide layer and the bit line.
S13: and forming a contact pad on the metal silicide layer, wherein the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure. The contact pad portion extends into the gap, and the length of the part of the contact pad extending into the gap is less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit line.
In an embodiment of the present disclosure, a gap is formed between the metal silicide layer and the bit line, and a contact pad is formed on the metal silicide layer such that a portion of the contact pad extends into the gap. This allows a larger contact area between the contact pad and the metal silicide layer, and allows an air gap to remain between the metal silicide layer and the bit line. Therefore, the contact resistance between the contact pad and the contact plug can be reduced, the risk of electric leakage of the storage node contact structure is reduced by using the air gap, and the parasitic capacitance between the storage node contact structure and the bit line is reduced. Thereby effectively improving the electrical performance of the semiconductor structure and improving the yield of the semiconductor structure.
In step S11, referring to S11 in fig. 5 and fig. 6, a substrate 1 is provided, and a plurality of bit lines 3 arranged in parallel and at intervals are formed on the substrate 1.
In one example, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. The substrate 1 is provided with a shallow trench isolation structure 10, and the shallow trench isolation structure 10 is, for example, silicon oxide (SiO) 2 ) And an isolation structure. The shallow trench isolation structure 10 isolates a plurality of active regions 2 arranged in an array in the substrate 1, and the active regions 2 include a source region and a drain region. The material of the active region 2 is, for example, polysilicon (poly), and the source region and the drain region of the active region 2 are doped regions of polysilicon.
Alternatively, as shown in fig. 6, the bit line 3 includes a bit line structure 31 and a sidewall structure 32. The bit line structure 31 includes: a conductive portion coupled corresponding to the source region of the active region 2, and an insulating portion covering the top surface of the conductive portion. The sidewall structures 32 include at least one dielectric layer. The material of the insulating portion and the dielectric layer is, for example, silicon oxide (SiO) 2 ) Or silicon nitride (Si) x N y ) At least one of (1). The conductive portion may have a single-layer structure or a stacked-layer structure, and the material of the conductive portion includes, for example, at least one of polysilicon or metal.
In addition, optionally, as shown in fig. 6, the bottom of some bit line structures 31 extends into the substrate 1 and is coupled to the corresponding source region, the peripheral side of the bottom of the bit line structure 31 is further provided with an insulating layer 11 filled in the substrate 1, and the material of the insulating layer 11 is, for example, silicon oxide (SiO) for example 2 ) Or silicon nitride (Si) x N y ) At least one of (1).
In step (b)In step S12, referring to S12 in fig. 5 and fig. 7, a contact plug 51 is formed between adjacent bit lines 3, and a metal silicide layer 52 is formed on an upper surface of the contact plug 51. Upper surface S of contact plug 51 1 Lower than the upper surface S of the bit line 3 2 The metal silicide layer 52 has a gap L with the bit line 3.
Here, the upper surface of the contact plug 51 includes the upper surface S of the contact plug 51 1 . For example, the upper surface of the contact plug 51 is the upper surface S of the contact plug 51 1 Alternatively, the upper surface of the contact plug 51 is the upper surface S of the contact plug 51 1 And an upper surface S 1 Adjacent side surfaces of the base.
In addition, the contact plug 51 is coupled to the drain region of the active region 2, and the contact plug 51 is, for example, a polysilicon layer. The metal silicide layer 52 is, for example, a cobalt silicide (CoSi) layer.
In step S13, referring to S13 in fig. 5 and fig. 8, a contact pad 53 is formed on the metal silicide layer 52. Contact pad 53 extends partially into the gap L, and contact pad 53 extends to a length L of the portion within the gap L 1 A height H less than the clearance L L So that an air gap G remains between the metal silicide layer 52 and the bit line 3.
Height H of air gap G G The settings can be selected according to actual requirements. Optionally, the height H of the air gap G G Height H of gap L L 20 to 80 percent of the total weight of the composition. For example, the height H of the air gap G G Height H of gap L L 20%, 40%, 60% or 80%.
From above, the contact pad 53 constitutes the storage node contact structure 5 together with the metal silicide layer 52 and the contact plug 51.
In one example, referring to fig. 9, step S12 forms a contact plug between adjacent bit lines and a metal silicide layer on an upper surface of the contact plug, the metal silicide layer having a gap with the bit lines, including the following steps.
S121: and forming a first dielectric layer on the side wall of the bit line, and forming a second dielectric layer on the surface of the first dielectric layer. The material of the second dielectric layer is different from the material of the first dielectric layer.
S122: contact plugs are formed between adjacent bit lines.
S123: and removing part of the second dielectric layer to form a gap between the contact plug and the first dielectric layer, wherein part of the contact plug is exposed out of the gap.
S124: and forming a metal layer on the exposed surface of the contact plug.
S125: and annealing the obtained structure to obtain the metal silicide layer.
S126: and removing the residual metal layer to expose the gap.
In the embodiment of the disclosure, the metal silicide layer is obtained by metalizing part of the material of the contact plug, so that the manufacturing process of the metal silicide layer can be simplified. And forming a first dielectric layer and a second dielectric layer which are made of different materials on the side wall of the bit line so as to expose the surface of the contact plug to be metalized by utilizing the removing space of the second dielectric layer and form a gap between the metal silicide layer and the first dielectric layer, thereby reducing the process difficulty of forming the metal silicide layer and the gap.
In step S121, please refer to S121 in fig. 9 and fig. 10, a first dielectric layer 6 is formed on the sidewall of the bit line 3, and a second dielectric layer 7 is formed on the surface of the first dielectric layer 6. The material of the second dielectric layer 7 is different from the material of the first dielectric layer 6.
Here, the first dielectric layer 6 and the second dielectric layer 7 may be obtained by, but not limited to, a deposition process. The first dielectric layer 6 includes, but is not limited to, a silicon nitride layer. The second dielectric layer 7 includes, but is not limited to, a silicon oxide layer.
It is to be understood that, in another example, as shown in fig. 11, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 which are stacked in a direction away from the bit line structure 31. Thus, under the condition that the thickness of the second silicon nitride layer 323 meets the use requirement, the first dielectric layer 6 can be directly replaced by the second silicon nitride layer 323, that is, the first dielectric layer 6 does not need to be formed on the sidewall structure 32 of the bit line 3, and the second dielectric layer 7 can be directly formed on the surface of the second silicon nitride layer 323. The material of the second dielectric layer 7 is different from that of the second silicon nitride layer 323, for example, the second dielectric layer 7 is a silicon oxide layer.
In step S122, please refer to S122 in fig. 9 and fig. 12, a contact plug 51 is formed between adjacent bit lines 3.
Here, the contact plug 51 may be obtained by, but not limited to, a deposition process and an etching process.
Illustratively, as shown in fig. 12 (a), a contact plug material layer 510 is deposited on the substrate 1, such that the contact plug material layer 510 fills the gap between every two adjacent bit lines 3 and covers the bit lines 3. As shown in fig. 12 (b), the contact plug material layer 510 is etched by an etching process to form the contact plug 51. The etching process is, for example, wet etching.
Alternatively, as shown in (b) of fig. 12, the height H of the contact plug 51 C Is the bit line 3 height H W 10 to 80 percent of the total weight of the composition. For example, the height H of the contact plug 51 C Is the bit line 3 height H W 10%, 20%, 50%, 60% or 80%.
In step S123, please refer to S123 in fig. 9 and fig. 13, a portion of the second dielectric layer 7 is removed to form a gap L between the contact plug 51 and the first dielectric layer 6, wherein the gap L exposes a portion of the contact plug 51.
Illustratively, the second dielectric layer 7 is a silicon oxide layer. Part of the material of the second dielectric layer 7 is removed by wet etching, for example, using a hydrofluoric acid diluted solution. The material of the first dielectric layer 6 is different from that of the second dielectric layer 7, and the first dielectric layer 6 can be used as an etching barrier layer in the etching process under the condition that part of the second dielectric layer 7 is removed by etching.
Optionally, the height of the removed portion of the second dielectric layer 7 is 20% to 80% of the initial height of the second dielectric layer 7. For example, the height of the removed portion of the second dielectric layer 7 is 20%, 40%, 60%, or 80% of the original height of the second dielectric layer 7.
Here, the height of the removed portion of the second dielectric layer 7 is different, and the surface area of the metal silicide layer 52 to be formed later for contacting the contact pad 53 is different. For example, the larger the height dimension of the removed portion of the second dielectric layer 7, the larger the height dimension of the gap L formed between the contact plug 51 and the first dielectric layer 6. Thus, the larger the exposed surface area of the contact plug 51, the larger the surface area of the metal silicide layer 52 that can be obtained, with the cross-sectional dimension of the gap L being constant. On this basis, it is advantageous to make the portion of the contact pad 53 to be formed later, which extends into the gap L, have a larger height dimension by using the gap L having a larger height dimension, so as to ensure that the contact area between the metal silicide layer 52 and the contact pad 53 to be formed later can be larger.
In one example, referring to fig. 14, the method for fabricating a semiconductor structure further includes: portions of the first dielectric layer 6, and portions of the sidewalls of the bit lines 3, are removed. This allows the gap between adjacent bit lines 3 to have a larger dimension than before the portions of the first dielectric layer 6 and the sidewalls of the bit lines 3 are not removed, thereby ensuring that the subsequently formed contact pads 53 have a larger orthographic projection area on the substrate 1. Thereby facilitating to ensure that the storage node contact structure 5 has good conductivity even after further shrinking the DRAM size.
Optionally, a portion of the first dielectric layer 6 is removed, so that the top surface of the first dielectric layer 6 is flush or substantially flush with the upper surface (surface before the metallization process) of the contact plug 51 at the present stage.
Alternatively, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323, which are stacked in a direction away from the bit line structure 31. Removing part of the sidewall of the bit line 3 includes removing part or all of the material of the second silicon nitride layer 323 and the silicon oxide layer 322 that is higher than the plane of the upper surface (surface before the metallization process) of the contact plug 51 at the present stage.
In step S124, please refer to S124 in fig. 9 and fig. 15, a metal layer 512 is formed on the exposed surface of the contact plug 51.
Optionally, the thickness of the metal layer 512 is 5nm to 16nm. For example, the thickness of the metal layer 512 is 5nm, 8nm, 10nm, 12nm, or 16nm.
Alternatively, the material of the metal layer 512 includes, but is not limited to, metal cobalt (Co).
In addition, the metal layer 512 may be prepared by, but not limited to, a deposition process. Moreover, the film formation quality of the metal layer 512 is related to the process parameters of the deposition process.
In one example, as shown in fig. 16, the metal layer 512 covers the exposed surface of the contact plug 51 and fills the gap between the contact plug 51 and the first dielectric layer 6. In this way, the metal layer 512 is easily densified, thereby facilitating the sufficient metallization of the exposed surface of the contact plug 51.
In another example, as shown in fig. 17, the metal layer 512 covers the exposed surface of the contact plug 51, and a portion of the metal layer 512 located in the gap between the contact plug 51 and the first dielectric layer 6 has a void V. Thus, the void V in the metal layer 512 facilitates the subsequent processes to remove the residual metal layer 512.
In step S125, please refer to S125 in fig. 9 and fig. 18, an annealing process is performed on the resulting structure to obtain the metal silicide layer 52.
Optionally, the annealing temperature for annealing the resulting structure is 300 ℃ to 700 ℃, for example 300 ℃, 500 ℃, or 700 ℃.
In step S126, please refer to S126 in fig. 9 and fig. 19, the remaining metal layer 512 is removed to expose the gap L.
Here, the residual metal layer 512 refers to a metal element, such as metallic cobalt, still remaining on the surface of the contact plug material layer 510 after the annealing process.
In addition, the remaining metal layer 512 may be removed by a wet etching process, for example, by cleaning with a diluted sulfur peroxide mixed solution. The diluted sulfur peroxide mixed solution comprises: sulfuric acid (H) 2 SO 4 ) Hydrogen peroxide (H) 2 O 2 ) And water (H) 2 O)。
It is to be added that after annealing the resulting structure, part of the material of the contact plug 51 is metallized, in particular the exposed surface portions of the contact plug 51. Therefore, the cross-sectional shape of the metal silicide layer 52 is related to the degree of metallization of the contact plug 51.
In one example, referring to fig. 20, annealing the resulting structure to obtain a metal silicide layer 52 includes: the resulting structure is annealed so that the exposed portion of the contact plug 51 reacts with the metal layer 512 to be entirely converted into the metal silicide layer 52. The cross-sectional shape of the metal silicide layer 52 is, for example, rectangular.
In another example, referring to fig. 21, annealing the resulting structure to obtain a metal silicide layer 52 includes: the resulting structure is annealed so that the exposed portion of the contact plug 51 reacts with the metal layer 512 to form a metal silicide layer 52 on the exposed portion of the surface of the contact plug 51. The cross-sectional shape of the metal silicide layer 52 is, for example, an inverted U-shape.
In one example, referring to fig. 22, step S13 forms a contact pad on the metal silicide layer, including the steps described below.
S131: and forming an adhesion layer on the surface of the bit line after the part of the side wall of the bit line is removed and the surface of the metal silicide layer, wherein the adhesion layer partially extends into the gap, and the part of the adhesion layer extending into the gap is the part of the contact pad extending into the gap.
S132: and forming a pad conductive layer on the surface of the adhesion layer.
In the embodiment of the disclosure, the adhesion layer is formed on the surface of the removed part of the sidewall of the bit line and the surface of the metal silicide layer, and then the pad conductive layer is formed on the surface of the adhesion layer, so that the adhesion capability between the pad conductive layer and the metal silicide layer, and between the pad conductive layer and the sidewall of the bit line, can be enhanced by using the adhesion layer, and on the basis of ensuring that the contact pad has good conductivity, the contact pad, the metal silicide layer and the sidewall of the bit line are well connected, thereby ensuring the use reliability of the semiconductor structure. In addition, the adhesion layer partially extends into the gap, so that the contact area of the contact pad and the metal silicide layer can be increased, and the contact resistance between the contact pad and the metal silicide layer is reduced. And, the contact pad is connected with the contact plug through the metal silicide layer, can utilize the metal silicide layer to reduce the contact resistance between contact pad and the contact plug.
In step S131, please refer to S131 in fig. 22, fig. 23 and fig. 24, an adhesion layer 531 is formed on the surface of the bit line 3 after removing a portion of the sidewall and the surface of the metal silicide layer 52. The adhesion layer 531 partially extends into the gap L, and the portion of the adhesion layer 531 extending into the gap L is the portion of the contact pad 53 extending into the gap L.
Alternatively, the material of the adhesion layer 531 includes, but is not limited to, titanium nitride. The adhesion layer 531 is also referred to as a metal barrier layer.
Here, the adhesive layer 531 serves to seal the gap L to leave the air gap G within the gap L. The adhesion layer 531 may be prepared by, but not limited to, a deposition process. By controlling the deposition rate of the adhesive layer 531, the molding height of the air gap G can be controlled.
In step S132, referring to S132 in fig. 22 and fig. 23 and 24, a pad conductive layer 532 is formed on the surface of the adhesion layer 531.
Alternatively, the material of the pad conductive layer 532 includes, but is not limited to, metal tungsten (W).
Thereby, the adhesive layer 531 and the pad conductive layer 532 constitute the contact pad 53.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (20)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein a plurality of bit lines which are arranged at intervals in parallel are formed on the substrate;
forming a contact plug between adjacent bit lines and forming a metal silicide layer on the upper surface of the contact plug; the upper surface of the contact plug is lower than the upper surface of the bit line, and a gap is formed between the metal silicide layer and the bit line;
forming a contact pad on the metal silicide layer, wherein the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure; the contact pad portion extends into the gap, and a length of the contact pad portion extending into the gap is less than a height of the gap, so that an air gap remains between the metal silicide layer and the bit line.
2. The method of claim 1, wherein forming a contact plug between adjacent bitlines and forming a metal silicide layer on an upper surface of the contact plug, the metal silicide layer having a gap with the bitlines comprises:
forming a first dielectric layer on the side wall of the bit line, and forming a second dielectric layer on the surface of the first dielectric layer; the material of the second dielectric layer is different from that of the first dielectric layer;
forming a contact plug between adjacent bit lines;
removing part of the second dielectric layer to form a gap between the contact plug and the first dielectric layer, wherein part of the contact plug is exposed from the gap;
forming a metal layer on the exposed surface of the contact plug;
annealing the obtained structure to obtain a metal silicide layer;
and removing the residual metal layer to expose the gap.
3. The method for fabricating a semiconductor structure according to claim 2, further comprising, before forming the metal layer on the exposed surface of the contact plug:
and removing part of the first dielectric layer and part of the side wall of the bit line.
4. The method of claim 2, wherein the step of forming the semiconductor structure comprises,
the metal layer covers the exposed surface of the contact plug and fills the gap;
or, the metal layer covers the exposed surface of the contact plug, and the part of the metal layer in the gap is provided with a pore.
5. The method for fabricating a semiconductor structure according to claim 2, wherein the annealing the resulting structure to obtain a metal silicide layer comprises:
and annealing the obtained structure, so that the exposed part of the contact plug reacts with the metal layer and is completely converted into the metal silicide layer.
6. The method for fabricating a semiconductor structure according to claim 2, wherein the annealing the resulting structure to obtain a metal silicide layer comprises:
and annealing the obtained structure to enable the exposed part of the contact plug to react with the metal layer so as to form the metal silicide layer on the exposed part of the surface of the contact plug.
7. The method of claim 2, wherein the step of forming the semiconductor structure comprises,
the first dielectric layer comprises a silicon nitride layer, and the second dielectric layer comprises a silicon oxide layer;
the bit line comprises a bit line structure and a side wall structure; the side wall structure comprises at least one dielectric layer, and the material of the outermost dielectric layer of the side wall structure is the same as that of the first dielectric layer.
8. The method for manufacturing a semiconductor structure according to claim 2, wherein the annealing temperature for annealing the resultant structure is 300 ℃ to 700 ℃.
9. The method of fabricating a semiconductor structure according to any one of claims 2 to 8, wherein said forming a contact pad on said metal silicide layer comprises:
forming an adhesion layer on the surface of the bit line after the partial side wall of the bit line is removed and on the surface of the metal silicide layer, wherein the adhesion layer partially extends into the gap, and the part of the adhesion layer extending into the gap is the part of the contact pad extending into the gap;
and forming a pad conductive layer on the surface of the adhesion layer.
10. The method of claim 9, wherein the adhesion layer comprises a titanium nitride layer and the pad conductive layer comprises a metal layer.
11. The method of claim 1, wherein the metal silicide layer comprises a cobalt silicide layer.
12. The method of claim 1, wherein the height of the air gap is 20% to 80% of the height of the gap.
13. A semiconductor structure, comprising:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the bit lines are arranged on the substrate at intervals in parallel;
and a storage node contact structure including a contact plug, a metal silicide layer, and a contact pad; wherein the contact plug is positioned between adjacent bit lines, and the upper surface of the contact plug is lower than that of the bit line; the metal silicide layer is positioned on the upper surface of the contact plug, and an air gap is formed between the metal silicide layer and the bit line; the contact pad is located on the metal silicide layer, and part of the contact pad extends to the position between the metal silicide layer and the bit line and is located above the air gap.
14. The semiconductor structure of claim 13, further comprising:
the first dielectric layer is positioned on the surface of the bit line and is positioned between the bit line and the storage node contact structure;
and the second dielectric layer is positioned on the surface of the first dielectric layer, is positioned between the first dielectric layer and the storage node contact structure and is positioned below the air gap.
15. The semiconductor structure of claim 14, wherein the first dielectric layer comprises a silicon nitride layer and the second dielectric layer comprises a silicon oxide layer; the metal silicide layer includes a cobalt silicide layer.
16. The semiconductor structure of claim 14, wherein an upper surface of the contact plug is flush with an upper surface of the second dielectric layer, and the metal silicide layer is located on the upper surface of the contact plug.
17. The semiconductor structure of claim 14, wherein an upper surface of the contact plug is higher than an upper surface of the second dielectric layer, and the metal silicide layer covers a surface of a portion of the contact plug located above the second dielectric layer.
18. The semiconductor structure of any of claims 14 to 17, wherein the contact pad comprises:
the adhesion layer is positioned on the surface of the bit line after the partial side wall of the bit line is removed and on the surface of the metal silicide layer, and the adhesion layer partially extends to the position between the metal silicide layer and the bit line;
and the pad conducting layer is positioned on the surface of the adhesion layer.
19. The semiconductor structure of claim 18, wherein the adhesion layer comprises a titanium nitride layer and the pad conductive layer comprises a metal layer.
20. The semiconductor structure of claim 13, wherein a height of the air gap is 20% to 80% of a height of a gap between the metal silicide layer and the bit line.
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