CN116489992A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN116489992A CN116489992A CN202310728352.8A CN202310728352A CN116489992A CN 116489992 A CN116489992 A CN 116489992A CN 202310728352 A CN202310728352 A CN 202310728352A CN 116489992 A CN116489992 A CN 116489992A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 258
- 238000002360 preparation method Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 33
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 31
- 230000007704 transition Effects 0.000 claims description 25
- -1 germanium ions Chemical class 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910001432 tin ion Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 15
- 230000015654 memory Effects 0.000 abstract description 13
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 230000008054 signal transmission Effects 0.000 abstract description 9
- 238000003860 storage Methods 0.000 abstract description 9
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 281
- 239000003990 capacitor Substances 0.000 description 61
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 14
- 229910052760 oxygen Inorganic materials 0.000 description 14
- 239000001301 oxygen Substances 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910000676 Si alloy Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The semiconductor structure adopts metal ions to dope the semiconductor column, forms a doped part in the semiconductor column, effectively avoids the semiconductor column from being oxidized in the process of the semiconductor structure, and reduces or avoids generating an oxide layer which influences the electric signal transmission between the semiconductor column and the conductive structure. And forming a conductive structure on the semiconductor column, wherein the conductive structure is in contact conduction with the semiconductor column. Therefore, the blocking of electric signal transmission between the conductive structure and the semiconductor column can be effectively avoided, and the transmission performance of the electric signal between the conductive structure and the semiconductor column is improved, so that the storage performance of the semiconductor structure when the semiconductor structure is a memory is improved.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.
Background
A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses.
The DRAM comprises a plurality of memory cells, each memory cell comprises a transistor and a capacitor which are arranged on a substrate, a source region of the transistor is connected with a bit line, a drain region of the transistor is connected with the capacitor, and a grid electrode of the transistor is connected with a word line. The transistor stores data information of the bit line in the capacitor under control of the word line, or reads the data information stored in the capacitor through the bit line. The drain region is connected with the capacitor plug, the electrode of the capacitor is connected with the capacitor contact pad, and the capacitor plug is connected with the capacitor contact pad, so that signal transmission between the drain region and the capacitor is realized.
However, the contact resistance between the capacitor contact pad and the capacitor plug is large, which affects the signal transmission between the capacitor and the drain region, and thus affects the memory performance of the DRAM.
Disclosure of Invention
The semiconductor structure and the preparation method thereof can effectively reduce the contact resistance between the semiconductor column and the conductive structure, are beneficial to improving the electric signal transmission performance between the semiconductor column and the conductive structure, and improve the storage performance when the semiconductor structure is a memory.
In a first aspect, the present disclosure provides a method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein an isolation layer and a plurality of semiconductor columns arranged in an array are arranged in the substrate, and the isolation layer at least covers the side walls of the semiconductor columns;
doping the semiconductor column by adopting metal ions, and forming a doped part in the semiconductor column;
and forming a conductive structure, wherein the conductive structure is positioned on the semiconductor column and is in contact conduction with the semiconductor column.
In the above method for manufacturing a semiconductor structure, optionally, forming the doped portion includes:
and doping the top surface of the semiconductor column, wherein the formed doped part is positioned in the semiconductor column and close to the top surface of the semiconductor column.
In the above method for manufacturing a semiconductor structure, optionally, the metal ion includes at least one of germanium ion, tin ion, aluminum ion, titanium ion, and arsenic ion.
In the above method for manufacturing a semiconductor structure, optionally, forming the conductive structure includes:
forming a first conductive layer, wherein the first conductive layer is positioned on the semiconductor column and is in contact conduction with the top surface of the semiconductor column;
the first conductive layer forms a contact transition layer with the semiconductor pillars.
In the above method for manufacturing a semiconductor structure, optionally, forming the conductive structure includes:
forming a second conductive layer, wherein the second conductive layer is positioned on the first conductive layer;
forming a third conductive layer, wherein the third conductive layer is positioned on the second conductive layer and is in contact conduction with the second conductive layer;
the second conductive layer is of a different material than the third conductive layer.
In the above method for manufacturing a semiconductor structure, before forming the second conductive layer, optionally, the method further includes:
forming a fourth conductive layer, wherein the fourth conductive layer is positioned on the first conductive layer and is in contact conduction with the first conductive layer;
forming the second conductive layer, comprising: the second conductive layer at least covers the top surface of the fourth conductive layer;
the materials of the fourth conductive layer, the second conductive layer and the third conductive layer are different, and the contact transition layer, the second conductive layer, the third conductive layer and the fourth conductive layer jointly form the conductive structure.
In the above method for manufacturing a semiconductor structure, optionally, the material of the semiconductor pillar includes polysilicon; and/or the material of the first conductive layer comprises cobalt; and/or the material of the second conductive layer comprises titanium nitride; and/or the material of the third conductive layer comprises tungsten; and/or the material of the fourth conductive layer comprises titanium.
In the above method for manufacturing a semiconductor structure, optionally, providing the substrate includes:
forming a substrate, wherein the substrate comprises a plurality of active areas which are arranged in an array, and an isolation structure is arranged between the adjacent active areas;
forming an isolation layer, wherein the isolation layer covers the top surface of the substrate, a plurality of contact grooves are arranged in an array manner in the isolation layer, and the plurality of contact grooves expose a plurality of active areas in a one-to-one correspondence manner;
forming the semiconductor columns, wherein a plurality of the semiconductor columns are located in the contact grooves in a one-to-one correspondence manner, the side walls of the semiconductor columns are abutted against the isolation layers, and the semiconductor columns are in contact conduction with the corresponding exposed active areas;
wherein the top surface of the semiconductor column is lower than the top surface of the isolation layer.
In the above method for manufacturing a semiconductor structure, optionally, the semiconductor pillar is a contact plug, and the conductive structure is a capacitor contact pad;
after forming the conductive structure, the method further comprises:
and forming a capacitor, wherein the capacitor is positioned on the conductive structure, and one electrode of the capacitor is in contact conduction with the conductive structure.
In a second aspect, the present disclosure provides a semiconductor structure comprising:
the semiconductor device comprises a substrate, wherein an isolation layer and a plurality of semiconductor columns arranged in an array are arranged in the substrate, and the isolation layer at least covers the side walls of the semiconductor columns; the semiconductor column is provided with a doping part doped with metal ions;
and the conductive structure is positioned on the semiconductor column and is in contact conduction with the semiconductor column.
In the above semiconductor structure, optionally, the doped portion is a position in the semiconductor structure near the top surface of the semiconductor pillar.
In the above semiconductor structure, optionally, the conductive structure includes a first conductive layer, and a contact transition layer is disposed between the first conductive layer and the semiconductor pillar, and the contact transition layer is located on a top surface of the semiconductor pillar and is in contact conduction with the semiconductor pillar.
In the above semiconductor structure, optionally, the conductive structure further includes a second conductive layer and a third conductive layer, where the second conductive layer and the third conductive layer are sequentially stacked on the first conductive layer, and the second conductive layer is in contact and conduction with the first conductive layer; the second conductive layer and the third conductive layer are different in material;
or, the conductive structure further comprises a fourth conductive layer, a second conductive layer and a third conductive layer, wherein the fourth conductive layer, the second conductive layer and the third conductive layer are sequentially stacked on the first conductive layer, and the materials of the fourth conductive layer, the second conductive layer and the third conductive layer are different from each other.
In the above semiconductor structure, optionally, the substrate includes a substrate, where the substrate includes a plurality of active regions arranged in an array, and an isolation structure is disposed between adjacent active regions;
the isolation layers and the semiconductor columns are arranged on the substrate, the semiconductor columns are in contact conduction with the active regions in a one-to-one correspondence manner, and the isolation layers are positioned between the adjacent semiconductor columns and are abutted against the side walls of the semiconductor columns;
wherein the top surface of the semiconductor column is lower than the top surface of the isolation layer.
In the above semiconductor structure, optionally, the semiconductor pillar is a contact plug, and the conductive structure is a capacitive contact pad;
the semiconductor structure further comprises a capacitor, the capacitor is arranged on the conductive structure, and one electrode of the capacitor is in contact conduction with the conductive structure.
The present disclosure provides a semiconductor structure and a method of fabricating the same, by disposing a plurality of semiconductor pillars in a substrate, covering an isolation layer on sidewalls of the semiconductor pillars, effectively protecting the semiconductor pillars by using the isolation layer, and avoiding electrical signal interference between adjacent semiconductor pillars. The semiconductor column is doped with metal ions, and the metal ions react with oxygen in the process environment in the process of the semiconductor structure, so that the reaction of the semiconductor column and the oxygen is effectively reduced or avoided to generate an oxide layer. By arranging the conductive structure on the semiconductor column, the conductive structure is in contact conduction with the semiconductor column. Therefore, the electronic transmission between the semiconductor column and the conductive structure can be reduced or prevented from being influenced by the oxide layer, and the transmission performance of the electric signal between the semiconductor column and the conductive structure is improved, so that the storage performance of the semiconductor structure when the semiconductor structure is a memory is improved.
The construction of the present disclosure, together with other objects and advantages thereof, will be best understood from the following description of the preferred embodiments when read in connection with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a related art semiconductor pillar and conductive structure connection location;
fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 3 is a schematic view of a substrate structure with a contact trench of a semiconductor structure according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of forming a doped portion of a semiconductor structure according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of forming a first conductive layer and a second conductive layer of a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of forming a third conductive layer of the semiconductor structure according to the embodiments of the present disclosure;
fig. 7 is a schematic structural view of a semiconductor structure according to an embodiment of the present disclosure;
fig. 8 is a schematic structural view of a semiconductor structure and a connection position of a conductive structure of the semiconductor structure according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of forming a capacitor of a semiconductor structure according to an embodiment of the present disclosure;
fig. 10 is a schematic structural view of a semiconductor structure according to another embodiment of the present disclosure, in which a fourth conductive layer and a second conductive layer are formed;
fig. 11 is a schematic structural view of a semiconductor structure according to another embodiment of the present disclosure, in which a third conductive layer is formed;
fig. 12 is a schematic structural view of a semiconductor structure according to another embodiment of the present disclosure.
Reference numerals illustrate:
100. a substrate; 100a, an active region; 100b, isolation structures; 200. an isolation layer; 201. an air gap; 300. a semiconductor pillar; 301. a doping section; 400. a conductive structure; 401. a first conductive layer; 402. a second conductive layer; 402a, grooves; 403. a third conductive layer; 404. a fourth conductive layer; 405. contacting the transition layer; 500. a capacitor; 501. a first electrode layer; 502. a capacitance dielectric layer; 503. a second electrode layer; 600. a bit line; 700. a contact trench; an L1-oxide layer; l2-a first dielectric layer; l3-a second dielectric layer.
Detailed Description
An active region is disposed in a substrate of the DRAM device, the active region including a source region, a channel, and a drain region, the source region being connected to the bit line, the channel corresponding to the gate, the drain region being connected to the capacitor. The gate may control the storage of signals in the bit line into the capacitor or the reading of signals stored in the capacitor. A capacitor plug (or, a storage node plug Storage node contact, abbreviated as SNC) and a capacitor contact pad (LP) may be disposed between the capacitor and the drain region. The drain region, the capacitor plug, the capacitor contact pad and the capacitor electrode are sequentially contacted and conducted, so that signal transmission of the drain region and the capacitor is realized. Referring to fig. 1, the capacitor plug is made of a semiconductor material, i.e., the semiconductor pillar 300 in fig. 1, and the capacitor contact pad is made of a metal material, i.e., the conductive structure 400 in fig. 1. In the process of the DRAM, the semiconductor pillars 300 are formed on a substrate (not shown in fig. 1), and the sidewalls of the semiconductor pillars 300 are provided with the isolation layer 200. After the formation of the semiconductor pillars 300, the semiconductor pillars 300 may be exposed to oxygen or water oxygen in the atmospheric environment before the formation of the conductive structures 400, thereby generating native oxides (native oxides), and forming an oxide layer L1 at the top positions of the semiconductor pillars 300. After the first conductive layer 401 and the second conductive layer 402 are formed subsequently, the oxide layer L1 prevents the conduction between the semiconductor pillar 300 and the first conductive layer 401, thereby reducing or isolating the electron transfer between the conductive structure 400 and the semiconductor pillar 300. Referring to fig. 1, electrons e cannot reach the first conductive layer 401 from the semiconductor pillar 300 due to the presence of the oxide layer L1. Alternatively, the semiconductor pillar 300 cannot be reached by the first conductive layer 401.
Wherein the first conductive layer 401 may be cobalt (Co), and the second conductive layer 402 may be titanium nitride (TiN). The first conductive layer 401 may form an alloy layer with the semiconductor pillar 300 (for example, the semiconductor pillar 300 is silicon, the alloy layer may be cobalt-silicon alloy layer CoSi x ) The alloy layer may improve electron transport capability between the semiconductor pillars 300 and the first conductive layer 401. However, the oxide layer L1 prevents the formation of an alloy layer, further affecting electron transport between the semiconductor pillars 300 and the conductive structure 400. Therefore, signal transmission between the drain region and the capacitor is blocked, affecting the signal storage and reading process of the DRAM.
The present disclosure provides a semiconductor structure and a method of fabricating the same, by disposing a plurality of semiconductor pillars in a substrate, covering an isolation layer on sidewalls of the semiconductor pillars, effectively protecting the semiconductor pillars by using the isolation layer, and avoiding electrical signal interference between adjacent semiconductor pillars. The semiconductor column is doped with metal ions, and the metal ions react with oxygen in the process environment in the process of the semiconductor structure, so that the reaction of the semiconductor column and the oxygen is effectively reduced or avoided to generate an oxide layer. By arranging the conductive structure on the semiconductor column, the conductive structure is in contact conduction with the semiconductor column. Therefore, the electronic transmission between the semiconductor column and the conductive structure can be reduced or prevented from being influenced by the oxide layer, and the transmission performance of the electric signal between the semiconductor column and the conductive structure is improved, so that the storage performance of the semiconductor structure when the semiconductor structure is a memory is improved.
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the present disclosure. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present disclosure and are not to be construed as limiting the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure. Embodiments of the present disclosure are described in detail below with reference to the attached drawings.
In a first aspect, the present disclosure provides a method of fabricating a semiconductor structure. The semiconductor structure may be a memory, and the memory of the present disclosure may be an unlimited variety of memories including semiconductor pillars and conductive structures. The Memory may include DRAM, static random access Memory (Static Random Access Memory, SRAM), flash Memory, electrically Erasable Programmable Read Only Memory (EEPROM), phase change random access Memory (Phase Change Random Access Memory, PRAM), or Magnetoresistive Random Access Memory (MRAM). The following description will take a DRAM as an example of the semiconductor structure.
Fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure. Referring to fig. 2, the preparation method includes: s100: providing a substrate, wherein an isolation layer and a plurality of semiconductor columns arranged in an array are arranged in the substrate, and the isolation layer at least covers the side walls of the semiconductor columns.
Wherein, referring to fig. 3, a substrate is provided, comprising: the substrate 100 is formed, and the substrate 100 includes a plurality of active regions 100a arranged in an array, and an isolation structure 100b is disposed between adjacent active regions 100a. The substrate 100 may be monocrystalline Silicon, polycrystalline Silicon, amorphous Silicon, silicon germanium compound, silicon-on-insulator (SOI) or the like, or other materials known to those skilled in the art. The substrate 100 may provide a structural basis for supporting the subsequently disposed active region 100a, isolation layer 200, semiconductor pillars 300, conductive structures 400, and the like. The substrate 100 may be formed by deposition. For example, it may be a chemical vapor deposition process (Chemical Vapor Deposition, CVD for short), a physical vapor deposition process (Physical Vapor Deposition, PVD for short), an atomic layer deposition process (Atomic Layer Deposition, ALD for short), or the like.
The active region 100a in the substrate 100 may be formed by ion doping, and ions doped in the active region 100a may be a group III element (B or Ga) to form a P-type active region. Alternatively, the ions doped in the active region 100a may be a group V element (As or P), thereby forming an N-type active region. The present embodiment is not limited to the ion doping type of the active region 100a. The active regions 100a may be arranged at intervals in an array, and an isolation structure 100b may be formed between adjacent active regions 100a, where the isolation structure 100b may be shallow trench isolation (Shallow trench isolation, abbreviated as STI), and the isolation structure 100b may avoid electrical interference between two adjacent active regions 100a, so as to ensure performance stability of the semiconductor structure.
After forming the substrate 100, further comprising: the isolation layer 200 is formed, the isolation layer 200 covers the top surface of the substrate 100, and the isolation layer 200 has a plurality of contact trenches 700 arranged in an array therein, the plurality of contact trenches 700 exposing the plurality of active regions 100a in a one-to-one correspondence. The isolation layer 200 may be formed by deposition, and the material of the isolation layer 200 may include, but is not limited to, silicon nitride (SiN), silicon oxide (SiO) x ) Or an insulating material such as silicon oxynitride (SiON).
The following is a description of a specific structure of the separator 200. As an implementation manner, the isolation layer 200 may have a single-layer structure selected from the above-mentioned insulating materials. As another achievable embodiment, the isolation layer 200 may be a multi-layered structure. The multi-layered isolation layer 200 may include an oxide-nitride-oxide (ONO) layer or a nitride-oxide-nitride (NON) layer sequentially stacked in a direction from one to the other of the adjacent two contact trenches 700. As yet another possible implementation, an Air gap 201 (Air gap) may be provided in the isolation layer 200 (shown with reference to fig. 3 and 4). The isolation layer 200 can protect the semiconductor pillars 300 formed in the contact trench 700, and prevent electrical interference between adjacent semiconductor pillars 300.
Referring to fig. 3, the contact trench 700 may be formed by means of mask etching, and the contact trench 700 correspondingly exposes the active region 100a, i.e., exposes the top surface of the substrate 100 including the active region 100a. With continued reference to fig. 3, after forming the contact trench 700, further includes: forming semiconductor pillars 300, wherein the semiconductor pillars 300 are located in the contact trenches 700 in a one-to-one correspondence, the sidewalls of the semiconductor pillars 300 abut the isolation layer 200, and the semiconductor pillars 300 are in contact conduction with the corresponding exposed active regions 100 a; wherein the top surface of the semiconductor pillar 300 is lower than the top surface of the isolation layer 200. Note that, the semiconductor pillars 300 may be formed by deposition, and the material of the semiconductor pillars 300 may be polysilicon (Poly-Si). The top surface of the semiconductor pillar 300 is lower than the top surface of the isolation layer 200, and a certain space may be reserved in the contact trench 700 at a position located at the top of the semiconductor pillar 300 for the formation of the subsequent conductive structure 400. The isolation layer 200 may protect not only the semiconductor pillars 300 but also the conductive structures 400 formed later.
Referring to fig. 2 and 4, after forming the semiconductor pillar 300, it further includes: s200: the semiconductor column is doped with metal ions to form a doped portion in the semiconductor column. Optionally, forming the doped portion 301 includes: the top surface of the semiconductor pillar 300 is doped, and the doped portion 301 is formed at a position in the semiconductor pillar 300 near the top surface of the semiconductor pillar 300. As one achievable embodiment, the metal ions include at least one of germanium ions, tin ions, aluminum ions, titanium ions, and arsenic ions. The following description will be made taking germanium (Ge) as an example of the metal ion.
The doped portion 301 is formed by doping the semiconductor pillar 300 with metal ions, which are more active than the semiconductor. In the process of semiconductor structure, metal ions are more reactive with oxygen or water oxygen in the atmospheric environment than silicon ions at the top surface of the semiconductor pillars 300. Thus, germanium ions may react with oxygen instead of silicon ions at the top surface of semiconductor pillars 300, reducing or avoiding consumption of silicon ions and formation of silicon oxide.
Referring to fig. 4, the top surface of the semiconductor pillar 300 is doped along the contact trench 700 with metal ions, which may be ion-implanted, and the ion-implanted concentration of germanium ions may beThe ion implantation energy may be 10KeV. The ion implantation mode can be thermal diffusion, the annealing temperature in the thermal diffusion can be 550 ℃, and the annealing time can be 60 minutes. The concentration of the ion implantation of germanium ions may be 3-5% of the polysilicon of the semiconductor pillars 300.
When the doping concentration of the metal ions is too low or the energy of ion implantation is too low, insufficient metal ions react with oxygen, so that the subsequent oxygen can continue to combine with silicon ions, consume the silicon ions and simultaneously generate silicon oxide. When the doping concentration of the metal ions is too high or the energy of ion implantation is too high, the top surface of the semiconductor pillar 300 may form a single metal ion, which affects the ohmic contact structure between the semiconductor pillar 300 and the conductive structure 400 formed later, and thus may also affect the electrical signal transmission between the semiconductor pillar 300 and the conductive structure 400.
In some embodiments, the pressure of the deposition is controlled during the subsequent process of depositing the semiconductor pillars 300, so that the top surfaces of the semiconductor pillars 300 form a rugged structure, and thus the rugged top surface of the semiconductor pillars 300 is easily doped with metal ions, thereby easily forming the doped portion 301.
Referring to fig. 2 and 5, after forming the doped portion 301, the method further includes: s300: and forming a conductive structure, wherein the conductive structure is positioned on the semiconductor column and is in contact conduction with the semiconductor column. Optionally, forming the conductive structure 400 includes: forming a first conductive layer 401, wherein the first conductive layer 401 is positioned on the semiconductor column 300 and is in contact conduction with the top surface of the semiconductor column 300; the first conductive layer 401 forms a contact transition layer 405 with the semiconductor pillars 300.
Referring to fig. 8, a first conductive layer 401 may be formed on the top surface of the semiconductor pillar 300 by deposition. The first conductive layer 401 and the semiconductor pillars 300 can react to form contact transition layers 405. The material of the first conductive layer 401 may include cobalt (Co), which may react with silicon of the semiconductor pillars 300 to form a cobalt-silicon alloy layer (CoSi x ). The cobalt silicon alloy layer as the contact transition layer 405 can effectively reduce half-lifeContact resistance at the interface of the conductor pillar 300 and the first conductive layer 401.
The doped portion 301 formed in the semiconductor pillar 300 may react with oxygen by using germanium ions instead of silicon ions, so that the reserved silicon ions react with the subsequently formed first conductive layer 401 to form the contact transition layer 405, which not only reduces or avoids forming silicon oxide, but also further improves the electron conduction capability between the semiconductor pillar 300 and the first conductive layer 401 by using the subsequently formed contact transition layer 405.
Referring to fig. 5 to 8, after forming the first conductive layer 401, it further includes: forming a second conductive layer 402, the second conductive layer 402 being located on the first conductive layer 401; forming a third conductive layer 403, wherein the third conductive layer 403 is located on the second conductive layer 402 and is in contact conduction with the second conductive layer 402; the second conductive layer 402 is different from the third conductive layer 403 in material.
It should be noted that, the second conductive layer 402 and the third conductive layer 403 may be formed by deposition, the material of the second conductive layer 402 includes titanium nitride, and the material of the third conductive layer 403 includes tungsten. In this way, the first conductive layer 401, the second conductive layer 402 and the third conductive layer 403 may form an ohmic contact in the form of Co/TiN/W, which is helpful for reducing the impedance between the semiconductor pillar 300 and the three, and facilitating the transmission of electrons. Referring to fig. 8, electrons e may reach the first, second, and third conductive layers 401, 402, and 403 from the semiconductor pillars 300 through the contact transition layer 405. Alternatively, electrons may pass from the first conductive layer 401, the second conductive layer 402, and the third conductive layer 403, through the contact transition layer 405, and reach the semiconductor pillars 300 (this path is not shown in fig. 8).
Wherein the first conductive layer 401 and the second conductive layer 402 may be located on the top surface of the semiconductor pillar 300. The second conductive layer 402 may further cover the sidewall and the top surface of the isolation layer 200, and the second conductive layer 402 may enclose the groove 402a. The third conductive layer 403 may be formed in the groove 402a and in contact with the second conductive layer 402. The second conductive layer 402 may also cover the second conductive layer 402 on top of the isolation layer 200. Forming the third conductive layer 403 may further include etching the third conductive layer 403 to form a plurality of columnar third conductive layers 403, where the plurality of columnar third conductive layers 403 are arranged in an array at intervals. Along the thickness direction of the substrate 100, the single columnar third conductive layer 403 may extend in the same direction. Alternatively, along the thickness direction of the substrate 100, the single columnar third conductive layer 403 may also include multiple extension sections with parallel extension directions and different axes, so as to form a structure similar to a "Z" shape, which can facilitate the alignment connection between the semiconductor column 300 and the subsequently formed capacitor 500, effectively utilize the space on the substrate 100, and reduce the difficulty in manufacturing the semiconductor structure.
As one implementation, semiconductor pillars 300 are contact plugs and conductive structures 400 are capacitive contact pads. After forming the conductive structure 400, further comprises: a capacitor 500 is formed, the capacitor 500 is located on the conductive structure 400, and one of the electrodes of the capacitor 500 is in contact conduction with the conductive structure 400.
Referring to fig. 9, after forming the conductive structure 400, a first dielectric layer L2 may be deposited between adjacent columnar third conductive layers 403, with a top surface of the first dielectric layer L2 being flush with a top surface of the third conductive layers 403, which facilitates subsequent formation of the capacitor 500. Moreover, the first dielectric layer L2 may also avoid electrical contact or electrical interference between the adjacent third conductive layers 403. The capacitor 500 may include a first electrode layer 501, a capacitor dielectric layer 502, and a second electrode layer 503, which are sequentially stacked. In fig. 9, the first electrode layer 501 of the capacitor 500 is shown in contact conduction with the third conductive layer 403 of the conductive structure 400.
Forming the capacitor 500 may include: forming a second dielectric layer L3 on the third conductive layer 403 and the first dielectric layer L2; a trench (not shown) is formed in the second dielectric layer L3, and a first electrode layer 501, a capacitor dielectric layer 502, and a second electrode layer 503 are sequentially deposited in the trench, thereby forming a capacitor 500. The second dielectric layer L3 can avoid the problem of electrical contact or electrical interference between adjacent capacitors 500, and can form a protective effect on the capacitors 500. The materials of the first dielectric layer L2 and the second dielectric layer L3 may include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride.
As another implementation manner, before forming the second conductive layer 402, the method further includes: forming a fourth conductive layer 404, wherein the fourth conductive layer 404 is located on the first conductive layer 401 and is in contact conduction with the first conductive layer 401; forming the second conductive layer 402 includes: the second conductive layer 402 covers at least a top surface of the fourth conductive layer 404; the fourth conductive layer 404, the second conductive layer 402, and the third conductive layer 403 are formed of different materials, and the contact transition layer 405, the second conductive layer 402, the third conductive layer 403, and the fourth conductive layer 404 together form the conductive structure 400.
Referring to fig. 10 to 12, the material of the fourth conductive layer 404 may include titanium. The contact transition layer 405, the first conductive layer 401, the second conductive layer 402, the third conductive layer 403, and the fourth conductive layer 404 may collectively form CoSi x Ohmic resistance in the form of/Co/Ti/TiN/W to reduce contact resistance between the semiconductor pillars 300 and the conductive structure 400.
In the present disclosure, after forming the substrate 100, before forming the isolation layer 200, it may further include: word lines (not shown) are formed in the substrate 100 and correspond to trenches of the active region 100a. The word lines may extend in the first direction and be spaced apart in the second direction. Before forming the isolation layer 200, it may further include: bit lines 600 (see fig. 9) are formed, and the bit lines 600 extend in the first direction and are arranged at intervals in the second direction. The bit line 600 is connected to and conducts with the source region of the active region 100a. Wherein the first direction and the second direction are directions parallel to the substrate 100 and intersecting each other.
During operation of the semiconductor structure, the bit line 600 writes an electrical signal for reading (or an electrical signal for storing) into the source region of the substrate 100, and the word line controls the transmission of the electrical signal to the semiconductor pillar 300 through the control of the channel, passes through the conductive structure 400, reaches the capacitor 500, and finishes reading the stored signal in the capacitor 500 (or stores the electrical signal into the capacitor 500).
In a second aspect, referring to fig. 9, the present disclosure provides a semiconductor structure comprising: the semiconductor device comprises a substrate, wherein an isolation layer 200 and a plurality of semiconductor columns 300 arranged in an array are arranged in the substrate, and the isolation layer 200 at least covers the side walls of the semiconductor columns 300; the semiconductor pillar 300 has a doped portion 301 doped with metal ions therein; the conductive structure 400 is located on the semiconductor pillar 300, and is in contact conduction with the semiconductor pillar 300.
The substrate 100 comprises a plurality of active areas 100a arranged in an array, and isolation structures 100b are arranged between adjacent active areas 100 a; the isolation layer 200 and the semiconductor pillars 300 are both disposed on the substrate 100, the plurality of semiconductor pillars 300 are in contact conduction with the plurality of active regions 100a in a one-to-one correspondence manner, and the isolation layer 200 is located between adjacent semiconductor pillars 300 and is abutted against the sidewalls of the semiconductor pillars 300; wherein the top surface of the semiconductor pillar 300 is lower than the top surface of the isolation layer 200.
It should be noted that the active region 100a of the substrate 100 may be formed by doping, and the substrate 100 provides a structural basis for supporting the active region 100a, the semiconductor pillars 300, the conductive structures 400, and the capacitors 500 to be formed later. The isolation layer 200 can protect the semiconductor pillars 300 and isolate adjacent semiconductor pillars 300 from electrical interference. The top surface of the semiconductor pillar 300 is lower than the top surface of the isolation layer 200, so that at least part of the side wall of the conductive structure 400 formed later is covered by the isolation layer 200, and the isolation layer 200 can protect the contact interface between the conductive structure 400 and the semiconductor pillar 300, and improve the stability of the connection position of the conductive structure 400 and the semiconductor pillar 300. The isolation layer 200 may also protect the conductive structures 400 from interfering with adjacent conductive structures 400. The material of the semiconductor pillars 300 may be polysilicon.
It should be noted that, the semiconductor pillars 300 in the present disclosure may be contact plugs, and the conductive structures 400 may be capacitive contact pads. The semiconductor structure further includes a capacitor 500, where the capacitor 500 is disposed on the conductive structure 400, and one of electrodes of the capacitor 500 is in contact with the conductive structure 400. The capacitor contact pad can be in a columnar shape or a Z-shaped structure. By arranging the contact plug and the capacitor contact pad, the alignment connection difficulty of the active region 100a and the capacitor 500 can be effectively reduced, the resistance between the active region and the capacitor is reduced, the transmission of electric signals between the active region and the capacitor is facilitated, and the storage performance of the semiconductor structure serving as a memory is improved.
The semiconductor structure provided by the present disclosure further includes a word line, which may be provided in the form of the buried substrate 100, and a bit line 600, which corresponds to a channel in the active region 100a. The bit line 600 is disposed on the substrate 100 and covered by the isolation layer 200, and the bit line 600 is connected to and turned on with the source region of the active region 100a. The extending directions of the word lines and the bit lines 600 cross each other. The process of transmission between the bit line 600 and the capacitor 500 can refer to the above embodiment, and will not be described herein.
Optionally, the doped portion 301 is a location in the semiconductor structure near the top surface of the semiconductor pillar 300. The doped portion 301 is disposed at a position on the top surface of the semiconductor pillar 300, so that doped metal ions can replace silicon ions of the semiconductor pillar 300 to react with oxygen or water oxygen in the atmosphere, so that silicon ions are reduced or avoided being consumed to generate silicon oxide, and an oxide layer L1 is prevented from being formed at the interface between the semiconductor pillar 300 and the conductive structure 400, and electric signal transmission between the semiconductor pillar 300 and the conductive structure is affected.
Optionally, the conductive structure 400 includes a first conductive layer 401, and a contact transition layer 405 is disposed between the first conductive layer 401 and the semiconductor pillar 300, where the contact transition layer 405 is located on a top surface of the semiconductor pillar 300 and is in contact conduction with the semiconductor pillar 300. The material of the first conductive layer 401 may be cobalt, and the contact transition layer 405 formed between the first conductive layer 401 and the semiconductor pillars 300 may be a cobalt silicon alloy layer (CoSi x ) This can effectively reduce the contact resistance at the interface of the semiconductor pillar 300 and the first conductive layer 401.
The specific structure of the conductive structure 400 is described below.
As an implementation manner, the conductive structure 400 shown in fig. 8 and 9 further includes a second conductive layer 402 and a third conductive layer 403, where the second conductive layer 402 and the third conductive layer 403 are sequentially stacked on the contact transition layer 405, and the second conductive layer 402 is in contact conduction with the transition contact layer; the materials of the second conductive layer 402 and the third conductive layer 403 are different. The material of the second conductive layer 402 includes titanium nitride, and the material of the third conductive layer 403 includes tungsten. In this way, the first conductive layer 401, the second conductive layer 402 and the third conductive layer 403 may form an ohmic contact in the form of Co/TiN/W, which is helpful for reducing the impedance between the semiconductor pillar 300 and the three, and facilitating the transmission of electrons.
As another possible embodiment, referring to fig. 12, the conductive structure 400 further includes a fourth conductive layer 404, a second conductive layer 402, and a third conductive layer 403, where the fourth conductive layer 404, the second conductive layer 402, and the third conductive layer 403 are sequentially stacked on the contact transition layer 405, and materials of the fourth conductive layer 404, the second conductive layer 402, and the third conductive layer 403 are different from each other. The material of the fourth conductive layer 404 may include titanium. The contact transition layer 405, the first conductive layer 401, the second conductive layer 402, the third conductive layer 403, and the fourth conductive layer 404 may collectively form CoSi x Ohmic resistance in the form of/Co/Ti/TiN/W to reduce contact resistance between the semiconductor pillars 300 and the conductive structure 400.
In describing embodiments of the present disclosure, it should be understood that the terms "mounted," "connected," and "coupled" are to be construed broadly, unless otherwise indicated and defined, and may be connected in either a fixed manner, or indirectly, through intermediaries, or may be in communication with each other between two elements or an interaction relationship between the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship based on that shown in the drawings, merely to facilitate description of the disclosure and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the disclosure. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless specifically stated otherwise.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein an isolation layer and a plurality of semiconductor columns arranged in an array are arranged in the substrate, and the isolation layer at least covers the side walls of the semiconductor columns;
doping the semiconductor column by adopting metal ions, and forming a doped part in the semiconductor column;
and forming a conductive structure, wherein the conductive structure is positioned on the semiconductor column and is in contact conduction with the semiconductor column.
2. The method of fabricating a semiconductor structure of claim 1, wherein forming the doped portion comprises:
and doping the top surface of the semiconductor column, wherein the formed doped part is positioned in the semiconductor column and close to the top surface of the semiconductor column.
3. The method of claim 1, wherein the metal ions comprise at least one of germanium ions, tin ions, aluminum ions, titanium ions, and arsenic ions.
4. A method of fabricating a semiconductor structure according to any one of claims 1-3, wherein forming the conductive structure comprises:
forming a first conductive layer, wherein the first conductive layer is positioned on the semiconductor column and is in contact conduction with the top surface of the semiconductor column;
the first conductive layer forms a contact transition layer with the semiconductor pillars.
5. The method of fabricating a semiconductor structure of claim 4, wherein forming the conductive structure comprises:
forming a second conductive layer, wherein the second conductive layer is positioned on the first conductive layer;
forming a third conductive layer, wherein the third conductive layer is positioned on the second conductive layer and is in contact conduction with the second conductive layer;
the second conductive layer is of a different material than the third conductive layer.
6. The method of manufacturing a semiconductor structure according to claim 5, further comprising, before forming the second conductive layer:
forming a fourth conductive layer, wherein the fourth conductive layer is positioned on the first conductive layer and is in contact conduction with the first conductive layer;
forming the second conductive layer, comprising: the second conductive layer at least covers the top surface of the fourth conductive layer;
the materials of the fourth conductive layer, the second conductive layer and the third conductive layer are different, and the contact transition layer, the second conductive layer, the third conductive layer and the fourth conductive layer jointly form the conductive structure.
7. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, wherein an isolation layer and a plurality of semiconductor columns arranged in an array are arranged in the substrate, and the isolation layer at least covers the side walls of the semiconductor columns; the semiconductor column is provided with a doping part doped with metal ions;
and the conductive structure is positioned on the semiconductor column and is in contact conduction with the semiconductor column.
8. The semiconductor structure of claim 7, wherein the doped portion is a location in the semiconductor structure proximate to a top surface of the semiconductor pillar.
9. The semiconductor structure of claim 7, wherein the conductive structure comprises a first conductive layer having a contact transition layer between the first conductive layer and the semiconductor pillar, the contact transition layer being located on a top surface of the semiconductor pillar and in contact conduction with the semiconductor pillar.
10. The semiconductor structure of claim 9, further comprising a second conductive layer and a third conductive layer disposed on the first conductive layer in a stacked order, the second conductive layer in contact with the first conductive layer; the second conductive layer and the third conductive layer are different in material;
or, the conductive structure further comprises a fourth conductive layer, a second conductive layer and a third conductive layer, wherein the fourth conductive layer, the second conductive layer and the third conductive layer are sequentially stacked on the first conductive layer, and the materials of the fourth conductive layer, the second conductive layer and the third conductive layer are different from each other.
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