CN112652570A - Contact structure, semiconductor device structure and preparation method thereof - Google Patents
Contact structure, semiconductor device structure and preparation method thereof Download PDFInfo
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- CN112652570A CN112652570A CN201910963618.0A CN201910963618A CN112652570A CN 112652570 A CN112652570 A CN 112652570A CN 201910963618 A CN201910963618 A CN 201910963618A CN 112652570 A CN112652570 A CN 112652570A
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
The invention relates to a contact structure, a semiconductor device structure and a preparation method thereof, wherein the contact structure comprises: a conductive plug; and the passivation protective layer covers the side wall of the conductive plug. In the contact structure, the passivation protective layer is formed on the side wall of the conductive plug, so that the conductive plug is prevented from being exposed in the air, the surface of the conductive plug is prevented from being oxidized, the passivation protective layer can protect the conductive plug from being removed in an acid washing process, the complete appearance of the conductive plug is ensured, and the conductive performance of a device is ensured.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and more particularly, to a contact structure, a semiconductor device structure and a method for manufacturing the same.
Background
Contact structures (e.g., bit line contact structures) in a DRAM (Dynamic Random Access Memory) process are generally formed by dry etching after filling doped polysilicon, however, in the prior art, polysilicon sidewalls forming a bit line structure are easily oxidized to form silicon oxide after contacting air, and are laterally etched in an acid cleaning process after subsequent dry etching, so that the sidewall profile of the bit line contact structure is damaged, the width of a bit line in a Memory device is reduced, the reduced width causes an increase in resistance, a current of a Memory cell is reduced to cause an excessively high bit line load, and a conduction rate of the bit line is reduced.
Meanwhile, with the continuous development of semiconductor technology, the feature size of a semiconductor integrated circuit device is continuously reduced, and as one kind of semiconductor integrated circuit device, the feature size of a DRAM is also gradually reduced, and in order to pursue a smaller feature size, it is a problem that the performance of the DRAM needs to be continuously sought. The performance of DRAM is determined by various factors, wherein the source of the transistor in the memory is electrically connected to the bit line (bit line) to form a current transmission path, and the bit line contact hole and the bit line contact structure with a high aspect ratio have non-uniform profiles due to a loading effect during the etching process, thereby affecting the conductivity of the bit line contact structure.
Disclosure of Invention
Based on the situation, the contact structure, the semiconductor device structure and the preparation method thereof are provided for solving the problems that the bit line contact structure of the traditional memory has uneven profile and influences the conductivity of the bit line contact.
In order to achieve the above object, the present invention provides a contact structure comprising:
a conductive plug;
and the passivation protective layer covers the side wall of the conductive plug.
According to the contact structure, the passivation protective layer is formed on the side wall of the conductive plug, so that the conductive plug is prevented from being exposed in the air, the surface of the plug is prevented from being oxidized, the conductive plug can be protected from being etched by the passivation protective layer in an acid washing process, the complete appearance of the conductive plug is ensured, and the conductive performance of a device is ensured.
In one embodiment, the conductive plug includes: a first conductive layer and a second conductive layer on the upper surface of the first conductive layer; the first conducting layer and the second conducting layer are doped, and the doping concentration of the first conducting layer is greater than that of the second conducting layer; the passivation protection layer includes a nitride protection layer.
In the contact structure, the conductive plug is set to be a structure comprising the first conductive layer and the second conductive layer, the first conductive layer is formed to cover the side wall of the contact hole, the second conductive layer is formed on the first conductive layer, the side wall of the second conductive layer in the contact hole is provided with the first conductive layer, and the concentration of the doping ions of the second conductive layer is smaller than that of the doping ions of the first conductive layer. When etching, due to the selection ratio, the first conducting layer on the side wall of the second conducting layer is preferentially etched, and the side wall of the second conducting layer can not be etched, so that the profile of the side wall of the second conducting layer is ensured. And the bottom of the first conductive layer is left to form a conductive plug together with the second conductive layer, and the first conductive layer doped with high concentration can improve the conduction rate of the bit line.
A method of making a contact structure comprising the steps of:
providing a substrate;
forming a conductive plug on a substrate;
and forming a passivation protection layer on the sidewall of the conductive plug.
According to the preparation method of the contact structure, the passivation protective layer is formed on the side wall of the conductive plug, so that the conductive plug is prevented from being exposed in the air, the surface of the plug is prevented from being oxidized, the passivation protective layer can protect the conductive plug from being etched in an acid washing process, the complete appearance of the conductive plug is ensured, and the conductivity of a device is ensured.
In one embodiment, the method further comprises the following steps before forming the conductive plug on the substrate: forming a contact hole in the substrate; the conductive plug is composed of a first conductive layer and a second conductive layer, and the forming of the conductive plug comprises the following steps:
forming a first conductive layer on the side wall and the bottom of the contact hole;
forming a second conductive layer on the surface of the first conductive layer; the second conducting layer and the first conducting layer are doped, and the doping concentration of the second conducting layer is smaller than that of the first conducting layer;
removing the first conductive layer on the side wall of the second conductive layer to obtain a conductive plug;
the method for forming a passivation layer on the sidewall of the conductive plug comprises the following steps:
and performing nitridation treatment on the conductive plug to form a passivation protection layer on the side wall of the conductive plug.
In the preparation method of the contact structure, the conductive plug is formed by preparing the first conductive layer and the second conductive layer: first, a first conductive layer is formed to cover the side wall of the contact hole, a second conductive layer is formed on the first conductive layer, the side wall of the second conductive layer in the contact hole is provided with the first conductive layer, and the doping concentration of the second conductive layer is smaller than that of the first conductive layer. When etching, due to the selection ratio, the first conducting layer on the side wall of the second conducting layer is preferentially etched, and the side wall of the second conducting layer can not be etched, so that the profile of the side wall of the second conducting layer is ensured. And the bottom of the first conductive layer is left to form a conductive plug together with the second conductive layer, and the first conductive layer doped with high concentration can improve the conduction rate of the bit line.
The present invention also provides a semiconductor device structure comprising:
a substrate, wherein a bit line contact hole is formed in the substrate;
the bit line contact structure comprises a bit line contact plug and a passivation protective layer; the bit line contact plug is positioned in the bit line contact hole, and the bottom of the bit line contact plug is contacted with the bottom of the bit line contact hole; the passivation protection layer is positioned on the side wall of the bit line contact plug;
and the bit line is positioned on the upper surface of the bit line contact structure.
In the semiconductor device structure, the passivation protective layer is formed on the side wall of the bit line contact plug to prevent the bit line contact plug from being exposed in the air, so that the surface of the bit line contact plug is prevented from being oxidized, the bit line contact plug can be protected from being etched by the passivation protective layer in the acid washing process, the complete appearance of the bit line contact plug is ensured, and the conductive performance of the device is ensured.
In one embodiment, the device further comprises a shallow trench isolation structure which is positioned in the substrate and isolates a plurality of active regions which are arranged at intervals in the substrate;
the word lines are arranged in the substrate at intervals in parallel, and the extending direction of the word lines intersects with the extending direction of the active region at an angle smaller than 90 degrees;
the filling insulating layer is positioned on the upper surfaces of the word lines and the substrate;
the bit line contact hole is positioned between adjacent word lines in the same active region, penetrates through the filling insulating layer positioned on the upper surface of the substrate along the thickness direction and extends into the substrate; the bit line is electrically connected to the active region via the bit line contact structure.
In one embodiment, the bit line contact plug includes: a first conductive layer and a second conductive layer on the first conductive layer; the first conducting layer and the second conducting layer are doped, and the doping concentration of the first conducting layer is greater than that of the second conducting layer; the passivation protection layer includes a nitride protection layer.
In the semiconductor device structure, the conductive plug is formed by the first conductive layer and the second conductive layer: a first conductive layer is formed to cover the side wall of the bit line contact hole, a second conductive layer is formed on the first conductive layer, the side wall of the second conductive layer in the bit line contact hole is provided with the first conductive layer, and the concentration of the doped ions of the second conductive layer is smaller than that of the doped ions of the first conductive layer. When etching, due to the selection ratio, the first conducting layer on the side wall of the second conducting layer is preferentially etched, and the side wall of the second conducting layer can not be etched, so that the profile of the side wall of the second conducting layer is ensured. And the bottom of the first conductive layer is left to form a conductive plug together with the second conductive layer, and the first conductive layer doped with high concentration can improve the conduction rate of the bit line.
The invention also provides a preparation method of the semiconductor device structure, which comprises the following steps:
providing a substrate, wherein a bit line contact hole is formed in the substrate;
forming a bit line contact structure in the bit line contact hole, and forming a bit line on the upper surface of the bit line contact structure; the bit line contact structure comprises a bit line contact plug and a passivation protective layer, wherein the bit line contact plug is positioned in the bit line contact hole, the bottom of the bit line contact plug is contacted with the bottom of the bit line contact hole, and the passivation protective layer is positioned on the side wall of the bit line contact plug.
According to the manufacturing method of the semiconductor device structure, the passivation protective layer is formed on the side wall of the bit line contact plug, the bit line contact plug is prevented from being exposed in the air, the surface of the bit line contact plug is prevented from being oxidized, the bit line contact plug can be protected from being etched by the passivation protective layer in the acid washing process, the appearance integrity of the bit line contact plug is ensured, and therefore the conductivity of the device is ensured.
In one embodiment, the method further comprises the following steps before forming the bit line contact hole in the substrate:
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions distributed at intervals in the substrate;
forming a plurality of word lines arranged at intervals in the substrate, wherein the extending direction of the word lines intersects with the extending direction of the active region at an angle smaller than 90 degrees;
forming a filling insulating layer on the upper surfaces of the word lines and the substrate; the bit line contact hole is positioned between adjacent word lines in the same active region, penetrates through the filling insulating layer positioned on the upper surface of the substrate along the thickness direction and extends into the substrate; the bit line is electrically connected to the active region via the bit line contact structure.
In one embodiment, forming a bit line contact structure in the bit line contact hole and forming a bit line on an upper surface of the bit line contact structure includes:
forming a first conductive layer on the side wall and the bottom of the bit line contact hole, and forming a second conductive layer on the surface of the first conductive layer; the second conducting layer and the first conducting layer are doped, and the doping concentration of the second conducting layer is smaller than that of the first conducting layer;
forming a bit line on the upper surface of the second conductive layer;
removing the first conductive layer on the side wall of the second conductive layer, and reserving the bottom of the first conductive layer to form a conductive plug;
and performing nitridation treatment on the bit line contact plug to form a passivation protective layer on the side wall of the bit line contact plug.
In the preparation method of the contact structure, the conductive plug is formed by preparing the first conductive layer and the second conductive layer: a first conductive layer is formed to cover the side wall of the bit line contact hole, a second conductive layer is formed on the first conductive layer, the side wall of the second conductive layer in the bit line contact hole is provided with the first conductive layer, and the concentration of the doped ions of the second conductive layer is smaller than that of the doped ions of the first conductive layer. When etching, due to the selection ratio, the first conducting layer on the side wall of the second conducting layer is preferentially etched, and the side wall of the second conducting layer can not be etched, so that the profile of the side wall of the second conducting layer is ensured. And the bottom of the first conductive layer is left to form a conductive plug together with the second conductive layer, and the first conductive layer doped with high concentration can improve the conduction rate of the bit line.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating a contact structure according to an embodiment of the present invention;
FIGS. 2 to 7 are schematic cross-sectional views of structures obtained at respective steps in a method for manufacturing a contact structure according to an embodiment of the present invention;
FIG. 8 is a flow chart of a method of fabricating a semiconductor device structure in one embodiment;
FIG. 9 is a schematic diagram illustrating a top view of a resulting structure after forming a shallow trench isolation structure in a substrate in accordance with one embodiment;
FIG. 10 is a schematic cross-sectional view along AA in FIG. 9;
FIG. 11 is a schematic diagram illustrating a top view of a structure resulting from forming a trench in a substrate, in accordance with one embodiment;
FIG. 12 is a schematic cross-sectional view along AA in FIG. 11;
FIG. 13 is a cross-sectional view of the resulting structure after forming an intergate dielectric layer within the trench, in accordance with one embodiment;
FIG. 14 is a schematic diagram illustrating a top view of a structure resulting from the formation of word lines in one embodiment;
FIG. 15 is a cross-sectional view of the resulting structure after forming a first word line conductive layer and a second word line conductive layer within the trench, in accordance with one embodiment;
FIG. 16 is a cross-sectional view of the structure resulting from the formation of a fill insulating layer in one embodiment;
FIG. 17 is a schematic diagram illustrating a top view of the structure resulting from the formation of bit line contact holes in one embodiment;
FIG. 18 is a schematic cross-sectional view taken along the direction AA in FIG. 17;
FIG. 19 is a cross-sectional structure of the resulting structure after forming a first layer of conductive material, in one embodiment;
FIG. 20 is a cross-sectional view of the resulting structure after forming a second layer of conductive material, in one embodiment;
FIG. 21 is a cross-sectional view of the structure resulting from the removal of the first and second layers of conductive material overlying the top surface of the dielectric layer, in accordance with one embodiment;
FIG. 22 is a cross-sectional structure of the resulting structure after forming a conductive body material layer, a dielectric material layer, and a patterned masking layer, in accordance with an embodiment;
FIG. 23 is a schematic cross-sectional view of the resulting structure after formation of bit lines in one embodiment;
FIG. 24 is a schematic diagram illustrating a top view of the structure resulting from the removal of the second conductive layer around the first conductive layer in one embodiment;
FIG. 25 is a schematic cross-sectional view taken along the direction AA in FIG. 24;
fig. 26 is a cross-sectional view of the structure after forming a passivation layer on the sidewalls of the bit line contact plugs according to an embodiment.
The reference numbers illustrate:
10 contact structure
11 conductive plug
111. 262 first conductive layer
112. 263 second conductive layer
113. 264 first layer of conductive material
114. 265 second conductive material layer
12. 266 passivation protective layer
13. 20 substrate
1425 contact hole
15 cover insulating layer
21 shallow trench isolation structure
22 active region
23 word line
231 grooves
232 intergate dielectric layer
233 first word line conductive layer
234 second word line conductive layer
24 filling the insulating layer
25 bit line contact hole
26 bit line contact structure
261 bit line contact plug
27 bit line
271 conductive body material layer
272 conductive body layer
273 layer of dielectric material
274 top dielectric layer
28 patterned mask layer
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In one embodiment, as shown in fig. 1, the present invention provides a method for preparing a contact structure, comprising the steps of:
s11: providing a substrate;
s12: forming a conductive plug on the substrate;
s13: and forming a passivation protection layer on the side wall of the conductive plug.
According to the preparation method of the contact structure, the passivation protective layer is formed on the side wall of the conductive plug, so that the conductive plug is prevented from being exposed in the air, the surface of the conductive plug is prevented from being oxidized, the conductive plug can be protected from being etched by the passivation protective layer in the acid washing process, the complete appearance of the conductive plug is ensured, and the conductive performance of a device is ensured.
In one example, as shown in fig. 2, the substrate 13 may include a semiconductor substrate, and device structures (such as transistors, etc.) requiring electrical extraction may be formed in the substrate 13; an active region (not shown) is formed within the substrate 13.
In an example, the upper surface of the substrate 13 may be formed with a cover insulating layer 15, and the material of the cover insulating layer 15 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.
In one example, as shown in fig. 2, after providing the substrate 13, a step of forming a contact hole 14 in the substrate 13 is further included, and when the cover insulating layer 15 is formed on the upper surface of the substrate 13, the contact hole 14 penetrates the cover insulating layer 15 in the thickness direction and extends into the substrate 13, and contacts an active region in the substrate 13. Specifically, the cover insulating layer 15 and the substrate 13 may be etched using an etching process to form the contact hole 14. Of course, in other examples, the contact hole 14 may not be formed in the substrate 13, i.e., the conductive plug 11 formed later may be directly formed on the upper surface of the substrate 13.
In one example, the bit line contact hole 14 may include a circular hole, a rectangular hole, an elliptical hole, or the like, and the longitudinal sectional shape of the bit line contact hole 14 may include, but is not limited to, a rectangle.
In one example, as shown in fig. 3 to 6, the step S12 of forming the conductive plug 11 on the substrate 13 may include the following steps:
s121: forming a first conductive material layer 113 on the sidewalls and bottom of the bit line contact hole 14 and the upper surface of the capping dielectric layer 15, as shown in fig. 3; the first conductive material layer 113 has a dopant therein;
s122: forming a second conductive material layer 114 on the surface of the first conductive material layer 113, wherein the bit line contact hole 14 is filled with the second conductive material layer 114, as shown in fig. 4; the second conductive material layer 114 has a dopant therein, and the dopant concentration of the second conductive material layer 114 is less than the dopant concentration of the first conductive material layer;
s123: etching to remove the first conductive material layer 113 and the second conductive material layer 114 on the upper surface of the insulating cover layer 15, as shown in fig. 5;
s124: the first conductive layer 111 located at the periphery of the second conductive layer 112 is removed to obtain the conductive plug 11, as shown in fig. 6.
In the method for manufacturing the contact structure, the conductive plug 11 is formed by manufacturing the first conductive layer 111 and the second conductive layer 112, the first conductive layer 111 is formed to cover the sidewall of the contact hole 14, the second conductive layer 112 is formed on the first conductive layer 111, the sidewall of the second conductive layer 112 in the contact hole 14 has the first conductive layer 111, and the doping concentration of the second conductive layer 112 is less than that of the first conductive layer 111. When etching, the first conductive layer 111 on the sidewall of the first conductive layer 112 is preferentially etched due to the selectivity, and the sidewall of the second conductive layer 112 may not be etched, thereby ensuring the profile of the sidewall of the second conductive layer 112. And the bottom of the first conductive layer 111 is left to form the conductive plug 11 together with the second conductive layer 112, the high concentration of the first conductive layer 111 can increase the conduction rate of the bit line.
In one example, in step S121, the first conductive material layer 113 may be formed by, but not limited to, an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDP-CVD) process, a radical-enhanced CVD (RECVD) process, or an Atomic Layer Deposition (ALD) process; the first conductive material layer 113 may include doped polysilicon, metal titanium, metal tungsten, metal copper, or the like, and preferably, in the present embodiment, the first conductive material layer 113 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer.
In one example, in step S121, the intrinsic material layer may be formed by first forming the intrinsic material layer on the sidewalls and the bottom of the bit line contact hole 14 and the upper surface of the capping dielectric layer 15, and then doping the intrinsic material layer by using an ion implantation process or a diffusion process to form the first conductive material layer 113. Of course, in other examples, the first conductive material layer 113 may be directly formed by directly performing ion doping in a deposition process.
In an example, in step S122, the second conductive material layer 114 may be formed by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the second conductive material layer 114 may include doped polysilicon, metal titanium, metal tungsten, metal copper, or the like, and preferably, in the present embodiment, the second conductive material layer 114 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer. The doping type of the second conductive material layer 114 may be the same as that of the first conductive material layer 113.
In one example, in step S122, an intrinsic material layer may be formed on the upper surface of the first conductive material layer 113, and then the intrinsic material layer may be doped by an ion implantation process or a diffusion process to form the second conductive material layer 114. Of course, in other examples, the second conductive material layer 114 may be directly formed by directly performing ion doping in the deposition process.
In one example, the doping concentration of the first conductive layer 111 may be 1 × 1018atom/cm-3(atomic number per cubic centimeter) to 1X 1022atom/cm-3The doping concentration of the second conductive layer 112 may be 1 × 1015atom/cm-3～1×1017atom/cm-3。
In an example, in step S123, the first conductive material layer 113 and the second conductive material layer 114 may be etched by using a dry etching process, since the doping concentrations of the first conductive material layer 113 and the second conductive material layer 114 are different, the higher the doping concentration is, the faster the dry etching removal is, after removing the first conductive material layer 113 and the second conductive material layer 114 on the upper surface of the insulating cover layer 15, the more the first conductive material layer 113 located at the periphery of the second conductive material layer 114 may be removed, so as to form a sidewall pre-etching, which may overcome a micro-loading effect, so that the remaining upper surface of the first conductive layer 111 is lower than the upper surface of the second conductive layer 112, as shown in fig. 5.
In one example, in step S124, a mask layer (not shown) may be formed on the upper surface of the second conductive layer 112 before the mask layer completely covers the second conductive layer 112, and then the mask layer is removed after the first conductive layers 111 on both sides of the second conductive layer 112 are removed by etching based on the mask layer until the substrate 13 on the periphery of the first conductive layer 112 is exposed.
In an example, the conductive plug 11 may be nitrided by a doping process, a chemical vapor deposition process, a glow discharge process, or a reactive sputtering process, and the passivation protection layer 12 may include, but is not limited to, a nitride protection layer.
In one example, in step S13, a passivation layer 12 is formed on the sidewall of the conductive plug 11 by performing a nitridation process on the conductive plug 11; specifically, the process conditions for performing the nitridation treatment on the conductive plug 11 include: the temperature of the nitriding treatment can be 20 ℃ to 40 ℃, the concentration of nitrogen in the nitriding treatment can be 100ppm (parts per million) to 200ppm, the pressure of the nitriding treatment can be 10 to 20 standard atmospheres, and the time of the nitriding treatment can be 10s to 30 s.
In an example, the thickness of the passivation protection layer 12 may be set according to actual needs, and preferably, in this embodiment, the bottom thickness of the passivation protection layer 12 may be 2nm (nanometers) to 3 nm.
In an example, the contact structure 10 in the present embodiment may be any contact structure for electrical contact and electrical lead-out, and may include, but is not limited to, a bit line contact structure, and the like.
In another embodiment, with continuing reference to fig. 7, the present invention further provides a contact structure 10, the contact structure 10 comprising:
a conductive plug 11;
and a passivation protection layer 12, wherein the passivation protection layer 12 covers the sidewall of the conductive plug 11.
In the contact structure 10, the passivation protection layer 12 is formed on the side wall of the conductive plug 11, so that the conductive plug 11 is prevented from being exposed in the air, the surface of the conductive plug 11 is prevented from being oxidized, the passivation protection layer 12 can protect the conductive plug 11 from being removed in an acid washing process, the conductive plug 11 is ensured to be complete in shape, and the conductive performance of a device is ensured.
In one example, the conductive plug 11 includes: a first conductive layer 111 and a second conductive layer 112 on the upper surface of the first conductive layer 111; the first conductive layer 111 and the second conductive layer 112 are doped with dopant ions, and the dopant concentration of the dopant ions in the first conductive layer 111 is greater than the dopant concentration of the dopant ions in the second conductive layer 112.
In the method for manufacturing the contact structure, the conductive plug 11 is formed by manufacturing the first conductive layer 111 and the second conductive layer 112, the first conductive layer 111 is formed to cover the sidewall of the contact hole 14, the second conductive layer 112 is formed on the first conductive layer 111, the sidewall of the second conductive layer 112 in the contact hole 14 has the first conductive layer 111, and the doping concentration of the second conductive layer 112 is less than that of the first conductive layer 111. When etching, the first conductive layer 111 on the sidewall of the first conductive layer 112 is preferentially etched due to the selectivity, and the sidewall of the second conductive layer 112 may not be etched, thereby ensuring the profile of the sidewall of the second conductive layer 112. And the bottom of the first conductive layer 111 is left to form the conductive plug 11 together with the second conductive layer 112, the high concentration of the first conductive layer 111 can increase the conduction rate of the bit line.
In one example, the first conductive layer 111 may include doped polysilicon, metallic titanium, metallic tungsten, or metallic copper, etc., and preferably, in the present embodiment, the first conductive layer 111 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer; the second conductive layer 112 may include doped polysilicon, metal titanium, metal tungsten, metal copper, or the like, and preferably, in this embodiment, the second conductive layer 112 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer; the doping type of the second conductive layer 112 may be the same as that of the first conductive layer 111.
In one example, the passivation protection layer 12 may include, but is not limited to, a nitride protection layer.
In an example, the thickness of the passivation protection layer 12 may be set according to actual needs, and preferably, in this embodiment, the bottom thickness of the passivation protection layer 12 may be 2nm (nanometers) to 3 nm.
In an example, the contact structure 10 in the present embodiment may be any contact structure for electrical contact and electrical lead-out, and may include, but is not limited to, a bit line contact structure, and the like.
In another embodiment, referring to fig. 8, the present invention further provides a method for manufacturing a semiconductor device structure, including the following steps:
s21: providing a substrate, wherein a bit line contact hole is formed in the substrate;
s22: forming a bit line contact structure in the bit line contact hole, and forming a bit line on the upper surface of the bit line contact structure; the bit line contact structure comprises a bit line contact plug and a passivation protective layer, the bit line contact plug is located in the bit line contact hole, the bottom of the bit line contact plug is in contact with the bottom of the bit line contact hole, and the passivation protective layer is located on the side wall of the bit line contact plug.
In the preparation method of the semiconductor device structure, the passivation protection layer 266 is formed on the side wall of the bit line contact plug 261 to prevent the bit line contact plug 261 from being exposed in the air, so that the surface of the bit line contact plug 261 is prevented from being oxidized, the passivation protection layer 266 can protect the bit line contact plug 261 from being removed in an acid washing process, the shape integrity of the bit line contact plug 261 is ensured, and the conductivity of the device is ensured.
In one example, the substrate 20 provided in step S21 may include, but is not limited to, a silicon substrate. Specifically, the substrate 20 may include a base (not shown) and an epitaxial layer (not shown) on the upper surface of the base, and the epitaxial layer may include an N-type epitaxial layer or a P-type epitaxial layer.
In one example, before forming the bit line contact hole in the substrate 20 in step S21, the method further includes the following steps:
forming a shallow trench isolation structure 21 in the substrate 20, wherein the shallow trench isolation structure 21 isolates a plurality of active regions 22 distributed at intervals in the substrate 20, as shown in fig. 9 and 10;
forming a plurality of word lines 23 arranged at intervals in the substrate 20, wherein the extending direction of the word lines 23 intersects the extending direction of the active region 22 at an angle smaller than 90 degrees, as shown in fig. 11 to 15;
a fill insulating layer 25 is formed on the upper surfaces of the word lines 23 and the substrate 20, as shown in fig. 16.
In one example, the shallow trench isolation structure 21 may be formed by forming a shallow trench (not shown) in the substrate 20 and then filling the shallow trench with an isolation material. The material of the shallow trench isolation structure 21 may include, but is not limited to, silicon oxide or silicon nitride, etc. The longitudinal cross-sectional shape of the shallow trench isolation structure 21 may be set according to actual needs, and the longitudinal cross-sectional shape of the shallow trench isolation structure 21 may include a rectangle, an inverted trapezoid, or a U-shape, where the longitudinal cross-sectional shape of the shallow trench isolation structure 10 is taken as an example in fig. 10 as the U-shape.
In an example, the number of active regions 22 that the shallow trench isolation structures 21 can isolate in the substrate 20 may be, but is not limited to, an array as shown in fig. 9. In one example, forming the word line 23 in the substrate 20 may include the steps of:
forming a trench 231 in the substrate 20, the trench 231 defining the position and shape of the word line 23, as shown in fig. 11 and 12;
forming an inter-gate dielectric layer 232 in the trench 231, wherein the inter-gate dielectric layer 232 covers the bottom and the sidewall of the trench 231 and the upper surface of the substrate 20, as shown in fig. 13;
a first word line conductive layer 233 and a second word line conductive layer 234 are formed in the trench 231, the first word line conductive layer 233 covers the lower sidewall and the bottom of the inter-gate dielectric layer 232, the second word line conductive layer 234 takes the space inside the first word line conductive layer 233, and the upper surface of the first word line conductive layer 233 and the upper surface of the second word line conductive layer 234 are both lower than the upper surface of the substrate 20, as shown in fig. 15.
In one example, a photolithographic etching process may be employed to form trenches 231 within substrate 20; the extending direction of the trench 231 has an angle smaller than 90 ° (degrees) with the extending direction of the active region 22.
In one example, the material of the intergate dielectric layer 232 may include, but is not limited to, silicon oxide or silicon nitride; the inter-gate dielectric layer 232 is formed using an atomic layer Deposition process, a plasma Vapor Deposition process (Chemical Vapor Deposition), or a Rapid Thermal Oxidation process (Rapid Thermal Oxidation).
In an example, the material of the first word line conductive layer 233 may include silicon doped with As (arsenic) or B (boron), germanium doped with P (phosphorus) or As, W (tungsten), Ti (titanium), TiN (titanium nitride), or Au (gold), the material of the second word line conductive layer 234 may include W, Ti, Al (aluminum), or Pt (platinum), and the material of the first word line conductive layer 233 is different from the material of the second word line conductive layer 234; the first word line conductive layer 233 and the second word line conductive layer 234 may be formed by, but not limited to, an atomic layer deposition process combined with an etch-back process.
In an example, the filling insulating layer 24 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, and the material of the filling insulating layer 24 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.
In one example, an etching process may be used to etch active region 22 to form bit line contact hole 25, as shown in fig. 17 and 18; of course, the bit line contact hole 25 may be formed by removing the filling insulating layer 24 in a portion of the word line 23 at the same time as the active region 22 is removed to enlarge the size of the bit line contact hole 25. The bit line contact hole 25 exposes a drain electrode (not shown) in the active region 22, and the drain electrode and the source electrode may be formed by, but not limited to, ion implantation after the word line 23 is formed.
In one example, in step S22, forming the bit line contact structure 26 in the bit line contact hole 25 and forming the bit line 27 on the upper surface of the bit line contact structure 26 may include the following steps:
s221: as shown in fig. 19 to 21, a first conductive layer 262 is formed on the sidewall and the bottom of the bit line contact hole 25, and a second conductive layer 263 is formed on the surface of the first conductive layer 262; the second conductive layer 263 and the first conductive layer 262 are doped, and the doping concentration of the second conductive layer 262 is less than that of the first conductive layer 261;
s222: forming a bit line 27 on the upper surface of the second conductive layer 263, as shown in fig. 22 and 23;
s223: removing the first conductive layer 262 on the sidewall of the second conductive layer 263 to form a bit line contact plug 261, as shown in fig. 24 and 25; specifically, an etching process may be used to remove the first conductive layer 262 on both sides of the second conductive layer 262 until the substrate 20 at the periphery of the first conductive layer 262 is exposed;
s224: the bit line contact plugs 261 are nitrided to form passivation protection layers 266 on sidewalls of the bit line contact plugs 261, as shown in fig. 26.
In the above method for manufacturing the contact structure, the conductive plug 261 is formed by preparing the first conductive layer 262 and the second conductive layer 263: first, a first conductive layer 262 is formed to cover the sidewall of the bit line contact hole 25, a second conductive layer 263 is formed on the first conductive layer 262, the sidewall of the second conductive layer 263 in the bit line contact hole 261 has the first conductive layer 262, and the concentration of the doping ions of the second conductive layer 263 is less than that of the doping ions of the first conductive layer 262. When etching, due to the selectivity, the first conductive layer 262 on the sidewall of the second conductive layer 263 is preferentially etched, and the sidewall of the second conductive layer 263 may not be etched, thereby ensuring the profile of the sidewall of the second conductive layer 263. And leaving the bottom of the first conductive layer 262 to constitute a conductive plug together with the second conductive layer 263, the highly doped first conductive layer 262 can increase the conduction rate of the bit line.
In one example, step S221 may include the steps of: first, a first conductive material layer 264 may be formed on the sidewall and bottom of the bit line contact hole 25 and the upper surface of the filling insulation layer 24 by using, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process or an atomic layer deposition process, as shown in fig. 19, the material of the first conductive material layer 264 may include doped polysilicon, metal titanium, metal tungsten or metal copper, etc., preferably, in this embodiment, the first conductive material layer 264 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer; next, a second conductive material layer 265 may be formed on the surface of the first conductive material layer 264 by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process, and the second conductive material layer 265 fills the bit line contact hole 25, as shown in fig. 20, the material of the second conductive material layer 265 may include doped polysilicon, titanium metal, tungsten metal, copper metal, or the like, and preferably, in this embodiment, the second conductive material layer 265 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer; finally, the first conductive material layer 264 and the second conductive material layer 265 may be etched and removed by using a dry etching process to remove the first conductive material layer 264 and the second conductive material layer 265 on the upper surface of the filling insulation layer 24, because the doping concentrations of the first conductive material layer 264 and the second conductive material layer 265 are different, and the dry etching process is faster when the doping concentration is higher, after the first conductive material layer 264 and the second conductive material layer 265 on the upper surface of the filling insulation layer 24 are removed, the first conductive material layer 264 at the periphery of the second conductive material layer 265 may be removed more, so as to form a sidewall pre-etching, which may overcome a micro-loading effect, so that the upper surface of the remaining first conductive layer 262 is lower than the upper surface of the second conductive layer 263, and the first conductive layer 262 and the second conductive layer 263 together form a bit line contact plug 261, as shown in fig. 21.
In one example, in step S221, the doping concentration of the first conductive material layer 264 may be 1 × 1018atom/cm-3～1×1022atom/cm-3The doping concentration of the second conductive material layer 265 may be 1 × 1015atom/cm-3～1×1017atom/cm-3。
In an example, step S222 may include the steps of: first, a conductive body material layer 271, a dielectric material layer 273 and a patterned masking layer 28 are formed on the upper surface of the structure obtained in step S21, as shown in fig. 22, the material of the conductive body material layer 271 may include but is not limited to tungsten, the material of the dielectric material layer 273 may include but is not limited to silicon nitride, and the patterned masking layer 28 may include but is not limited to patterned photoresist; dielectric material layer 273 and conductive body material layer 271 may then be formed on the basis of patterned masking layer 28 to form bit line 27 comprising conductive body layer 272 and top dielectric layer 274, as shown in fig. 23.
It should be noted that in step S223, in the process of removing the first conductive layer 262 on the periphery of the second conductive layer 263 to obtain the conductive plug 261, the bit line contact hole 25 is continuously etched, the profile of the bit line contact hole 25 is changed to form the bit line contact hole 25, as shown in fig. 25, the longitudinal sectional shape of the bit line contact hole 25 may include an inverted trapezoid.
In one example, as shown in fig. 24, the bit lines 27 may be straight lines, and the bit lines 27 may extend in the direction in which the word lines 23 are arranged. A bit line contact structure 26 is located between adjacent word lines 21 in the same active region 22 for electrically connecting a bit line 27 to the drain in each active region.
In one example, in step S224, the bit line contact plug 261 may be nitrided using a doping process, a chemical vapor deposition process, a glow discharge process, or a reactive sputtering process, and the passivation protection layer 266 may include, but is not limited to, a nitride protection layer.
In one example, in step S224, a passivation layer 266 is formed on sidewalls of the bit line contact plugs 261 by performing a nitridation process on the bit line contact plugs 261; specifically, the process conditions for performing the nitridation treatment on the conductive plug 11 include: the temperature of the nitriding treatment can be 20-40 ℃, the concentration of nitrogen in the nitriding treatment process can be 100-200 ppm, the pressure of the nitriding treatment can be 10-20 standard atmospheres, and the time of the nitriding treatment can be 10-30 s.
In an example, the thickness of the passivation protection layer 266 may be set according to actual needs, and preferably, in this embodiment, the bottom of the passivation protection layer 266 may be 2nm to 3 nm.
In another embodiment, with continuing reference to fig. 24 and 26, the present invention further provides a semiconductor device structure, including:
a substrate 20, a bit line contact hole 25 is formed in the substrate 20;
a bit line contact structure 26, the bit line contact structure 26 including a bit line contact plug 261 and a passivation protection layer 262; bit line contact plug 261 is located within bit line contact hole 25, and the bottom of bit line contact plug 261 contacts the bottom of bit line contact hole 25; a passivation protection layer 266 is positioned on sidewalls of the bit line contact plugs 261;
and bit lines 27 located on the upper surfaces of the bit line contact structures 26.
In the semiconductor device structure, the passivation protection layer 266 is formed on the side wall of the bit line contact plug 261 to prevent the bit line contact plug 261 from being exposed in the air, so that the surface of the bit line contact plug 261 is prevented from being oxidized, the passivation protection layer 266 can protect the bit line contact plug 261 from being removed in an acid washing process, the shape and the integrity of the bit line contact plug 261 are ensured, and the conductivity of the device is ensured.
In one example, the substrate 20 may include, but is not limited to, a silicon substrate. Specifically, the substrate 20 may include a base (not shown) and an epitaxial layer (not shown) on the upper surface of the base, and the epitaxial layer may include an N-type epitaxial layer or a P-type epitaxial layer.
In one example, the longitudinal sectional shape of the bit line contact hole 25 may include, but is not limited to, an inverted trapezoid.
In one example, the semiconductor device structure further comprises: the shallow trench isolation structure 21 is positioned in the substrate 20, and a plurality of active regions 22 distributed at intervals are isolated in the substrate 20; a plurality of word lines 23 arranged in parallel at intervals, the word lines 23 being located in the substrate 20, the extending direction of the word lines 23 intersecting the extending direction of the active region 22 at an angle smaller than 90 degrees; a filling insulating layer 24, wherein the filling insulating layer 24 is positioned on the upper surfaces of the word line 23 and the substrate 20; the bit line contact hole 25 is located between adjacent word lines 23 in the same active region 22, penetrates through the filling insulating layer 24 on the upper surface of the substrate 20 in the thickness direction, and extends into the substrate 20; the bit line 27 is electrically connected to the active region 22 via a bit line contact structure 26.
In one example, the shallow trench isolation structure 21 may be formed by forming a shallow trench (not shown) in the substrate 20 and then filling the shallow trench with an isolation material. The material of the shallow trench isolation structure 21 may include, but is not limited to, silicon oxide or silicon nitride, etc. The longitudinal cross-sectional shape of the shallow trench isolation structure 21 may be set according to actual needs, and the longitudinal cross-sectional shape of the shallow trench isolation structure 21 may include a rectangle, an inverted trapezoid, or a U-shape, where the longitudinal cross-sectional shape of the shallow trench isolation structure 10 is the U-shape in fig. 26 as an example.
In an example, the number of active regions 22 that the shallow trench isolation structures 21 can isolate in the substrate 20 can be, but is not limited to, an array as shown in fig. 24.
In one example, the word line 23 may include: an inter-gate dielectric layer 232, wherein the inter-gate dielectric layer 232 is located on the sidewall and the bottom of the trench 231, and may extend to the upper surface of the substrate 20; the first word line conducting layer 233, the first word line conducting layer 233 covers the lower sidewall and bottom of the inter-gate dielectric layer 232; the second word line conductive layer 234 and the second conductive layer 234 fill the gap inside the first word line conductive layer 233, and the upper surface of the first word line conductive layer 233 and the upper surface of the second word line conductive layer 234 are both lower than the upper surface of the substrate 20, as shown in fig. 26.
In an example, the material of the first word line conductive layer 233 may include silicon doped with As (arsenic) or B (boron), germanium doped with P (phosphorus) or As, W (tungsten), Ti (titanium), TiN (titanium nitride), or Au (gold), the material of the second word line conductive layer 234 may include W, Ti, Al (aluminum), or Pt (platinum), and the material of the first word line conductive layer 233 is different from the material of the second word line conductive layer 234; the material of the filling insulating layer 24 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, and the material of the filling insulating layer 24 may be the same as the material of the filling insulating layer 24.
In one example, bit line 27 may include a conductive body layer 272 and a top dielectric layer 274; a conductive body layer 272 is located on the upper surface of the bit line contact structure 26 and a top dielectric layer 274 is located on the upper surface of the conductive body layer 272.
In one example, the material of the conductive body layer 272 may include, but is not limited to, tungsten, and the material of the top dielectric layer 274 may include, but is not limited to, silicon nitride.
In one example, the bit line contact plug 261 may include: a first conductive layer 262 and a second conductive layer 263 disposed on an upper surface of the first conductive layer 262; the first conductive layer 262 and the second conductive layer 263 are doped, and the doping concentration of the first conductive layer 262 is greater than that of the second conductive layer 263;
in the semiconductor device structure, the conductive plug 261 is formed by the first conductive layer 262 and the second conductive layer 263: first, a first conductive layer 262 is formed to cover the sidewall of the bit line contact hole 25, a second conductive layer 263 is formed on the first conductive layer 262, the sidewall of the second conductive layer 263 in the bit line contact hole 25 has the first conductive layer 262, and the doping concentration of the second conductive layer 263 is less than that of the first conductive layer 262. When etching, due to the selectivity, the first conductive layer 262 on the sidewall of the second conductive layer 263 is preferentially etched, and the sidewall of the second conductive layer 263 may not be etched, thereby ensuring the profile of the sidewall of the second conductive layer 263. And the bottom of the first conductive layer 262 is left to form the conductive plug 261 together with the second conductive layer 263, and the highly doped first conductive layer 262 can increase the conduction rate of the bit line.
In an example, the material of the first conductive layer 262 may include doped polysilicon, metallic titanium, metallic tungsten, or metallic copper, and the like, and preferably, in the present embodiment, the first conductive layer 262 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer. The material of the second conductive layer 263 may include doped polysilicon, metal titanium, metal tungsten, or metal copper, and the like, and preferably, in this embodiment, the second conductive layer 263 may include an n-type doped polysilicon layer or a p-type doped polysilicon layer. The doping type of the second conductive layer 263 may be the same as that of the first conductive layer 262.
In one example, the concentration of the first conductive layer 262The degree may be 1 × 1018atom/cm-3～1×1022atom/cm-3The concentration of the second conductive layer 263 can be 1 × 1015atom/cm-3～1×1017atom/cm-3。
In one example, the passivation protection layer 266 may include, but is not limited to, a nitride protection layer.
In an example, the thickness of the passivation protection layer 266 may be set according to actual needs, and preferably, in this embodiment, the bottom of the passivation protection layer 266 may be 2nm to 3 nm.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A contact structure, comprising:
a conductive plug;
and the passivation protective layer covers the side wall of the conductive plug.
2. The contact structure of claim 1, wherein the conductive plug comprises: the first conducting layer and the second conducting layer on the upper surface of the first conducting layer; the first conducting layer and the second conducting layer are doped, and the doping concentration of the first conducting layer is greater than that of the second conducting layer; the passivation protective layer is a nitride protective layer.
3. A method for preparing a contact structure, comprising the steps of:
providing a substrate;
forming a conductive plug on the substrate;
and forming a passivation protection layer on the side wall of the conductive plug.
4. The method for preparing a contact structure according to claim 3,
before forming the conductive plug on the substrate, the method further comprises the following steps: forming a contact hole in the substrate;
the conductive plug is composed of a first conductive layer and a second conductive layer, and the forming of the conductive plug comprises the following steps:
forming a first conductive layer on the side wall and the bottom of the contact hole;
forming a second conductive layer on the surface of the first conductive layer; the second conducting layer and the first conducting layer are doped, and the doping concentration of the second conducting layer is smaller than that of the first conducting layer;
removing the first conductive layer on the side wall of the second conductive layer to obtain the conductive plug;
the step of forming the passivation layer on the sidewall of the conductive plug comprises the following steps:
and performing nitridation treatment on the conductive plug to form the passivation protection layer on the side wall of the conductive plug.
5. A semiconductor device structure, comprising:
the bit line contact structure comprises a substrate, wherein a bit line contact hole is formed in the substrate;
the bit line contact structure comprises a bit line contact plug and a passivation protective layer; the bit line contact plug is positioned in the bit line contact hole, and the bottom of the bit line contact plug is contacted with the bottom of the bit line contact hole; the passivation protection layer is positioned on the side wall of the bit line contact plug;
and the bit line is positioned on the upper surface of the bit line contact structure.
6. The semiconductor device structure of claim 5, further comprising:
the shallow trench isolation structure is positioned in the substrate and isolates a plurality of active regions which are distributed at intervals in the substrate;
the word lines are arranged in the substrate at intervals in parallel, and the extending direction of the word lines intersects with the extending direction of the active region at an angle smaller than 90 degrees;
the filling insulating layer is positioned on the upper surfaces of the word lines and the substrate;
the bit line contact hole is positioned between adjacent word lines in the same active region, penetrates through the filling insulating layer positioned on the upper surface of the substrate along the thickness direction and extends into the substrate; the bit line is electrically connected with the active region via the bit line contact structure.
7. The semiconductor device structure according to claim 5 or 6, wherein the bit line contact plug comprises: a first conductive layer and a second conductive layer on the first conductive layer; the first conducting layer and the second conducting layer are doped, and the doping concentration of the first conducting layer is greater than that of the second conducting layer; the passivation protection layer includes a nitride protection layer.
8. A method for manufacturing a semiconductor device structure is characterized by comprising the following steps:
providing a substrate, wherein a bit line contact hole is formed in the substrate;
forming a bit line contact structure in the bit line contact hole, and forming a bit line on the upper surface of the bit line contact structure; the bit line contact structure comprises a bit line contact plug and a passivation protective layer, the bit line contact plug is located in the bit line contact hole, the bottom of the bit line contact plug is in contact with the bottom of the bit line contact hole, and the passivation protective layer is located on the side wall of the bit line contact plug.
9. The method as claimed in claim 8, further comprising the steps of:
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions distributed at intervals in the substrate;
forming a plurality of word lines arranged at intervals in the substrate, wherein the extending direction of the word lines intersects with the extending direction of the active region at an angle smaller than 90 degrees;
forming a filling insulating layer on the upper surfaces of the word lines and the substrate; the bit line contact hole is positioned between adjacent word lines in the same active region, penetrates through the filling insulating layer positioned on the upper surface of the substrate along the thickness direction and extends into the substrate; the bit line is electrically connected with the active region via the bit line contact structure.
10. The method as claimed in claim 8 or 9, wherein forming a bit line contact structure in the bit line contact hole and forming a bit line on an upper surface of the bit line contact structure comprises:
forming a first conductive layer on the side wall and the bottom of the bit line contact hole, and forming a second conductive layer on the surface of the first conductive layer; the second conducting layer and the first conducting layer are doped, and the doping concentration of the second conducting layer is smaller than that of the first conducting layer;
forming a bit line on the upper surface of the second conductive layer;
removing the first conductive layer on the sidewall of the second conductive layer to form the bit line contact plug;
and performing nitridation treatment on the bit line contact plug to form the passivation protection layer on the side wall of the bit line contact plug.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022217782A1 (en) * | 2021-04-15 | 2022-10-20 | 长鑫存储技术有限公司 | Semiconductor device manufacturing method and semiconductor device |
| CN116489992A (en) * | 2023-06-20 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| WO2023226098A1 (en) * | 2022-05-23 | 2023-11-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| WO2023240893A1 (en) * | 2022-06-15 | 2023-12-21 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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2019
- 2019-10-11 CN CN201910963618.0A patent/CN112652570A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022217782A1 (en) * | 2021-04-15 | 2022-10-20 | 长鑫存储技术有限公司 | Semiconductor device manufacturing method and semiconductor device |
| WO2023226098A1 (en) * | 2022-05-23 | 2023-11-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| WO2023240893A1 (en) * | 2022-06-15 | 2023-12-21 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| CN116489992A (en) * | 2023-06-20 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116489992B (en) * | 2023-06-20 | 2023-11-10 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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