CN115623774A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115623774A CN115623774A CN202110783362.2A CN202110783362A CN115623774A CN 115623774 A CN115623774 A CN 115623774A CN 202110783362 A CN202110783362 A CN 202110783362A CN 115623774 A CN115623774 A CN 115623774A
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Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein a plurality of bit lines which are arranged at intervals in parallel are formed on the substrate; forming a contact plug between adjacent bit lines, and forming a metal silicide layer on the top of the contact plug, wherein the upper surface of the metal silicide layer is lower than the upper surfaces of the bit lines, and the longitudinal section of the metal silicide layer is U-shaped; forming a contact pad on the metal silicide layer, wherein the contact pad fills up a gap between adjacent bit lines; the contact pad, the metal silicide layer and the contact plug together form a storage node contact structure. The semiconductor structure and the preparation method thereof can reduce the contact resistance of the storage node contact structure, effectively reduce the risk of electric leakage of the storage node contact structure, improve the electrical performance of the semiconductor structure and improve the yield of the semiconductor structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
A Dynamic Random Access Memory (DRAM) is a semiconductor Memory commonly used in electronic devices such as computers, and is composed of a plurality of Memory cells. Wherein, the memory cell includes: a storage capacitor, and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to a word line. The source region of the transistor is used to constitute a bit line contact region to be electrically connected to a bit line through a bit line contact structure. The drain region of the transistor is used to constitute a storage node contact region to be electrically connected to the storage capacitor through the storage node contact structure.
However, as the size of the DRAM is smaller, the size of the storage node contact structure is also reduced, so that a larger contact resistance is easily generated between the transistor and the storage capacitor, which results in a slow speed of the DRAM and even a failure of a device (e.g., a chip) in which the DRAM is located. Therefore, how to reduce the contact resistance between the transistor and the storage capacitor and improve the performance of the DRAM device has become an urgent technical problem to be solved in the current advanced semiconductor process.
Disclosure of Invention
Accordingly, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce the contact resistance inside the semiconductor structure, improve the electrical performance of the semiconductor structure, and increase the yield of the semiconductor structure.
To achieve the above objects, in one aspect, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, which includes the following steps.
A substrate is provided, and a plurality of bit lines arranged at intervals in parallel are formed on the substrate.
Contact plugs are formed between adjacent bit lines, and a metal silicide layer is formed on top of the contact plugs. The upper surface of the metal silicide layer is lower than the upper surface of the bit line, and the longitudinal section of the metal silicide layer is U-shaped.
Contact pads are formed on the metal silicide layer. The contact pads fill the gaps between adjacent bit lines. The contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure.
In another aspect, some embodiments of the present disclosure provide a semiconductor structure prepared by the preparation method according to some embodiments above.
The semiconductor structure includes: a substrate and a storage node contact structure. A plurality of bit lines are formed on the substrate and arranged at intervals in parallel. The storage node contact structure includes a contact plug, a metal silicide layer and a contact pad. The contact plug is located between adjacent bit lines. The metal silicide layer is positioned on the top of the contact plug, the upper surface of the metal silicide layer is lower than the upper surface of the bit line, and the longitudinal section of the metal silicide layer is U-shaped. The contact pad is located on the metal silicide layer and fills the gap between the adjacent bit lines.
In the semiconductor structure and the method for manufacturing the same provided by the embodiment of the present disclosure, the metal silicide layer is formed on the top of the contact plug, and the upper surface of the metal silicide layer is lower than the upper surface of the bit line, so that a space is formed between the metal silicide layer and the bit line to accommodate the contact pad. The metal silicide layer has a U-shaped longitudinal cross section. Thus, after the contact pad is formed on the metal silicide layer and the contact pad fills the gap between adjacent bit lines, the contact pad and the metal silicide layer can have a larger contact area to reduce the contact resistance between the contact pad and the contact plug, i.e., reduce the contact resistance inside the semiconductor structure. Therefore, the risk of electric leakage of the storage node contact structure can be effectively reduced, the electrical performance of the semiconductor structure is improved, and the yield of the semiconductor structure is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic top view of a semiconductor structure provided in one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment;
FIG. 3 is an enlarged view of an I region of the semiconductor structure shown in FIG. 2;
FIG. 4 is an enlarged view of another I region of the semiconductor structure shown in FIG. 2;
FIG. 5 is a cross-sectional view of a contact pad provided in one embodiment;
FIG. 6 is a cross-sectional view of another contact pad provided in an embodiment;
FIG. 7 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
FIG. 8 is a schematic sectional view of the structure obtained in step S11 of the production method shown in FIG. 7;
fig. 9 is a schematic sectional view of the structure obtained in step S12 in the production method shown in fig. 7;
fig. 10 is a schematic sectional view of the structure obtained in step S13 in the production method shown in fig. 7;
fig. 11 is a flowchart illustrating a method for forming a contact plug and a metal silicide layer according to an embodiment;
fig. 12 is a schematic cross-sectional view of the structure obtained in step S121 in the manufacturing method shown in fig. 11;
fig. 13 is a schematic cross-sectional view of the structure obtained in step S122 in the manufacturing method shown in fig. 11;
fig. 14 is a schematic sectional view of the structure obtained in step S123 in the production method shown in fig. 11;
fig. 15 is a schematic cross-sectional view of the structure obtained in step S124 in the manufacturing method shown in fig. 11;
fig. 16 is a schematic cross-sectional view of the structure obtained in step S125 in the manufacturing method shown in fig. 11;
fig. 17 is a schematic cross-sectional view of the structure obtained in step S126 in the manufacturing method shown in fig. 11;
FIG. 18 is a flow chart of a method of making a contact pad provided in one embodiment;
FIG. 19 is a diagram of a process for making a contact pad provided in one embodiment;
fig. 20 is a diagram of another process for making contact pads provided in an embodiment.
Description of reference numerals:
100-semiconductor structure, 1-substrate, 10-shallow trench isolation structure, 11-insulating layer, 2-active region, 3-bit line,
31-bit line structure, 32-sidewall structure, 321-first silicon nitride layer, 322-silicon oxide layer, 323-second silicon nitride layer,
4-buried gate word line, 5-storage node contact structure, 51-contact plug, 52-metal silicide layer,
53-contact pad, 531-adhesion layer, 532-pad conductive layer, H Z The sum of the heights of the contact plug and the metal silicide layer,
H W height of bit line, W 1 -a spacing between the metal silicide layer and the bit line,
W 2 width of the inner gap of the metal silicide layer, T 1 -the thickness of the adhesive layer,
5100 contact plug material, 510 contact plug material layer, H C -the height of the layer of contact plug material,
5110 dielectric Material, 511 patterned dielectric layer, K-opening Pattern, W c -the width of the layer of contact plug material,
T 2 thickness of the patterned dielectric layer, G-groove, H S -the height of the removed part of the sidewalls of the bit lines,
512-metal layer, T 3 -thickness of metal layer, 5310-layer of adhesion material, 5320-layer of pad conductive material.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Referring to fig. 1 and 2, an embodiment of the present disclosure provides a semiconductor structure 100. The semiconductor structure 100 includes: a substrate 1, and a storage node contact structure 5 disposed on the substrate 1.
In one example, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
In one example, a shallow trench isolation structure 10 is disposed within the substrate 1. The shallow trench isolation structure 10 isolates a plurality of active regions 2 arranged in an array in the substrate 1, where the active regions 2 include a source region and a drain region (not shown in fig. 1).
Optionally, the shallow trench isolation structure 10 is silicon oxide (SiO) 2 ) And an isolation structure.
Optionally, the material of the active region 2 is polysilicon (poly), and the source region and the drain region of the active region 2 are doped regions of polysilicon.
In one example, as shown in fig. 1, a substrate 1 is formed thereon with a plurality of bit lines 3 arranged in parallel at intervals and a plurality of buried gate word lines 4 arranged in parallel at intervals. The embedded gate word lines 4 extend along a first direction, and the bit lines 3 extend along a second direction, where an included angle between the first direction and the second direction is greater than 0 ° and less than or equal to 90 °. The active region 2 crosses over the two buried gate word lines 4, a source region of the active region 2 is located between the two buried gate word lines 4 crossed by the active region 2, and a drain region of the active region 2 is located outside the two buried gate word lines 4 crossed by the active region 2.
Alternatively, as shown in fig. 2, the bit line 3 includes a bit line structure 31 and a sidewall structure 32. The bit line structure 31 includes: a conductive portion coupled corresponding to the source region of the active region 2, and an insulating portion covering the top surface of the conductive portion. Sidewall structures 32 include at least one dielectric layer. The material of the insulating portion and the dielectric layer is, for example, silicon oxide (SiO) 2 ) Or silicon nitride (Si) x N y ) At least one of (a). The conductive portion may have a single-layer structure or a stacked-layer structure, and a material of the conductive portion includes at least one of polysilicon or metal, for example.
Further alternatively, as shown in FIG. 2, some of the bit line structures 31 have bottomsThe bit line structure 31 has a bottom portion extending into the substrate 1 and coupled to a corresponding source region, and an insulating layer 11 filled in the substrate 1 is disposed on the bottom portion of the bit line structure 31, wherein the insulating layer 11 is, for example, silicon oxide (SiO) or the like 2 ) Layer or silicon nitride (Si) x N y ) And (3) a layer.
With continued reference to fig. 2, the storage node contact structure 5 includes a contact plug 51, a metal silicide layer 52, and a contact pad 53. The contact plugs 51 are located between adjacent bit lines 3. The metal silicide layer 52 is located on top of the contact plug 51, the upper surface of the metal silicide layer 52 is lower than the upper surface of the bit line 3, and the longitudinal cross-sectional shape of the metal silicide layer 52 is U-shaped. Contact pads 53 are located on metal silicide layer 52 and fill the gaps between adjacent bit lines 3.
In one example, the contact plug 51 of the storage node contact structure 5 is correspondingly coupled to the drain region of the active region 2, and the material of the contact plug 51 is, for example, polysilicon. Fig. 1 illustrates only the distribution of the active regions 2, the bit lines 3, and the buried gate word lines 4, and does not illustrate the storage node contact structures 5. Thus, the orthographic projection position of the storage node contact structure 5 on the substrate 1 can be understood from the foregoing.
In one example, the metal silicide layer 52 is, for example, a cobalt silicide (CoSi) layer.
In the embodiment of the present disclosure, the metal silicide layer 52 is located on the top of the contact plug 51, and the upper surface of the metal silicide layer 52 is lower than the upper surface of the bit line 3, so that a space is formed between the metal silicide layer 52 and the bit line 3 to accommodate the contact pad 53. The metal silicide layer 52 has a U-shaped longitudinal cross-section. After the contact pad 53 is disposed on the metal silicide layer 52 and the contact pad 53 is filled in the gap between the adjacent bit lines 3, the contact pad 53 and the metal silicide layer 52 may have a larger contact area to reduce the contact resistance between the contact pad 53 and the contact plug 51, that is, the contact resistance inside the semiconductor structure. Therefore, the risk of electric leakage of the storage node contact structure 5 can be effectively reduced, and the electrical performance of the semiconductor structure is improved, so that the yield of the semiconductor structure is improved.
In one example, as shown in fig. 3, the metal silicide layer 52 has a gap with the bit line 3, and the contact pad 53 fills the gap. In this way, the shape of the lower surface of the contact pad 53 may be "M" or "M-like" so that the contact area between the contact pad 53 and the metal silicide layer 52 may be further increased to reduce the contact resistance between the contact pad 53 and the contact plug 51.
In one example, as shown in fig. 3, the sum H of the heights of the contact plug 51 and the metal silicide layer 52 Z Is the height H of the bit line 3 W 60 to 90 percent of the total weight of the composition. For example, the sum H of the heights of the contact plug 51 and the metal silicide layer 52 Z Is the bit line 3 height H W 60%, 70%, 80% or 90%.
Here, the sum of the heights of the contact plug 51 and the metal silicide layer 52 means: the bottom surface of the contact plug 51 coupled to the active region 2 to the highest point of the metal silicide layer 52. The height of bit line 3, refers to: the bottom surface of the bit line 3 coupled to the active region 2 is sized to the top surface thereof.
Of course, in one example, it is also allowable that the sum of the heights of the contact plug 51 and the metal silicide layer 52, and the height of the bit line 3 are calculated in accordance with their respective dimensions higher than the surface of the substrate 1. The embodiments of the present disclosure are not limited thereto.
In one example, as shown in fig. 3, the contact pad 53 includes: an adhesive layer 531 and a pad conductive layer 532. The adhesion layer 531 is located on the surface of the bit line 3 where part of the sidewall is removed and on the surface of the metal silicide layer 52. The pad conductive layer 532 is positioned on the surface of the adhesive layer 531.
Here, removing part of the sidewalls of the bit lines 3 means: a portion of the sidewall structure 32 of the bit line 3 is removed to make the gap between adjacent bit lines 3 have a larger size than before the sidewall is not removed. This ensures that the contact pads 53 have a larger orthographic area on the substrate 1. Thereby advantageously ensuring good conductivity of the storage node contact structure 5 even after further scaling down of the DRAM.
Alternatively, as shown in fig. 4, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323, which are stacked in a direction away from the bit line structure 31. The thicknesses of the first silicon nitride layer 321, the silicon oxide layer 322 and the second silicon nitride layer 323 may be the same or different, and may be selected according to actual requirements. The foregoing removal of a portion of the sidewalls of the bit lines 3 refers to the removal of the material of the second silicon nitride layer 323 that is higher than the top surface of the contact plugs 51. As such, a portion of the surface of the adhesion layer 531 is in direct contact with the surface of the silicon oxide layer 322.
Further, the adhesion layer 531 may optionally include, but is not limited to, a titanium nitride (TiN) layer.
Optionally, the pad conductive layer 532 includes a metal layer. The material of the pad conductive layer 532 is, for example, at least one of tungsten (W), cobalt (Co), molybdenum (Mo), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), and lanthanum (La).
It is understood that the structure (e.g., surface shape) of the adhesive layer 531 is related to the thickness of the adhesive layer 531.
In one possible embodiment, as shown in fig. 5, the thickness T of the adhesion layer 531 is smaller than the spacing W between the metal silicide layer 52 and the bit line 3 1 And is smaller than the width W of the inner gap of the metal silicide layer 52 2 1/2 of (1). The surface of the adhesion layer 531 for contacting the pad conductive layer 532 thus has irregularities, so that the lower surface of the pad conductive layer 532 has an "M" shape or an "M" like shape. It is thereby possible to increase the contact area between the pad conductive layer 532 and the adhesive layer 531 to reduce the contact resistance between the pad conductive layer 532 and the adhesive layer 531.
In another possible embodiment, as shown in fig. 6, the adhesion layer 531 fills the gap between the metal silicide layer 52 and the bit line 3 and the gap inside the metal silicide layer 52. Thus, the surface of the adhesion layer 531 for contacting the pad conductive layer 532 easily has two convex portions, so that the lower surface of the pad conductive layer 532 is uneven. It is thereby possible to increase the contact area between the pad conductive layer 532 and the adhesive layer 531 to reduce the contact resistance between the pad conductive layer 532 and the adhesive layer 531.
Referring to fig. 7, an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, which is used to fabricate the semiconductor structure 100 in some embodiments described above. The preparation method comprises the following steps.
S11: a substrate is provided, and a plurality of bit lines arranged at intervals in parallel are formed on the substrate.
S12: contact plugs are formed between adjacent bit lines, and a metal silicide layer is formed on top of the contact plugs. The upper surface of the metal silicide layer is lower than the upper surface of the bit line, and the longitudinal section of the metal silicide layer is U-shaped.
S13: contact pads are formed on the metal silicide layer. The contact pads fill the gaps between adjacent bit lines. The contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure.
In the embodiment of the disclosure, the metal silicide layer is formed on the top of the contact plug, so that the upper surface of the metal silicide layer is lower than the upper surface of the bit line, and the longitudinal section of the metal silicide layer is U-shaped, thereby ensuring that a space is formed between the metal silicide layer and the bit line to accommodate the contact pad. Thus, after the contact pad is formed on the metal silicide layer and the gap between adjacent bit lines is filled up by the contact pad, a larger contact area can be formed between the contact pad and the metal silicide layer, so that the contact resistance between the contact pad and the contact plug is reduced, and the contact resistance in the semiconductor structure is also reduced. Therefore, the risk of electric leakage of the storage node contact structure can be effectively reduced, the electrical performance of the semiconductor structure is improved, and the yield of the semiconductor structure is improved.
In step S11, referring to S11 in fig. 7 and fig. 8, a substrate 1 is provided, and a plurality of bit lines 3 arranged in parallel and at intervals are formed on the substrate 1.
In one example, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. The substrate 1 is provided with a shallow trench isolation structure 10, and the shallow trench isolation structure 10 is, for example, silicon oxide (SiO) 2 ) And an isolation structure. The shallow trench isolation structure 10 isolates a plurality of active regions 2 arranged in an array in the substrate 1, and the active regions 2 include a source region and a drain region. The material of the active region 2 is, for example, polysilicon (poly), and the source region and the drain region of the active region 2 are doped regions of polysilicon.
In the alternative,as shown in fig. 8, the bit line 3 includes a bit line structure 31 and a sidewall structure 32. The bit line structure 31 includes: a conductive part correspondingly coupled with the source region of the active region 2, and an insulating part covered on the top surface of the conductive part. Sidewall structures 32 include at least one dielectric layer. The material of the insulating part and the dielectric layer is, for example, silicon oxide (SiO) 2 ) Or silicon nitride (Si) x N y ) At least one of (1). The conductive portion may have a single-layer structure or a stacked-layer structure, and the material of the conductive portion includes, for example, at least one of polysilicon or metal.
In addition, optionally, as shown in fig. 8, the bottom of some bit line structures 31 extends into the substrate 1 and is coupled to the corresponding source region, the peripheral side of the bottom of the bit line structure 31 is further provided with an insulating layer 11 filled in the substrate 1, and the insulating layer 11 is, for example, silicon oxide (SiO) 11 2 ) Layer or silicon nitride (Si) x N y ) A layer.
In step S12, referring to S12 in fig. 7 and fig. 9, a contact plug 51 is formed between adjacent bit lines 3, and a metal silicide layer 52 is formed on top of the contact plug 51. The upper surface of the metal silicide layer 52 is lower than the upper surface of the bit line 3, and the vertical cross-sectional shape of the metal silicide layer 52 is U-shaped.
Optionally, the contact plug 51 is coupled to the drain region of the active region 2, and the material of the contact plug 51 is, for example, polysilicon. The metal silicide layer 52 is, for example, a cobalt silicide (CoSi) layer.
In step S13, referring to S13 in fig. 7 and fig. 10, a contact pad 53 is formed on the metal silicide layer 52. The contact pad 53 fills the gap between the adjacent bit lines 3.
Alternatively, as shown in fig. 10, the contact pad 53 includes: an adhesive layer 531 and a pad conductive layer 532. The adhesion layer 531 is located on the surface of the bit line 3 where part of the sidewall is removed and on the surface of the metal silicide layer 52. The pad conductive layer 532 is positioned on the surface of the adhesive layer 531.
Alternatively, as shown in fig. 10, there is a gap between the metal silicide layer 52 and the bit line 3, and the contact pad 53 fills the gap.
From above, the contact pad 53 constitutes the storage node contact structure 5 together with the metal silicide layer 52 and the contact plug 51.
In one example, referring to fig. 11, step S12 forms a contact plug between adjacent bit lines and a metal silicide layer on top of the contact plug, including the steps described below.
S121: a contact plug material layer is formed between adjacent bit lines, and the upper surface of the contact plug material layer is lower than the upper surfaces of the bit lines.
S122: and forming a patterned dielectric layer on the side wall of the bit line.
S123: and forming a groove in the contact plug material layer based on the patterned dielectric layer.
S124: and removing partial side walls of the patterned dielectric layer and the bit lines.
S125: and forming a metal layer on the surface of the contact plug material layer.
S126: and annealing the obtained structure to obtain the contact plug and the metal silicide layer.
In the embodiment of the present disclosure, the metal silicide layer is obtained by metalizing the contact plug material layer, and the manufacturing process of the metal silicide layer can be simplified. And the cross section shape of the metal silicide layer is obtained based on the groove formed in the contact plug material layer, so that the forming difficulty of the metal silicide layer can be reduced on the basis of ensuring the forming shape of the metal silicide layer.
In step S121, please refer to S121 in fig. 11 and fig. 12, a contact plug material layer 510 is formed between the adjacent bit lines 3, wherein the upper surface of the contact plug material layer 510 is lower than the upper surface of the bit line 3.
Here, the contact plug material layer 510 may be obtained by, but not limited to, a deposition process and an etching process.
For example, as shown in fig. 12 (a), a contact plug material 5100 is deposited on the substrate 1, so that the contact plug material 5100 fills the gap between each adjacent two bitlines 3 and covers the bitlines 3. As shown in fig. 12 (b), the contact plug material 5100 is etched using an etching process, forming the contact plug material layer 510. The etching process is, for example, wet etching.
Alternatively, as shown in (b) of fig. 12, the height H of the contact plug material layer 510 C Is bit line 3 highDegree H W 60 to 90 percent of the total weight of the steel. For example, the height H of the contact plug material layer 510 C Is the height H of the bit line 3 W 60%, 70%, 80% or 90%.
Here, the height of the contact plug material layer 510 refers to: the contact plug material layer 510 has a size from a bottom surface coupled to the active region 2 to a top surface thereof. The height of bit line 3, refers to: the bottom surface of the bit line 3 coupled to the active region 2 is sized to its top surface. Of course, in one example, it is also allowable that the height of the contact plug material layer 510, and the height of the bit line 3 are calculated according to their dimensions above the surface of the substrate 1, respectively. The embodiments of the present disclosure are not limited thereto.
In step S122, referring to S122 in fig. 11 and fig. 13, a patterned dielectric layer 511 is formed on the sidewall of the bit line 3.
Optionally, the patterned dielectric layer 511 includes, but is not limited to, silicon nitride (Si) x N y ) And (3) a layer. The patterned dielectric layer 511 can be obtained by, but not limited to, a deposition process and an etching process. The Deposition process is, for example, a Chemical Vapor Deposition (CVD) process. The etching process is, for example, a dry etching process.
Illustratively, as shown in fig. 13 (a), a dielectric material 5110 is deposited on the substrate 1, such that the dielectric material 5110 covers the bit line 3, the sidewall of the bit line 3 and the contact plug material layer 510. As shown in (b) of fig. 13, a dry etching process is used to remove a portion of the dielectric material 5110 covering the surface of the contact plug material layer 510, so as to form the patterned dielectric layer 511, so that the patterned dielectric layer 511 has an opening pattern K. The orthogonal projection shape of the opening pattern K on the substrate 1 is, for example, a circle, a square, an ellipse, or the like.
Alternatively, as shown in (b) of fig. 13, the thickness T of the patterned dielectric layer 511 2 Is the width W of the contact plug material layer 510 C 1/6 to 1/3 of (1/6). For example, the thickness T of the patterned dielectric layer 511 2 Is the width W of the contact plug material layer 510 C 1/6, 1/5, 1/4, or 1/3 of (1/3).
In step S123, referring to S123 in fig. 11 and fig. 14, a recess G is formed in the contact plug material layer 510 based on the patterned dielectric layer 511.
For example, as shown in fig. 14, the contact plug material layer 510 is etched by a dry etching process through the opening pattern K in the patterned dielectric layer 511 to form a groove G in the contact plug material layer 510. The depth of the groove G can be set according to actual requirements.
In step S124, referring to S124 of fig. 11 and fig. 15, portions of the sidewalls of the patterned dielectric layer 511 and the bit lines 3 are removed.
Optionally, the material of the patterned dielectric layer 511 is the same as the material of the part of the sidewall of the bit line 3 to be removed, and the patterned dielectric layer 511 and the part of the sidewall of the bit line 3 may be removed at one time by using the same etching process. For example, as shown in fig. 15, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 which are stacked in a direction away from the bit line structure 31. The patterned dielectric layer 511 is a silicon nitride layer. A portion of the material of the second silicon nitride layer 323 and the patterned dielectric layer 511 may be removed by a phosphoric acid wet etching process. In this case, the silicon oxide layer 322 can serve as an etching stopper layer during the phosphoric acid wet etching.
Optionally, the height H of the removed part of the sidewall of the bit line 3 S Is the bit line 3 height H W 20 to 80 percent of the total weight of the composition. For example, the height H of the removed part of the sidewall of the bit line 3 S Is the height H of the bit line 3 W 20%, 40%, 60% or 80%.
Here, the height of the bit line 3 means: the bottom surface of the bit line 3 coupled to the active region 2 is sized to the top surface thereof. Of course, it is also permissible, in one example, for the height of the bit lines 3 to be calculated in each case in terms of their dimension above the surface of the substrate 1. The embodiments of the present disclosure do not limit this.
In addition, the height H of the removed part of the sidewall of the bit line 3 S In contrast, the surface area of the subsequently formed metal silicide layer 52 for contacting the contact pad 53 is different. For example, the height H of the removed part of the sidewall of the bit line 3 S The larger the dimension, the larger the surface area of the subsequently formed metal silicide layer 52 for contacting the contact pad 53.
In step S125, referring to S125 in fig. 11 and fig. 16, a metal layer 512 is formed on the surface of the contact plug material layer 510.
Optionally, the thickness T of the metal layer 512 formed on the surface of the contact plug material layer 510 3 5nm to 16nm. For example, the thickness T of the metal layer 512 3 Is 5nm, 8nm, 10nm, 12nm or 16nm.
Alternatively, the material of the metal layer 512 includes, but is not limited to, metal cobalt (Co).
In step S126, please refer to S126 in fig. 11 and fig. 17, an annealing process is performed on the resulting structure to obtain the contact plug 51 and the metal silicide layer 52.
Optionally, the annealing temperature for annealing the resulting structure is 300 ℃ to 700 ℃, for example, 300 ℃, 500 ℃, or 700 ℃.
After annealing the resulting structure, a portion of the material of the contact plug material layer 510 is metalized, especially the portion of the contact plug material layer 510 where the recess G is formed. For example, the material of the contact plug material layer 510 is converted from polysilicon to cobalt silicide. Thus, the contact plug 51 and the metal silicide layer 52 can be obtained by using different portions of the contact plug material layer 510.
It is understood that, after the annealing process is performed on the resulting structure to obtain the contact plug 51 and the metal silicide layer 52, the method for manufacturing the semiconductor structure further includes: the remaining metal layer 512 is removed.
Here, the residual metal layer 512 refers to a metal element, such as metallic cobalt, still remaining on the surface of the contact plug material layer 510 after the annealing treatment.
In addition, the remaining metal layer 512 may be removed by a wet etching process, for example, by cleaning with a diluted sulfur peroxide mixed solution. The diluted sulfur peroxide mixed solution comprises: sulfuric acid (H) 2 SO 4 ) Hydrogen peroxide (H) 2 O 2 ) And water (H) 2 O)。
In one example, referring to fig. 18, step S13 forms a contact pad on the metal silicide layer, including the steps described below.
S131: and forming an adhesion layer on the surface of the bit line with the part of the side wall removed and the surface of the metal silicide layer.
S132: and forming a pad conductive layer on the surface of the adhesion layer.
In the embodiment of the disclosure, the adhesion layer is formed on the surface of the bit line and the surface of the metal silicide layer, where part of the sidewall is removed, and then the pad conductive layer is formed on the surface of the adhesion layer, so that the adhesion between the pad conductive layer and the metal silicide layer, and between the pad conductive layer and the sidewall of the bit line, can be enhanced by using the adhesion layer, and on the basis of ensuring that the contact pad has good conductivity, good connection between the contact pad and the metal silicide layer, and between the contact pad and the sidewall of the bit line is ensured, thereby ensuring the use reliability of the semiconductor structure.
In step S131, referring to S131 in fig. 18 and fig. 19 and 20, an adhesion layer 531 is formed on the surface of the bit line 3 and the surface of the metal silicide layer 52 with a portion of the sidewall removed.
Alternatively, the material of the adhesion layer 531 includes, but is not limited to, titanium nitride. The adhesion layer 531 is also referred to as a metal barrier layer.
In step S132, please refer to S131 in fig. 18 and fig. 19 and 20, a pad conductive layer 532 is formed on the surface of the adhesion layer 531.
Alternatively, the material of the pad conductive layer 532 includes, but is not limited to, metal tungsten (W).
It is understood that the adhesion layer 531 and the pad conductive layer 532 may be prepared by a deposition process and an etching process. For example, an adhesion material layer and a pad conductive material layer are sequentially deposited and then etched to obtain an adhesion layer 531 and a pad conductive layer 532.
In addition, the structures (e.g., surface shapes) of the adhesion layer 531 and the pad conductive layer 532 are related to the thickness of the corresponding material layer.
In one possible implementation, as shown in (a) of fig. 19, an adhesion material layer 5310 is deposited on the surface of the bit line 3 and the surface of the metal silicide layer 52, where a portion of the sidewall is removed, and the thickness of the adhesion material layer 5310 is less than 1/2 of the spacing between the metal silicide layer 52 and the bit line 3 and less than 1/2 of the width of the gap inside the metal silicide layer 52, so that the surface of the adhesion material layer 5310 for the contact pad conductive layer 532 has irregularities.
Then, as shown in (b) of fig. 19, a pad conductive material layer 5320 is deposited on the surface of the adhesion material layer 5310.
Thereafter, as shown in (c) of fig. 19, the pad conductive material layer 5320 and the adhesive material layer 5310 are etched to form an adhesive layer 531 and a pad conductive layer 532. In this manner, the lower surface of the pad conductive layer 532 has an "M" shape or an "M-like" shape. This can increase the contact area between the pad conductive layer 532 and the adhesive layer 531 to reduce the contact resistance between the pad conductive layer 532 and the adhesive layer 531.
In another possible implementation, as shown in fig. 20 (a), an adhesion material layer 5310 is deposited on the surface of the bit line 3 and the surface of the metal silicide layer 52, where part of the sidewall is removed, and the adhesion material layer 5310 fills the gap between the metal silicide layer 52 and the bit line 3 and the gap inside the metal silicide layer 52, so that the surface of the adhesion material layer 5310 for contacting the pad conductive layer 532 has two protrusions.
Then, as shown in (b) of fig. 20, a pad conductive material layer 5320 is deposited on the surface of the adhesion material layer 5310.
Thereafter, as shown in (c) of fig. 20, the pad conductive material layer 5320 and the adhesion material layer 5310 are etched to form an adhesion layer 531 and a pad conductive layer 532. In this way, the lower surface of the pad conductive layer 532 is uneven, and the contact area between the pad conductive layer 532 and the adhesive layer 531 can be increased to reduce the contact resistance between the pad conductive layer 532 and the adhesive layer 531.
The contact pad 53 is constituted by the adhesive layer 531 and the pad conductive layer 532.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (19)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a plurality of bit lines which are arranged in parallel at intervals are formed on the substrate;
forming a contact plug between adjacent bit lines, and forming a metal silicide layer on the top of the contact plug, wherein the upper surface of the metal silicide layer is lower than that of the bit lines, and the longitudinal section of the metal silicide layer is U-shaped;
forming a contact pad on the metal silicide layer, wherein the contact pad fills a gap between adjacent bit lines; the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure.
2. The method of claim 1, wherein a gap is formed between the metal silicide layer and the bit line, and the contact pad fills the gap.
3. The method of claim 1, wherein forming contact plugs between adjacent bit lines and forming a metal silicide layer on top of the contact plugs comprises:
forming a contact plug material layer between adjacent bit lines, wherein the upper surface of the contact plug material layer is lower than the upper surfaces of the bit lines;
forming a graphical dielectric layer on the side wall of the bit line;
forming a groove in the contact plug material layer based on the graphical dielectric layer;
removing the patterned dielectric layer and partial side walls of the bit lines;
forming a metal layer on the surface of the contact plug material layer;
and annealing the obtained structure to obtain the contact plug and the metal silicide layer.
4. The method of claim 3, wherein the height of the contact plug material layer is 60% to 90% of the height of the bit line.
5. The method of claim 3, wherein the thickness of the patterned dielectric layer is 1/6 to 1/3 of the width of the contact plug material layer.
6. The method of claim 3, wherein the height of the removed sidewall of the bit line is 20-80% of the height of the bit line.
7. The method for manufacturing a semiconductor structure according to claim 3, wherein the annealing temperature for annealing the obtained structure is 300 ℃ to 700 ℃.
8. The method of claim 3, wherein the metal layer formed on the surface of the contact plug material layer has a thickness of 5nm to 16nm.
9. The method for fabricating a semiconductor structure according to claim 3, wherein the annealing the resulting structure to obtain the contact plug and the metal silicide layer further comprises: and removing the residual metal layer.
10. The method of any of claims 1 to 9, wherein the forming a contact pad on the metal silicide layer comprises:
forming an adhesion layer on the surface of the bit line with the partial side wall removed and the surface of the metal silicide layer;
and forming a pad conductive layer on the surface of the adhesion layer.
11. The method of claim 10, wherein the step of forming the semiconductor structure comprises the step of forming the semiconductor structure,
the thickness of the adhesion layer is less than 1/2 of the spacing between the metal silicide layer and the bit line and less than 1/2 of the width of the gap inside the metal silicide layer.
12. The method of claim 10, wherein the adhesion layer fills a gap between the metal silicide layer and the bit line and a gap inside the metal silicide layer.
13. A semiconductor structure, comprising:
the bit line array comprises a substrate, a plurality of bit lines and a plurality of bit lines, wherein the plurality of bit lines are arranged on the substrate at intervals in parallel;
and a storage node contact structure including a contact plug, a metal silicide layer, and a contact pad; wherein the contact plug is located between adjacent bit lines; the metal silicide layer is positioned at the top of the contact plug, the upper surface of the metal silicide layer is lower than the upper surface of the bit line, and the longitudinal section of the metal silicide layer is U-shaped; the contact pad is positioned on the metal silicide layer and fills a gap between the adjacent bit lines.
14. The semiconductor structure of claim 13, wherein the metal silicide layer has a gap with the bitline, and the contact pad fills the gap.
15. The semiconductor structure of claim 13, wherein a sum of a height of the contact plug and a height of the metal silicide layer is 60% to 90% of the height of the bit line.
16. The semiconductor structure of claim 13, wherein the contact pad comprises:
the adhesion layer is positioned on the surface of the bit line with the part of the side wall removed and the surface of the metal silicide layer;
and the pad conducting layer is positioned on the surface of the adhesion layer.
17. The semiconductor structure of claim 16, wherein a thickness of the adhesion layer is less than 1/2 of a spacing between the metal silicide layer and the bit line and less than 1/2 of a width of a gap inside the metal silicide layer.
18. The semiconductor structure of claim 16, wherein the adhesion layer fills gaps between the metal silicide layer and the bit lines and gaps inside the metal silicide layer.
19. The semiconductor structure of any one of claims 16-18, wherein the adhesion layer comprises a titanium nitride layer and the pad conductive layer comprises a metal layer.
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