TWI832916B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI832916B
TWI832916B TW108138695A TW108138695A TWI832916B TW I832916 B TWI832916 B TW I832916B TW 108138695 A TW108138695 A TW 108138695A TW 108138695 A TW108138695 A TW 108138695A TW I832916 B TWI832916 B TW I832916B
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Taiwan
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semiconductor layer
substrate
transistor
semiconductor
semiconductor device
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TW108138695A
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TW202017056A (zh
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雷維基 森古普塔
洪俊九
麥克 羅德爾
瓦西里歐斯 康斯坦提諾斯 吉勞西
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南韓商三星電子股份有限公司
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Abstract

本揭露提供一種半導體裝置及其製造方法。根據本揭露的一些示例性實施例，一種半導體裝置包括：基底；位於所述基底上的第一半導體層，所述第一半導體層是第一類型的半導體裝置；以及位於所述基底及所述第一半導體層上的第二半導體層，所述第二半導體層是所述第一類型的半導體裝置，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移。本揭露的半導體裝置可具有高密度的電子組件。

Description

半導體裝置及其製造方法
本發明的一些示例性實施例的方面指向一種半導體裝置及其製造方法。相關申請的交叉參考
本申請主張在2018年10月25日提出申請的標題為“用于單片3DIC的單極堆疊場效應電晶體（UNIPOLAR STACKED FET FOR MONOLITHIC 3DIC）”的美國臨時專利申請第62/750,696號的優先權及權益，所述美國臨時專利申請的全部內容併入本文供參考。
半導體裝置普遍存在於現代電子產品中。半導體裝置在電子組件的數量及密度方面各不相同。分立半導體裝置一般含有一種類型的電子組件，例如發光二極體（light emitting diode，LED）、小訊號電晶體、電阻器、電容器、電感器及功率金屬氧化物半導體場效應電晶體（metal oxide semiconductor field effect transistor，MOSFET）。積體半導體裝置通常含有數百到數百萬個電子組件。
在此背景技術部分中的上述訊息僅用於增強對技術背景的理解，且因此不應被解釋為承認現有技術的存在或相關性。
本發明的一些示例性實施例的方面指向一種半導體裝置及其製造方法。
根據本揭露的一些示例性實施例，一種半導體裝置包括：基底；位於所述基底上的第一半導體層，所述第一半導體層是第一類型的半導體裝置；以及位於所述基底及所述第一半導體層上的第二半導體層，所述第二半導體層是所述第一類型的半導體裝置，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移。
根據一些示例性實施例，所述半導體裝置更包括：位於所述基底上的第三半導體層，所述第三半導體層是不同於所述第一類型的半導體裝置的第二類型的半導體裝置；以及位於所述基底上的第四半導體層，所述第四半導體層是所述第二類型的半導體裝置。
根據一些示例性實施例，當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
根據一些示例性實施例，所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
根據一些示例性實施例，當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的閘區的第一部分與所述第二電晶體及所述第四電晶體的閘區重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的所述閘區的第二部分從所述第二電晶體及所述第四電晶體的所述閘區橫向偏移。
根據一些示例性實施例，對應於所述第一半導體層的第一源極或汲極與對應於所述第二半導體層的第一源極或汲極接觸，並且對應於所述第一半導體層的第二源極或汲極與對應於所述第二半導體層的第二源極或汲極橫向隔離。
根據一些示例性實施例，所述半導體裝置更包括位於所述基底與所述第一半導體層之間的掩埋電源軌（buried power rail）。
根據本揭露的一些示例性實施例，一種半導體裝置包括：第一半導體層，所述第一半導體層是第一類型的半導體裝置；第一閘區，至少部分地包封所述第一半導體層；位於所述第一半導體層上的第二半導體層，所述第二半導體層是所述第一類型的半導體裝置；以及第二閘區，至少部分地包封所述第二半導體層，其中當沿著z方向觀察時，所述第一半導體層、所述第一閘區的第一部分、所述第二半導體層及所述第二閘區重疊，並且當沿著所述z方向觀察時，所述第一閘區的第二部分從所述第二閘區橫向偏移。
根據一些示例性實施例，所述半導體裝置更包括基底，其中當沿著所述z方向觀察時，所述第一半導體層、所述第一閘區、所述第二半導體層及所述第二閘區形成在所述基底上。
根據一些示例性實施例，當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移。
根據一些示例性實施例，所述半導體裝置更包括：位於所述基底上的第三半導體層，所述第三半導體層是不同於所述第一類型的半導體裝置的第二類型的半導體裝置；以及位於所述基底上的第四半導體層，所述第四半導體層是所述第二類型的半導體裝置。
根據一些示例性實施例，當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
根據一些示例性實施例，所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
根據本揭露的一些示例性實施例，在一種製造半導體裝置的方法中，所述方法包括：在基底上形成第一半導體層，所述第一半導體層是第一類型的半導體裝置；以及在所述基底及所述第一半導體層上形成第二半導體層，所述第二半導體層是所述第一類型的半導體裝置，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移。
根據一些示例性實施例，所述方法更包括：在所述基底上形成第三半導體層，所述第三半導體層是不同於所述第一類型的半導體裝置的第二類型的半導體裝置；以及在所述基底上形成第四半導體層，所述第四半導體層是所述第二類型的半導體裝置。
根據一些示例性實施例，當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
根據一些示例性實施例，所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
根據一些示例性實施例，當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的閘區的第一部分與所述第二電晶體及所述第四電晶體的閘區重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的所述閘區的第二部分從所述第二電晶體及所述第四電晶體的所述閘區橫向偏移。
根據一些示例性實施例，對應於所述第一半導體層的第一源極或汲極與對應於所述第二半導體層的第一源極或汲極接觸，並且對應於所述第一半導體層的第二源極或汲極與對應於所述第二半導體層的第二源極或汲極橫向隔離。
根據一些示例性實施例，所述方法更包括在所述基底與所述第一半導體層之間形成掩埋電源軌。
根據一些示例性實施例，所述第一半導體層和所述第二半導體層中的至少一者包括奈米片層、奈米線層或鰭層。
現在將詳細參照本發明總體概念的實施例，本發明總體概念的實例在附圖中示出，其中相同的參考編號在通篇中指代相同的元件。以下描述實施例，以便在參照圖式的同時解釋本發明的總體概念。
通過參照以下對實施例的詳細描述及附圖，可更容易地理解本發明的方面及特徵以及實現這些方面及特徵的方法。然而，本發明總體概念可以許多不同的形式實施，並且不應被解釋為僅限於在本文中闡述的實施例。相反，提供這些實施例是為了使本揭露徹底及完整，並將本發明總體概念的概念完全傳達給所屬領域中的技術人員，並且本發明總體概念將僅由所附申請專利範圍限定。
在闡述本發明的上下文中（尤其在以上申請專利範圍的上下文中）使用的用語“一（a及an）”及“所述（the）”以及相似的指示語應被視為涵蓋單數及複數兩者，除非另外指明或明顯與上下文相矛盾。除非另外注明，否則用語“包括（comprising）”、“具有（having）”、“包含（including）”及“含有（containing）”應被視為開放式用語（即，意指“包括但不限於”）。
除非另外定義，否則在本文所用所有技術及科學用語的含意均與本發明所屬領域中的普通技術人員所通常理解的含意相同。應注意，除非另外規定，否則使用本文所提供的任何及所有實例或示例性用語僅旨在更好地說明本發明而並非限制本發明的範圍。另外，除非另外定義，否則常用字典中定義的所有用語均不能被過度解釋。
半導體裝置執行多種功能，例如訊號處理、高速計算、發送及接收電磁訊號、控制電子裝置、將陽光轉換成電能以及為電視顯示器創建視覺投影。半導體裝置存在於娛樂、通訊、電力轉換、網絡、計算機及消費品領域。半導體裝置也存在於軍事應用、航空、汽車、工業控制器及辦公設備中。積體半導體裝置的實例包括微控制器、微處理器、電荷耦合裝置（charge-coupled device，CCD）、太陽能電池及數位微鏡裝置（digital micro-mirror device，DMD）。
半導體裝置利用半導體材料的電性質。半導體材料的原子結構允許通過施加電場或基極電流（base current）或通過摻雜製程來操縱其導電率。摻雜將雜質引入半導體材料，以操縱及控制半導體裝置的導電性。
半導體裝置包含主動電結構（active electrical structure）及被動電結構（passive electrical structure）。包括雙極及場效應電晶體在內的主動結構控制電流的流動。通過改變摻雜水平及施加電場或基極電流，電晶體促進或限制電流的流動。包括電阻器、電容器及電感器在內的被動結構在電壓與電流之間建立起執行各種電功能所必需的關係。被動結構與主動結構電連接以形成電路，所述電路使得半導體裝置能夠執行高速計算及其他有用的功能。
半導體裝置一般使用兩個複雜的製造過程（即，前端製造及後端製造）製造而成，每個製程都可能涉及數百個步驟。前端製造涉及在半導體晶圓（wafer）的表面上形成多個晶粒（die）。每個半導體晶粒通常彼此相同，並且含有通過電連接主動組件與被動組件而形成的電路。後端製造涉及從完成的晶圓將個別半導體晶粒單體化、並封裝所述晶粒以提供結構支撐及環境隔離。在本文中使用的術語“半導體晶粒”指用語的單數及複數形式，並且因此可指單個半導體裝置及多個半導體裝置兩者。
半導體製造的一個目標是生產較小的半導體裝置。較小的裝置通常消耗較少的功率，具有較高的性能，並且可被更高效地生產。此外，較小的半導體裝置具有較小的占用區域，此對於較小的最終產品來說是可取的。通過前端製程的改善可實現較小的半導體晶粒尺寸，從而使得半導體晶粒具有較小、較高密度的主動組件及被動組件。後端製程可通過改善電互連及封裝材料而使得半導體裝置封裝具有較小的占用區域。
圖1示出根據一些示例性實施例的在其表面安裝有各種半導體封裝的電子裝置。如圖1所示，電子裝置50包括在其表面上安裝有多個半導體封裝的晶片載體基底或印刷電路板（PCB）52。依據應用，電子裝置50可具有一種類型的半導體封裝、或多種類型的半導體封裝。出於說明的目的，在圖1中示出了不同類型的半導體封裝。
電子裝置50可以是使用半導體封裝來執行一種或多種電功能的獨立系統（stand-alone system）。作為另一選擇，電子裝置50可以是更大系統的子組件。舉例來說，電子裝置50可以是手機（cellular phone）、個人數位助理（personal digital assistant，PDA）、數位攝影機（digital video camera，DVC）或其他電子通訊裝置的一部分。作為另一選擇，電子裝置50可以是圖形卡、網絡接口卡或可插入計算機中的其他訊號處理卡。根據一些實施例，電子裝置50可以是被配置為存儲電子數據的記憶體裝置。半導體封裝可包括微處理器、記憶體、專用積體電路（application specific integrated circuit，ASIC）、邏輯電路、模擬電路、射頻電路、分立裝置或其他半導體晶粒或電子組件。
在圖1中，印刷電路板52提供用於安裝在印刷電路板上的半導體封裝的結構支撐及電互連的通用基板。使用蒸鍍、電解鍍覆、無電鍍、絲網印刷或其他合適的金屬沉積製程，在印刷電路板52的表面上或層內形成導電訊號跡線（conductive signal trace）54。導電訊號跡線54在半導體封裝、所安裝組件及其他外部系統組件中的每一者之間提供電通訊。導電訊號跡線54還為半導體封裝中的每一者提供電源及接地連接。
在一些實施例中，半導體裝置具有兩個封裝級（packaging level）。第一級封裝是一種將半導體晶粒機械地（mechanically）及電性地（electrically）附接到中間載體的技術。第二級封裝涉及將中間載體機械地及電性地附接到印刷電路板。在其他實施例中，半導體裝置可僅具有其中晶粒直接機械地及電性地安裝到印刷電路板的第一級封裝。
出於說明的目的，在印刷電路板52上示出了幾種類型的第一級封裝，包括接合線封裝（bond wire package）56及倒裝晶片（flipchip）58。另外，幾種類型的第二級封裝（包括球柵陣列（ball grid array，BGA）60、凸塊晶片載體（bump chip carrier，BCC）62、雙列直插封裝（dual in-line package，DIP）64、接腳柵陣列（land grid array，LGA）66、多晶片模組（multi-chip module，MCM）68、四方扁平無引線封裝（quad flat non-leaded package，QFN）70及四方扁平封裝72）被示出為安裝在印刷電路板52上。依據系統設計，配置有第一級封裝樣式及第二級封裝樣式的任意組合的半導體封裝的任意組合以及其他電子組件可連接到印刷電路板52。在一些實施例中，電子裝置50包括單個附接半導體封裝，而其他實施例可包括多個互連封裝。
隨著主動組件及被動組件的占用區域持續變小，在半導體晶粒上橫向增加組件的密度變得越來越困難。因此，根據一些示例性實施例的半導體組件及封裝通過相對於半導體基底的x-y平面在z軸上構建多層主動組件而利用主動組件的堆疊三維（three-dimensional，3D）佈置來增加相對較小占用區域中的組件密度。
利用例如n在p上（n-on-p）堆疊方法的相關技術結構可在P型組件的頂部形成N型組件，反之亦可，此意味著底部源極/汲極（例如，P型源極/汲極）可形成在下層上，且頂部源極/汲極（例如，N型源極/汲極）可z方向形成在底部源極/汲極的頂部上。類似地，對於閘極來說，不同功函數金屬可用於不同層（tier）中的組件。因此，n在p上堆疊結構的製造過程可能相當複雜。
相反，根據本揭露的一些示例性實施例可重疊n在n上（n-over-n）或p在p上（p-over-p）組件，從而提高製造效率，因為相同類型的組件在z方向上堆疊在彼此頂部。另外，根據本揭露的一些示例性實施例可減少熱預算（thermal budget）問題，因為在彼此頂部形成相同類型的組件的製造過程可減少原本可能發生的對較低層組件的損壞。一些示例性實施例可進一步促進低成本及組件之間的複雜性互連。
舉例來說，如下文將更詳細示出及解釋，根據一些示例性實施例的半導體裝置可包括多個堆疊的或重疊的奈米片層，這些奈米片層以用於不同功能的配置形式放置，其中在堆疊裝置的源極端子、汲極端子及閘極端子之間存在隔離。每層奈米片可形成不同的裝置或組件。根據半導體裝置的設計，可適當地形成源極端子、汲極端子及閘極端子之間的互連，並且也可形成與不同層中的組件的源極端子及汲極端子的電源連接。
儘管可在本說明書通篇中使用術語奈米片層，但實施例並不僅限於奈米片層；相反，實施例可包括各種半導體層，例如奈米片、奈米線或鰭狀層。
圖2A是示出根據一些示例性實施例的半導體裝置的各方面的剖視圖。圖2B示出根據一些示例性實施例，示出半導體裝置的另一些方面的剖視圖。具體來說，圖2A及圖2B是示出通過利用多層的裝置的用於半導體裝置200中的多個主動半導體裝置組件的互連方案的方塊圖。半導體裝置200可以是例如相對於圖1中的電子裝置50示出的半導體封裝中的一者。
圖2A及圖2B所示的半導體裝置200可包括基底202（例如，體矽基底（bulk-silicon substrate）或絕緣體上矽（silicon-on-insulator，SOI）基底）。半導體裝置200還可包括形成在基底202上的多層半導體裝置組件。圖2A及圖2B所示的半導體裝置200示出位於金屬層208下方的兩層（tier）（或層（layer））（204及206）主動組件，但本發明的實施例並不僅限於兩層組件，且不同的示例性實施例可包括多於兩層組件。此外，如下文將進一步詳細示出，不同的層可包括多個奈米片層，這些奈米片層被配置成在同一層內形成多個組件。
每一層可包括獨特的組件，這些組件可與其他層或同一層中的組件電連接或電隔離，以根據電路的設計執行不同的邏輯功能。舉例來說，如圖2所示，組件的第一層（或頂層）204可包括可連接到金屬層208的各種訊號線的源區210、汲區212及閘區214，以形成主動半導體組件，例如N型電晶體或P型電晶體。源區/汲區210/212可具有相應的源極/汲極216/218，源極/汲極216/218包含與源區210和/或汲區212接觸的任何合適的導電材料。另外，閘區214可具有相應的電極220，電極220包含與閘區214接觸的任何合適的導電材料。
類似於第一層（或頂層）204，組件的第二層（或底層）206可包括可電連接到金屬層208的各種訊號線的源區222、汲區224及閘區226，以形成主動半導體組件，例如N型電晶體或P型電晶體。源區/汲區222/224可具有相應的源極/汲極228/230，源極/汲極228/230包含與源區222和/或汲區224接觸的任何合適的導電材料。閘區226可具有相應的電極232，電極232包含與閘區226接觸的任何合適的導電材料。閘區226的導電子組件與基底202電隔離。
電極216/218/220/228/230/232可通過一個或多個通孔234電連接到金屬層208的一個或多個訊號線或電源線。
因此，一些示例性實施例可利用多個閘極連接（例如，220及232）來將相應的組件層連接到金屬層208。舉例來說，如圖2A所示，不同層204及206中的不同半導體組件的閘區（例如，214及226）可通過在基底202的x-y平面中彼此橫向偏移的獨立閘極220及232而連接到金屬層208，使得不同層中的組件的閘極彼此橫向偏移。
圖2B示出根據一些示例性實施例的半導體裝置200的進一步的細節，其中半導體裝置200進一步垂直互連到掩埋電源軌236，用於向底層206和/或頂層204提供功率和/或電訊號。如圖2B所示，根據一些示例性實施例，一層或多層任何合適的導電材料的掩埋電源軌236可形成在基底202上和/或掩埋在基底202內。可形成掩埋通孔（buried via）238，以將半導體裝置200的組件電連接到掩埋電源軌236。舉例來說，如圖2B所示，掩埋通孔238可被形成為將底部源區/汲區222/224（和/或源極/汲極228/230）電連接到掩埋電源軌236，但實施例並不僅限於此。在一些實施例中，可形成多個掩埋通孔238，以將半導體裝置200的各種其他組件或區（例如，在任意層中）電連接到掩埋電源軌236。
圖3示出根據一些示例性實施例的半導體裝置的三維透視圖。圖4示出根據一些示例性實施例的半導體裝置的另一個三維透視圖。如圖3所示，半導體裝置200的每一層可包括閘區。
舉例來說，底層206可包括底部閘區226，且頂層204可包括頂部閘區214。此外，每個層可包括多個奈米片層，以形成例如源區及汲區（例如，底部源區/汲區222/224及頂部源區/汲區210/212）。
舉例來說，底部源極及汲極區可包括由第一奈米片層形成的第一源區222及由第二奈米片層形成的第一汲區224，並且第一源區222、第一汲區224及底部閘區226可共同形成第一電晶體（例如，P型電晶體）239。底部源極及汲極區可另外包括由第三奈米片層形成的第二源區240及由第四奈米片層形成的第二汲區242。第二源區240、第二汲區242及底部閘區226可共同形成第二電晶體（例如，N型電晶體）244。
類似地，頂部源極及汲極區可包括由第五奈米片層形成的第三源區210及由第六奈米片層形成的第三汲區212。第三源區210、第三汲區212及第三閘區214可共同形成第三電晶體（例如，P型電晶體）246。頂部源極及汲極區可另外包括由第七奈米片層形成的第四源區250及由第八奈米片層形成的第四汲區252。第四源區250、第四汲區252及頂部閘區214可共同形成第四電晶體（例如，N型電晶體）254。
儘管圖3所示的實施例示出包括四個電晶體的半導體裝置200，但根據半導體裝置200的設計，本發明的實施例可包括額外的電晶體或更少的電晶體，並且可包括額外的主動組件。
在製造過程期間，可適當地對各種奈米片層及閘區進行摻雜以形成P型或N型電晶體。如圖3所示，每個奈米片層可被其相應的閘區包封或圍繞，並且相同類型（例如，P型或N型）的組件可被形成為在z方向上重疊。舉例來說，如圖3所示，第一電晶體239與第三電晶體246可以是相同類型的電晶體（例如，P型或N型），且第二電晶體244與第四電晶體254可以是相同類型的電晶體（例如，P型或N型）。出於說明的目的，假設電晶體239及電晶體246可以是例如P型電晶體，並且電晶體244及電晶體254可以是N型電晶體，但實施例並不僅限於此。
如圖3所示，第一電晶體239與第三電晶體246在z方向上彼此重疊，且第二電晶體244與第四電晶體254在z方向上彼此重疊。第一電晶體239、第二電晶體244、第三電晶體246及第四電晶體254中的每一者可具有電連接到相應電晶體的源區及汲區的相應源極/汲極（例如，電極216/218/228/230）。根據半導體裝置200的電路設計，源極/汲極還可與半導體裝置200中的其他組件電互連或隔離。
根據一些示例性實施例，根據半導體裝置200的電路結構，不同層中的奈米片層可橫向偏移，以使得較低層中的源極/汲極能夠繞過較高層中的奈米片層及組件。舉例來說，如圖3及圖4所示，頂層204中的奈米片層250及252在x-y平面中至少部分地從底層206中的奈米片層240及242橫向偏移，使得底層206中的奈米片層240及242的至少一部分不與頂層204中的奈米片層250及252沿z方向重疊，從而使得對應於底層206中的奈米片層240及242的電極能夠連接到底層206中的奈米片層240及242，而不會穿過頂層204中的奈米片層250及252或通過頂層204中的奈米片層250及252短路。
依據半導體裝置200的電路設計，頂層源極/汲極可彼此電連接或電隔離。在半導體裝置200的正面透視圖中，頂部源極/汲極216/218可直接電連接到底部源極/汲極228/230，使得底部源極/汲極228/230物理上鄰近並接觸頂部源極/汲極216/218，並且底部源極/汲極228/230穿過頂層奈米片層210及212或通過頂層奈米片層210及212短路。在電晶體254及電晶體244的頂部源極/汲極與底部源極/汲極之間可存在類似的直接電連接。
相反，如圖4所示，依據半導體裝置200的電路設計，一個或多個底層源極/汲極可與頂層源極汲極電隔離和/或物理隔離。舉例來說，如圖4所示，對應於底層電晶體244的底部源極/汲極270/272可橫向偏移，並且與頂層電晶體254的奈米片層250及252以及對應於頂層電晶體254的頂部源極/汲極274/276物理及電隔離。也就是說，底部源極/汲極270/272不穿過奈米片層250及252或通過奈米片層250及252短路，因為奈米片層240及242在x-y平面中至少部分地沿著z方向從奈米片層250及252橫向偏移。
圖5示出根據一些示例性實施例的半導體裝置200的俯視圖或佈局圖。如圖5所示，與相關技術結構相反，金屬層208的電壓供應線（例如，VDD及GND）位於閘極訊號線之間。舉例來說，如圖5所示，金屬層208可包括連接到底部閘區226（例如圖3所示）的第一閘極訊號線208-A。金屬層208還可包括連接到頂部閘區226（例如圖3所示）的第二閘極訊號線208-B。一條或多條源極或汲極訊號線208-Y可連接到半導體裝置200的組件的源區或汲區。最後，金屬層208可包括高壓線208-VDD及低壓線208-GND，高壓線208-VDD及低壓線208-GND可根據半導體裝置200的設計連接到半導體裝置200的組件的源區或汲區中的一者或多者。
如圖3到圖5所示，底部閘區226與頂部閘區214在z方向上部分重疊，但在x-y平面中也橫向偏移，使得底部閘區226與頂部閘區214不完全重疊，並且電極232能夠電連接到底部閘區226，而不會穿過頂部閘區214或通過頂部閘區214短路。另外，如圖5所示，與高壓線及低壓線位於單元的外部邊界或邊緣的相關技術結構相反，高壓線208-VDD、低壓線208-GND和/或源極或汲極訊號線208-Y可位於第一閘極訊號線208-A與第二閘極訊號線208-B之間，從而使得下層閘區（例如，底部閘區226）能夠連接到第一閘極訊號線208-A，而不會通過頂部或較高層閘區214短路。
因此，如以上參照圖1到圖5所示及所述，根據本揭露的一些示例性實施例可包括多個相同類型（例如，P型或N型）的堆疊溝道裝置。儘管以上相對於半導體裝置200描述的溝道裝置被表徵為形成有奈米片層的電晶體，但本發明的實施例並不僅限於此，並且還可包括半導體層，舉例來說，半導體層可以是奈米線、鰭場效應電晶體（FinFET）或任何其他合適的主動溝道組件。如上所述，底部溝道與頂部溝道可在整個半導體裝置內彼此電隔離及物理隔離，以形成可根據整個半導體裝置的電路設計互連的各種不同的半導體組件。頂部源區及汲區與底部源區及汲區可彼此電隔離及物理隔離，以形成不同的源極端子及汲極端子。此外，底部閘區與頂部閘區可彼此電隔離及物理隔離，以形成不同的閘極端子。一些示例性實施例可包括頂層源極/汲極接觸件及導電層，所述頂層源極/汲極接觸件將頂層源極/汲極端子連接到第一通孔級（first via level），所述導電層用於接收高/低功率電壓和/或數據訊號。一些示例性實施例可包括將底層源極/汲極端子連接到頂層源極/汲極接觸件的底層源極/汲極接觸件。一些示例性實施例還可包括將底層源極/汲極端子連接到頂層源極/汲極端子的底層源極/汲極接觸件。根據一些示例性實施例，底層源極/汲極接觸件可將底層源極汲極端子連接到第一通孔級。
一些示例性實施例還可包括將底層閘極端子連接到第一通孔級的底層閘極接觸件。一些示例性實施例還可包括交錯的頂層及底層溝道單元架構，其使得源區、汲區及閘區的底層接觸件能夠連接到第一通孔級，而不連接到頂層溝道端子或穿過頂層溝道端子。入站（inbound）電源軌及訊號線可根據上述交錯排列形式進行排列。
一些示例性實施例還可包括兼容的掩埋電源軌架構，所述架構能夠實現具有改善密度的較短單元。
根據一些示例性實施例，彼此重疊的堆疊溝道裝置可以是相同類型（例如，P型或N型）且可包含任何合適的半導體材料（包括例如Si、SiGe、III-V、TMD），並且根據各種實施例，所述半導體材料可以是晶體或非晶體的。此外，如上所述的各種接觸件、電源軌或通孔級可由任何合適的導電或金屬材料（包括例如Ti、Ta、TiN、TaN、Co、Ru、Cu及W）形成。
儘管已經在某些具體實施例中描述了本揭露，但所屬領域中的技術人員將不難設想出對所描述的實施例的變型，此決不背離本揭露的範圍。此外，對於各種領域中的技術人員來說，本文中的公開內容本身將建議對其他任務的解決方案及對其他應用的適應性。申請人的意圖是通過申請專利範圍覆蓋本揭露的所有這些用途以及在不背離本揭露的範圍的情況下可對本文中為了公開目的而選擇的本揭露的實施例作出的那些改變及修改。因此，本揭露的當前實施例在所有方面都應被認為是說明性的而非限制性的，本揭露的範圍將由所附申請專利範圍及其等效形式而不是前面的描述來指示。
50:電子裝置 52:印刷電路板（PCB） 54:導電訊號跡線 56:接合線封裝 58:倒裝晶片 60:球柵陣列（BGA） 62:凸塊晶片載體（BCC） 64:雙列直插封裝（DIP） 66:接腳柵陣列（LGA） 68:多晶片模組（MCM） 70:四方扁平無引線封裝（QFN） 72:四方扁平封裝 200:半導體裝置 202:基底 204:第一層/頂層 206:第二層/底層 208:金屬層 208-A:第一閘極訊號線 208-B:第二閘極訊號線 208-GND:低壓線 208-VDD:高壓線 208-Y:源極或汲極訊號線 210:源區/頂部源區/第三源區/頂層奈米片層 212:汲區/頂部汲區/第三汲區/頂層奈米片層 214:閘區/第三閘區/頂部閘區/較高層閘區 216:源極/頂部源極/電極 218:汲極/頂部汲極/電極 220:電極/閘極連接/獨立閘極 222:源區/底部源區/第一源區 224:汲區/底部汲區/第一汲區 226:閘區 228:源極/底部源極/電極 230:汲極/底部汲極/電極 232:電極/閘極連接/獨立閘極 234:通孔 236:掩埋電源軌 238:掩埋通孔 239:第一電晶體/電晶體 240:第二源區/奈米片層 242:第二汲區/奈米片層 244:第二電晶體/電晶體 246:第三電晶體/電晶體 250:第四源區/奈米片層 252:第四汲區/奈米片層 254:第四電晶體/電晶體 270:底部源極 272:底部汲極 274:頂部源極 276:頂部汲極 X、Y、Z:方向軸
當結合所附圖式考慮時，由於通過參考以下詳細描述將更好地理解本揭露，因此對本揭露及其許多伴隨特徵及方面的更完整的理解將變得更易於顯而易見，在所附圖式中： 圖1示出根據一些示例性實施例的在其表面安裝有各種半導體封裝的電子裝置。 圖2A是示出根據一些示例性實施例的半導體裝置的各方面的剖視圖。 圖2B示出根據一些示例性實施例，示出半導體裝置的另一些方面的剖視圖。 圖3示出根據一些示例性實施例的半導體裝置的三維透視圖。 圖4示出根據一些示例性實施例的半導體裝置的另一個三維透視圖。 圖5示出根據一些示例性實施例的半導體裝置的俯視圖或佈局圖。
200:半導體裝置
202:基底
204:第一層/頂層
206:第二層/底層
208:金屬層
210:源區/頂部源區/第三源區/頂層奈米片層
212:汲區/頂部汲區/第三汲區/頂層奈米片層
214:閘區/第三閘區/頂部閘區/較高層閘區
216:源極/頂部源極/電極
218:汲極/頂部汲極/電極
220:電極/閘極連接/獨立閘極
222:源區/底部源區/第一源區
224:汲區/底部汲區/第一汲區
226:閘區
228:源極/底部源極/電極
230:汲極/底部汲極/電極
232:電極/閘極連接/獨立閘極
234:通孔
X、Y、Z:方向軸

Claims (20)

  1. 一種半導體裝置，包括：基底；第一半導體層，在所述基底上，所述第一半導體層是第一類型的半導體裝置且連接至第一閘極；以及第二半導體層，在所述基底及所述第一半導體層上，所述第二半導體層是所述第一類型的半導體裝置且連接至第二閘極，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移，且其中當在垂直於所述基底的所述平面的方向上觀察時，所述第一閘極從所述第二閘極橫向偏移。
  2. 如申請專利範圍第1項所述的半導體裝置，更包括：第三半導體層，在所述基底上，所述第三半導體層是不同於所述第一類型的半導體裝置的第二類型的半導體裝置；以及第四半導體層，在所述基底上，所述第四半導體層是所述第二類型的半導體裝置。
  3. 如申請專利範圍第2項所述的半導體裝置，其中當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基 底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
  4. 如申請專利範圍第2項所述的半導體裝置，其中所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
  5. 如申請專利範圍第4項所述的半導體裝置，其中當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的閘區的第一部分與所述第二電晶體及所述第四電晶體的閘區重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的所述閘區的第二部分從所述第二電晶體及所述第四電晶體的所述閘區橫向偏移。
  6. 如申請專利範圍第1項所述的半導體裝置，其中對應於所述第一半導體層的第一源極或第一汲極與對應於所述第二半導體層的第一源極或第一汲極接觸，並且對應於所述第一半導體層的第二源極或第二汲極與對應於所述第二半導體層的第二源極或第二汲極橫向隔離。
  7. 如申請專利範圍第1項所述的半導體裝置，更包括位於所述基底與所述第一半導體層之間的掩埋電源軌。
  8. 一種半導體裝置，包括：第一半導體層，所述第一半導體層是第一類型的半導體裝置； 第一閘區，至少部分地圍繞所述第一半導體層；第一閘極，連接至所述第一閘區；第二半導體層，在所述第一半導體層上，所述第二半導體層是所述第一類型的半導體裝置；第二閘區，至少部分地圍繞所述第二半導體層；以及第二閘極，連接至所述第二閘區，其中當沿著z方向觀察時，所述第一半導體層、所述第一閘區的第一部分、所述第二半導體層及所述第二閘區重疊，並且當沿著所述z方向觀察時，所述第一閘區的第二部分從所述第二閘區橫向偏移，且其中當沿著所述z方向觀察時，所述第一閘極從所述第二閘極橫向偏移。
  9. 如申請專利範圍第8項所述的半導體裝置，更包括基底，其中當沿著所述z方向觀察時，所述第一半導體層、所述第一閘區、所述第二半導體層及所述第二閘區形成在所述基底上。
  10. 如申請專利範圍第9項所述的半導體裝置，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移。
  11. 如申請專利範圍第9項所述的半導體裝置，更包括：第三半導體層，在所述基底上，所述第三半導體層是不同於 所述第一類型的半導體裝置的第二類型的半導體裝置；以及第四半導體層，在所述基底上，所述第四半導體層是所述第二類型的半導體裝置。
  12. 如申請專利範圍第11項所述的半導體裝置，其中當在垂直於所述基底的平面的方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
  13. 如申請專利範圍第11項所述的半導體裝置，其中所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
  14. 一種製造半導體裝置的方法，所述方法包括：在基底上形成第一半導體層，所述第一半導體層是第一類型的半導體裝置且連接至第一閘極；以及在所述基底及所述第一半導體層上形成第二半導體層，所述第二半導體層是所述第一類型的半導體裝置且連接至第二閘極，其中當在垂直於所述基底的平面的方向上觀察時，所述第一半導體層的第一部分與所述第二半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一半導體層的第二部分從所述第二半導體層橫向偏移，且其中當在垂直於所述基底的所述平面的方向上觀察時，所述 第一閘極從所述第二閘極橫向偏移。
  15. 如申請專利範圍第14項所述的製造半導體裝置的方法，更包括：在所述基底上形成第三半導體層，所述第三半導體層是不同於所述第一類型的半導體裝置的第二類型的半導體裝置；以及在所述基底上形成第四半導體層，所述第四半導體層是所述第二類型的半導體裝置。
  16. 如申請專利範圍第15項所述的製造半導體裝置的方法，其中當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第一部分與所述第四半導體層重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第三半導體層的第二部分從所述第四半導體層橫向偏移。
  17. 如申請專利範圍第15項所述的製造半導體裝置的方法，其中所述第一半導體層、所述第二半導體層、所述第三半導體層及所述第四半導體層分別對應於第一電晶體、第二電晶體、第三電晶體及第四電晶體。
  18. 如申請專利範圍第17項所述的製造半導體裝置的方法，其中當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電晶體的閘區的第一部分與所述第二電晶體及所述第四電晶體的閘區重疊，並且當在垂直於所述基底的所述平面的所述方向上觀察時，所述第一電晶體及所述第三電 晶體的所述閘區的第二部分從所述第二電晶體及所述第四電晶體的所述閘區橫向偏移。
  19. 如申請專利範圍第14項所述的製造半導體裝置的方法，其中對應於所述第一半導體層的第一源極或第一汲極與對應於所述第二半導體層的第一源極或第一汲極接觸，並且對應於所述第一半導體層的第二源極或第二汲極與對應於所述第二半導體層的第二源極或第二汲極橫向隔離。
  20. 如申請專利範圍第14項所述的製造半導體裝置的方法，其中所述第一半導體層和所述第二半導體層中的至少一者包括奈米片層、奈米線層或鰭層。
TW108138695A 2018-10-25 2019-10-25 半導體裝置及其製造方法 TWI832916B (zh)

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11437376B2 (en) * 2019-05-31 2022-09-06 Tokyo Electron Limited Compact 3D stacked-CFET architecture for complex logic cells
US11798940B2 (en) * 2019-06-27 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
JP2021153149A (ja) * 2020-03-24 2021-09-30 キオクシア株式会社 半導体装置
US11748543B2 (en) * 2020-04-27 2023-09-05 Taiwan Semiconductor Manufacturing Company Limited Multiple power domains using nano-sheet structures
US11532702B2 (en) * 2020-05-19 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain isolation structures for leakage prevention
US11296070B2 (en) * 2020-06-12 2022-04-05 Taiwan Semiconductor Manufacturing Company Limited Integrated circuit with backside power rail and backside interconnect
TWI763269B (zh) * 2021-01-20 2022-05-01 瑞昱半導體股份有限公司 圖案式接地防護裝置
EP4089723A1 (en) * 2021-05-14 2022-11-16 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
US11843001B2 (en) 2021-05-14 2023-12-12 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
EP4089722A1 (en) * 2021-05-14 2022-11-16 Samsung Electronics Co., Ltd. Devices including stacked nanosheet transistors
US20230046885A1 (en) * 2021-08-11 2023-02-16 Samsung Electronics Co., Ltd. Three-dimensional semiconductor device having vertical misalignment
US11948974B2 (en) * 2021-08-30 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including vertical transistor with back side power structure
WO2023099000A1 (en) * 2021-12-02 2023-06-08 Imec Vzw A complementary field-effect transistor device
US20230187509A1 (en) * 2021-12-14 2023-06-15 Intel Corporation Stacked transistors with removed epi barrier
US20230207468A1 (en) * 2021-12-28 2023-06-29 International Business Machines Corporation Stacked staircase cmos with buried power rail
US20240162229A1 (en) * 2022-11-10 2024-05-16 International Business Machines Corporation Stacked fet with extremely small cell height

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570395B1 (en) * 2015-11-17 2017-02-14 Samsung Electronics Co., Ltd. Semiconductor device having buried power rail
US20170117291A1 (en) * 2015-10-24 2017-04-27 Monolithic 3D Inc. Semiconductor memory device, structure and methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5624415B2 (ja) 2010-09-21 2014-11-12 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5651415B2 (ja) 2010-09-21 2015-01-14 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US9177890B2 (en) 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
WO2015081413A1 (en) 2013-12-05 2015-06-11 Conversant Intellectual Property Management Inc. A three dimensional non-volatile memory with charge storage node isolation
US9659963B2 (en) 2015-06-29 2017-05-23 International Business Machines Corporation Contact formation to 3D monolithic stacked FinFETs
WO2017111866A1 (en) 2015-12-26 2017-06-29 Intel Corporation Dynamic logic built with stacked transistors sharing a common gate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170117291A1 (en) * 2015-10-24 2017-04-27 Monolithic 3D Inc. Semiconductor memory device, structure and methods
US9570395B1 (en) * 2015-11-17 2017-02-14 Samsung Electronics Co., Ltd. Semiconductor device having buried power rail

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