TWI826709B - 半導體裝置以及其製造方法 - Google Patents

半導體裝置以及其製造方法 Download PDF

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TWI826709B
TWI826709B TW109125489A TW109125489A TWI826709B TW I826709 B TWI826709 B TW I826709B TW 109125489 A TW109125489 A TW 109125489A TW 109125489 A TW109125489 A TW 109125489A TW I826709 B TWI826709 B TW I826709B
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insulating layer
pattern
semiconductor
gate
gate electrode
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TW109125489A
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TW202118052A (zh
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孫洛辰
李昇俊
楊奉燮
崔道永
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南韓商三星電子股份有限公司
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Abstract

一種半導體裝置包括：基板，包括週邊區；第一主動圖案，設置於基板的週邊區上，第一主動圖案所具有的上部部分包括交替堆疊的第一半導體圖案與第二半導體圖案；第一閘極電極，與第一主動圖案相交；成對的第一源極/汲極圖案，分別設置於第一閘極電極的兩側處；以及第一閘極絕緣層，設置於第一閘極電極與第一主動圖案之間。第一閘極絕緣層包括：第一絕緣層，形成於第一主動圖案上；第二絕緣層，形成於第一絕緣層上；以及高介電常數介電層，形成於第二絕緣層上。第一閘極絕緣層包含第一偶極元素，第一偶極元素包括鑭（La）、鋁（Al）或其組合。

Description

半導體裝置以及其製造方法
[相關申請案的交叉參考]
本專利申請案主張於2019年10月25日在韓國智慧財產局中提出申請的韓國專利申請案第10-2019-0133518號的優先權，所述韓國專利申請案的揭露內容全文併入本案供參考。
本發明概念的示例性實施例是有關於一種半導體裝置及一種製造所述半導體裝置的方法，且更具體而言有關於一種包括場效電晶體的半導體裝置及一種製造所述半導體裝置的方法。
金屬氧化物半導體場效電晶體(Metal-oxide-semiconductor field effect transistor，MOSFET)是在超大規模積體電路中廣泛使用的半導體裝置。由於半導體裝置的積體度隨著電子工業的進步而變得越來越高，已根據半導體裝置的簡化設計規則將MOSFET按比例減小。半導體裝置的操作特性可能由於MOSFET的大小減小而劣化。因此，已研究用於形成在克服高積體度的限制的同時具有極佳效能的半導體裝置的各種方法。
本發明概念的示例性實施例可提供一種具有增強的電性特性的半導體裝置及一種製造所述半導體裝置的方法。
在一個態樣中，一種半導體裝置可包括：基板，包括週邊區；第一主動圖案，設置於所述基板的所述週邊區上，所述第一主動圖案所具有的上部部分包括交替堆疊的第一半導體圖案與第二半導體圖案；第一閘極電極，與所述第一主動圖案相交；成對的第一源極/汲極圖案，分別設置於所述第一閘極電極的兩側處；以及第一閘極絕緣層，設置於所述第一閘極電極與所述第一主動圖案之間。所述第一閘極絕緣層可包括：第一絕緣層，形成於所述第一主動圖案上；第二絕緣層，形成於所述第一絕緣層上；以及高介電常數介電層(high-k dielectric layer)，形成於所述第二絕緣層上。所述第一閘極絕緣層可包含第一偶極元素，所述第一偶極元素包括鑭(La)、鋁(Al)或其組合。所述第一閘極絕緣層中的所述第一偶極元素的濃度可自所述第一閘極電極與所述高介電常數介電層之間的介面向所述第二絕緣層增加，可達到最大值，且然後可向所述第一絕緣層與所述第一半導體圖案中相鄰的一者之間的介面降低。
在一個態樣中，一種半導體裝置可包括：基板，包括第一區及第二區；第一主動圖案及第二主動圖案，分別設置於所述基板的所述第一區及所述第二區上；第一閘極電極及第二閘極電極，分別與所述第一主動圖案及所述第二主動圖案相交；第一閘極絕緣層，設置於所述第一閘極電極與所述第一主動圖案之間；以及第 二閘極絕緣層，設置於所述第二閘極電極與所述第二主動圖案之間。所述第一閘極絕緣層可包含第一偶極元素，所述第一偶極元素包括鑭(La)、鋁(Al)或其組合。所述第二閘極絕緣層可包含第二偶極元素，所述第二偶極元素包括鑭(La)或鋁(Al)。所述第一閘極絕緣層的厚度可大於所述第二閘極絕緣層的厚度。所述第一閘極絕緣層中的所述第一偶極元素的最大濃度可大於所述第二閘極絕緣層中的所述第二偶極元素的最大濃度。
在一個態樣中，一種半導體裝置可包括：基板，包括週邊區；裝置隔離層，設置於所述基板的所述週邊區上以界定第一主動圖案；成對的第一源極/汲極圖案，設置於所述第一主動圖案上；第一半導體圖案及第二半導體圖案，設置於所述成對的第一源極/汲極圖案之間，其中所述第一半導體圖案與所述第二半導體圖案交替堆疊於所述第一主動圖案上，且所述第二半導體圖案中最下部的一者的底表面高於所述裝置隔離層的頂表面；第一閘極電極，在所述第一主動圖案上與所述第一半導體圖案及所述第二半導體圖案相交；第一閘極絕緣層，設置於所述第一閘極電極與所述第一半導體圖案及所述第二半導體圖案之間；成對的閘極間隔件，分別設置於所述第一閘極電極的兩個側壁上；閘極頂蓋圖案，設置於所述第一閘極電極上；第一層間絕緣層，設置於所述閘極頂蓋圖案上；主動接觸件，穿透所述第一層間絕緣層且電性連接至所述成對的第一源極/汲極圖案中的至少一者；第二層間絕緣層，設置於所述第一層間絕緣層上；以及第一金屬層，設置於所述第二層間絕緣 層中且電性連接至所述主動接觸件。所述第一閘極絕緣層可包括：第一絕緣層，形成於所述第一半導體圖案及所述第二半導體圖案上；第二絕緣層，形成於所述第一絕緣層上；以及高介電常數介電層，形成於所述第二絕緣層上。所述高介電常數介電層可設置於所述第二絕緣層與所述第一閘極電極之間。所述第一閘極絕緣層可包含偶極元素。所述偶極元素在所述第一閘極電極與所述高介電常數介電層之間的介面處的濃度可小於所述偶極元素在所述第一絕緣層與所述第一半導體圖案中相鄰的一者之間的介面處的濃度。
在一個態樣中，一種製造半導體裝置的方法可包括：形成交替堆疊於基板上的第一半導體層與第二半導體層；將所述第一半導體層及所述第二半導體層圖案化以形成包括第一半導體圖案及第二半導體圖案的主動圖案；在所述主動圖案上依序形成第一絕緣層及第一金屬氧化物層，所述第一金屬氧化物層包含選自鑭(La)及鋁(Al)的第一偶極元素；對所述第一金屬氧化物層執行第一退火製程(annealing process)以將所述第一偶極元素擴散至所述第一絕緣層中；在執行所述第一退火製程之後在所述主動圖案上形成源極/汲極圖案；以及形成與所述主動圖案相交的閘極電極。
100:基板
110:第一層間絕緣層
120:第二層間絕緣層
130:第三層間絕緣層
A-A’、B-B’、C-C’、D-D’、E-E’、F-F’、G-G’、H-H’:線
AC:主動接觸件
AP1:第一主動圖案
AP2:第二主動圖案
AP3:第三主動圖案
AP4:第四主動圖案
BM:障壁圖案
BS:底表面
CH1:第一通道圖案
CH2:第二通道圖案
CH3:第三通道圖案
CH4:第四通道圖案
CN1:第一濃度
CN2:第二濃度
CN3:第三濃度
D1:第一方向
D2:第二方向
D3:第三方向
DPL1:第一金屬氧化物層
DPL2:第二金屬氧化物層
EG:第一絕緣層
ET1:第一空的空間
ET2:第二空的空間
ET3:第三空的空間
FM:導電圖案
GC:閘極接觸件
GE1:第一閘極電極
GE2:第二閘極電極
GI1:第一閘極絕緣層
GI2:第二閘極絕緣層
GP:閘極頂蓋圖案
GS:閘極間隔件
HK:高介電常數介電層
IL:第二絕緣層
IP:絕緣圖案
LGC:邏輯單元區
M:區
M1:第一互連線
MA:遮罩層
MP:硬遮罩圖案
NR1:第一N型MOSFET(NMOSFET)區
NR2:第二NMOSFET區
PER:週邊區
PP1:第一犧牲圖案
PP2:第二犧牲圖案
PR1:第一P型MOSFET(PMOSFET)區
PR2:第二PMOSFET區
RS1:第一凹陷區
RS2:第二凹陷區
SC:矽化物圖案
SD1:源極/汲極圖案/第一源極/汲極圖案
SD2:源極/汲極圖案/第二源極/汲極圖案
SD3:第三源極/汲極圖案
SD4:第四源極/汲極圖案
SP1:第一半導體圖案
SP2:第二半導體圖案
ST:裝置隔離層
SW:側壁
T1:第一厚度
T2:第二厚度
TR1:第一溝槽
TR2:第二溝槽
TR3:第三溝槽
TR4:第四溝槽
TS:頂表面
V1:第一通孔
V2:第二通孔
W1:第一寬度
W2:第二寬度
藉由結合隨附圖式閱讀對示例性實施例的以下說明，本發明概念將變得更顯而易見且更易於理解，在隨附圖式中：圖1是示出根據本發明概念的示例性實施例的半導體裝置的 平面圖。
圖2A至圖2H分別是沿著圖1所示的線A-A’、B-B’、C-C’、D-D’、E-E’、F-F’、G-G’及H-H’截取的剖視圖。
圖3是圖2A所示的區「M」的放大剖視圖。
圖4、圖6、圖8、圖10、圖12及圖14是示出根據本發明概念的示例性實施例的製造半導體裝置的方法的平面圖。
圖5A、圖7A、圖9A、圖11A、圖13A及圖15A分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線A-A’截取的剖視圖。
圖5B、圖7B、圖9B、圖11B、圖13B及圖15B分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線B-B’截取的剖視圖。
圖5C、圖7C、圖9C、圖11C、圖13C及圖15C分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線C-C’截取的剖視圖。
圖5D、圖7D、圖9D、圖11D、圖13D及圖15D分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線D-D’截取的剖視圖。
圖11E、圖13E及圖15E分別是沿著圖10、圖12及圖14所示的線E-E’截取的剖視圖。
圖11F、圖13F及圖15F分別是沿著圖10、圖12及圖14所示的線F-F’截取的剖視圖。
圖16A及圖16B分別是沿著圖12所示的線C-C’及F-F’截取以示出根據本發明概念的示例性實施例的製造半導體裝置的方法的剖視圖。
圖17A、圖17B及圖17C分別是沿著圖1所示的線A-A’、B-B’及C-C’截取以示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
由於圖1至圖17C中的圖式旨在用於例示性目的，因此圖式中的元件未必按比例繪製。舉例而言，出於清晰目的，所述元件中的一些可能被放大或誇大。
圖1是示出根據本發明概念的示例性實施例的半導體裝置的平面圖。圖2A至圖2H分別是沿著圖1所示的線A-A’、B-B’、C-C’、D-D’、E-E’、F-F’、G-G’及H-H’截取的剖視圖。
參照圖1，可提供包括週邊區PER及邏輯單元區LGC的基板100。基板100可為包含例如矽(Si)、鍺(Ge)或矽鍺(SiGe)的半導體基板，或者可為化合物半導體基板。在本發明概念的示例性實施例中，基板100可為包含矽(Si)(例如，單晶矽(Si)、多晶矽(polycrystalline silicon，p-Si)、非晶矽(amorphous silicon，a-Si)或其組合)的矽(Si)基板，及/或可包含例如矽鍺(SiGe)、絕緣體上矽鍺(silicon germanium on insulator，SGOI)、銻化銦(InSb)、鉛碲化合物(PbTe)、磷化鎵(GaP)、砷化銦(InAs)、磷化銦(InP)、砷化鎵(GaAs)或銻化鎵(GaSb)等其他材料。 週邊區PER可為上面設置有構成處理器核心的電晶體或輸入/輸出(input/output，I/O)端子的區。邏輯單元區LGC可為上面設置有構成邏輯電路的標準單元的區。週邊區PER可環繞邏輯單元區LGC，但本發明概念不限於此。處理器核心可形成於週邊區PER中，以控制例如形成於邏輯單元區LGC中的邏輯電路的功能。週邊區PER的電晶體的操作功率可高於邏輯單元區LGC的電晶體的操作功率。在下文中，將參照圖1及圖2A至圖2D詳細闡述週邊區PER的電晶體。
週邊區PER可包括第一P型MOSFET(P-type MOSFET，PMOSFET)區PR1及第一N型MOSFET(N-type MOSFET，NMOSFET)區NR1。第一PMOSFET區PR1及第一NMOSFET區NR1可由形成於基板100的上部部分中的第二溝槽TR2界定。換言之，第二溝槽TR2可設置於第一PMOSFET區PR1與第一NMOSFET區NR1之間，且可將第一PMOSFET區PR1與第一NMOSFET區NR1分隔開。第一PMOSFET區PR1與第一NMOSFET區NR1可在第一方向D1上彼此間隔開，第二溝槽TR2夾置於第一PMOSFET區PR1與第一NMOSFET區NR1之間。
形成於基板100的上部部分中的第一溝槽TR1可界定第一主動圖案AP1及第二主動圖案AP2，且第一主動圖案AP1及第二主動圖案AP2可分別設置於第一PMOSFET區PR1及第一NMOSFET區NR1上。第一溝槽TR1可較第二溝槽TR2淺。第一主動圖案AP1及第二主動圖案AP2可具有在與第一方向D1交叉 的第二方向D2上延伸的線形狀或棒形狀。然而，本發明概念不限於此。舉例而言，第一主動圖案AP1及第二主動圖案AP2可各自設置成在不同於第一方向D1及第二方向D2的方向上延伸的斜棒形狀。第一主動圖案AP1及第二主動圖案AP2可為基板100的垂直突出的部分。
裝置隔離層ST可填充第一溝槽TR1及第二溝槽TR2，且可包括氧化矽(SiO2)層。第一主動圖案AP1及第二主動圖案AP2的上部部分可自裝置隔離層ST垂直向上突出(參見圖2C)。裝置隔離層ST可不覆蓋第一主動圖案AP1及第二主動圖案AP2的上部部分，且可覆蓋第一主動圖案AP1及第二主動圖案AP2的下部部分的側壁。
第一主動圖案AP1及第二主動圖案AP2中的每一者的上部部分可包括交替堆疊的第一半導體圖案SP1與第二半導體圖案SP2。彼此相鄰的第一半導體圖案SP1可以夾置於其間的第二半導體圖案SP2而在垂直方向(即，垂直於第一方向D1及第二方向D2的第三方向D3)上彼此間隔開。交替堆疊的第一半導體圖案SP1與第二半導體圖案SP2可彼此垂直交疊。在本發明概念的示例性實施例中，第二半導體圖案SP2中最下部的一者的底表面可高於裝置隔離層ST的頂表面。
第一半導體圖案SP1可包含矽(Si)、鍺(Ge)及矽鍺(SiGe)中的一者，且第二半導體圖案SP2可包含矽(Si)、鍺(Ge)及矽鍺(SiGe)中不同於第一半導體圖案SP1中所包含的所述一 者的另一者。舉例而言，第一半導體圖案SP1可包含矽(Si)，且第二半導體圖案SP2可包含矽鍺(SiGe)。
第一主動圖案AP1的上部部分中可設置有成對的第一源極/汲極圖案SD1。第一源極/汲極圖案SD1可為包含具有第一導電類型(例如，P型)的摻雜劑的摻雜區。P型摻雜劑可包括例如硼(B)、鋁(Al)、鎵(Ga)、銦(In)或其組合。第一通道圖案CH1可界定在所述成對的第一源極/汲極圖案SD1之間。第一通道圖案CH1可包括設置於所述成對的第一源極/汲極圖案SD1之間的第一半導體圖案SP1及第二半導體圖案SP2，且可連接所述成對的第一源極/汲極圖案SD1。
第二主動圖案AP2的上部部分中可設置有成對的第二源極/汲極圖案SD2。第二源極/汲極圖案SD2可為包含具有第二導電類型(例如，N型)的摻雜劑的摻雜區。N型摻雜劑可包括例如磷(P)、砷(As)、銻(Sb)、鉍(Bi)或其組合。第二通道圖案CH2可界定在所述成對的第二源極/汲極圖案SD2之間。第二通道圖案CH2可包括設置於所述成對的第二源極/汲極圖案SD2之間的第一半導體圖案SP1及第二半導體圖案SP2，且可連接所述成對的第二源極/汲極圖案SD2。
第一源極/汲極圖案SD1及第二源極/汲極圖案SD2可包括藉由選擇性磊晶生長(selective epitaxial growth，SEG)製程形成的磊晶圖案。在本發明概念的示例性實施例中，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2中的每一者的頂表面可設置 於與第一半導體圖案SP1中最上部的一者的頂表面的水平高度實質上相同的水平高度處。
第一源極/汲極圖案SD1可包含晶格常數大於基板100的半導體元素的晶格常數的半導體元素(例如，SiGe)。因此，第一源極/汲極圖案SD1可向第一通道圖案CH1提供壓縮應力。舉例而言，矽鍺(SiGe)可用作PMOSFET中的第一源極/汲極圖案SD1的應力源(stressor)，以將壓縮應力引入至通道且提高電洞遷移率(hole mobility)。舉例而言，較高的鍺(Ge)濃度與較高的壓縮應力二者均可有助於提高電洞遷移率。第二源極/汲極圖案SD2可包含與基板100的半導體元素相同的半導體元素(例如，Si)。作為另一選擇，第二源極/汲極圖案SD2可包含碳化矽(SiC)。
第一閘極電極GE1可在第一方向D1上延伸，且可與在第二方向D2上延伸的第一主動圖案AP1及第二主動圖案AP2相交(參見圖1)。第一閘極電極GE1可與第一通道圖案CH1及第二通道圖案CH2垂直交疊。
再次參照圖2C，第一閘極電極GE1可設置於第一通道圖案CH1及第二通道圖案CH2中的每一者的頂表面及兩個側壁上。換言之，根據本示例性實施例的週邊區PER的電晶體可為其中第一閘極電極GE1三維地環繞通道的三維(three-dimensional，3D)場效電晶體。
再次參照圖1及圖2A至圖2D，成對的閘極間隔件GS可分別設置於第一閘極電極GE1的兩個側壁上，且可在第一方向 D1上沿著第一閘極電極GE1延伸。閘極間隔件GS的頂表面可高於第一閘極電極GE1的頂表面。閘極間隔件GS的頂表面可與稍後欲闡述的第一層間絕緣層110的頂表面共面。閘極間隔件GS可包含碳氮化矽(SiCN)、氮氧化矽碳(SiCON)或氮化矽(Si3N4)中的至少一者。在本發明概念的示例性實施例中，閘極間隔件GS中的每一者可具有由碳氮化矽(SiCN)、氮氧化矽碳(SiCON)或氮化矽(Si3N4)中的至少兩者形成的多層式結構。
第一閘極電極GE1上可設置有閘極頂蓋圖案GP，且閘極頂蓋圖案GP可在第一方向D1上沿著第一閘極電極GE1延伸。閘極間隔件GS的頂表面可與閘極頂蓋圖案GP的頂表面共面，且閘極間隔件GS可覆蓋閘極頂蓋圖案GP的側壁。閘極頂蓋圖案GP可包含相對於稍後欲闡述的第一層間絕緣層110及第二層間絕緣層120具有蝕刻選擇性的材料。舉例而言，閘極頂蓋圖案GP可包含氮氧化矽(SiON)、碳氮化矽(SiCN)、氮氧化矽碳(SiCON)或氮化矽(Si3N4)中的至少一者。
第一閘極電極GE1與第一通道圖案CH1之間、第一閘極電極GE1與閘極間隔件GS之間以及第一閘極電極GE1與第二通道圖案CH2之間可設置有第一閘極絕緣層GI1，且第一閘極絕緣層GI1可沿著其上的第一閘極電極GE1的底表面延伸。第一閘極絕緣層GI1可覆蓋設置於第一閘極電極GE1下方的裝置隔離層ST的頂表面。
第一閘極絕緣層GI1可包括第一絕緣層EG，第一絕緣 層EG直接覆蓋第一通道圖案CH1及第二通道圖案CH2中的每一者的頂表面及兩個側壁。第一閘極絕緣層GI1可更包括形成於第一絕緣層EG上的第二絕緣層IL及形成於第二絕緣層IL上的高介電常數介電層HK。第二絕緣層IL可設置於第一絕緣層EG與高介電常數介電層HK之間。
在本發明概念的示例性實施例中，高介電常數介電層HK可較第二絕緣層IL厚。第一絕緣層EG可較高介電常數介電層HK厚。第一絕緣層EG及第二絕緣層IL中的每一者可包括氧化矽(SiO2)層或氮氧化矽(SiON)層。舉例而言，第一絕緣層EG及第二絕緣層IL中的每一者可包括氧化矽(SiO2)層。在此種情形中，由於第一絕緣層EG與第二絕緣層IL包含相同的材料，因此第一絕緣層EG與第二絕緣層IL之間的介面可能無法檢查或不可見。換言之，第一絕緣層EG及第二絕緣層IL可構成單一氧化矽(SiO2)層。高介電常數介電層HK可包含介電常數高於氧化矽(SiO2)的介電常數的高介電常數介電材料。舉例而言，高介電常數介電材料可包括例如氧化鉿(HfO2)、氧化鉿矽(HfSiO4)、氧化鉿鋯(HfZrO4)、氧化鉿鉭(Hf2Ta2O9)、氧化鉿鋁(HfAlO3)、氧化鑭(La2O3)、氧化鑭鋁(LaAlO3)、氧化鋯(ZrO2)、氧化鋯矽(ZrSiO4)、氧化鉭(Ta2O5)、氧化鈦(TiO2)、氧化鋇鍶鈦(BaSrTi2O6)、氧化鋇鈦(BaTiO3)、氧化鍶鈦(SrTiO3)、氧化釔(Y2O3)、氧化鋰(Li2O)、氧化鋁(Al2O3)、氧化鉛鈧鉭(Pb(Sc,Ta)O3)或鈮酸鉛鋅[Pb(Zn1/3Nb2/3)O3]中的至少一者。
第一閘極電極GE1可包括第一金屬圖案及形成於第一金屬圖案上的第二金屬圖案。第一金屬圖案可設置於第一閘極絕緣層GI1上，且可相鄰於第一通道圖案CH1及第二通道圖案CH2。第一金屬圖案可包含用於調節電晶體的臨限電壓的功函數金屬。電晶體的所期望臨限電壓可藉由調節第一金屬圖案的厚度及組成物來獲得。
第一金屬圖案可包括金屬氮化物層。舉例而言，第一金屬圖案可包含氮(N)以及選自包括例如鈦(Ti)、鉭(Ta)、鋁(Al)、鎢(W)及鉬(Mo)的群組的至少一種金屬。另外，第一金屬圖案可更包含碳(C)。在本發明概念的示例性實施例中，第一金屬圖案可控制功函數，且可包含選自例如氮化鈦(TiN)、碳化鉭(TaC)、氮化鉭(TaN)、氮化鈦矽(TiSiN)、氮化鉭矽(TaSiN)、氮化鉭鈦(TaTiN)、氮化鈦鋁(TiAlN)、氮化鉭鋁(TaAlN)、氮化鎢(WN)、碳氮化鈦鋁(TiAlCN)、碳化鈦鋁(TiAlC)、碳化鈦(TiC)、碳氮化鉭(TaCN)、氮化鈮(NbN)、碳化鈮(NbC)、氮化鋁(MoN)、碳化鉬(MoC)、碳化鎢(WC)及其組合中的一或多者。在本發明概念的示例性實施例中，第一金屬圖案可包括多個堆疊的功函數金屬層。
第二金屬圖案可包含電阻低於第一金屬圖案的電阻的金屬。舉例而言，第二金屬圖案可包含選自包括例如鎢(W)、鋁(Al)、鈦(Ti)、鉭(Ta)、釕(Ru)、鈦鋁(TiAl)、銅(Cu)、鈷(Co)、鎳(Ni)、鉑(Pt)、鎳鉑(NiPt)、鈮(Nb)、鉬(Mo)、 銠(Rh)、鈀(Pd)、銥(Ir)、鋨(Os)、銀(Ag)、金(Au)、鋅(Zn)、釩(V)及其組合的群組的至少一種金屬。
基板100上可設置有第一層間絕緣層110，且第一層間絕緣層110可覆蓋閘極間隔件GS以及第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。第一層間絕緣層110的頂表面可與閘極頂蓋圖案GP的頂表面及閘極間隔件GS的頂表面實質上共面。第二層間絕緣層120可設置於第一層間絕緣層110及閘極頂蓋圖案GP上。舉例而言，第一層間絕緣層110及第二層間絕緣層120中的每一者可包括氧化矽(SiO2)層。由於第一層間絕緣層110與第二層間絕緣層120可包含相同的材料，因此第一層間絕緣層110與第二層間絕緣層120之間的介面可能不可見。
主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110，以便分別電性連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。成對的主動接觸件AC可分別設置於第一閘極電極GE1的兩側處。當在平面圖中觀察時，主動接觸件AC可具有在第一方向D1上延伸的棒形狀(參見圖1)。主動接觸件AC的底表面可低於第一源極/汲極圖案SD1及第二源極/汲極圖案SD2的頂表面。然而，本發明概念不限於此。舉例而言，在本發明概念的示例性實施例中，主動接觸件AC的底表面可形成於與第一源極/汲極圖案SD1及第二源極/汲極圖案SD2的頂表面的平面相同的平面上。
主動接觸件AC可包括導電圖案FM及環繞導電圖案FM 的障壁圖案BM。舉例而言，導電圖案FM可包含例如鋁(Al)、銅(Cu)、鎢(W)、鉬(Mo)或鈷(Co)中的至少一種金屬。障壁圖案BM可覆蓋導電圖案FM的底表面及側壁。障壁圖案BM可包括兩個層，例如金屬層/金屬氮化物層。金屬層可包含包括例如鈦(Ti)、鉭(Ta)、鎢(W)、鎳(Ni)、鈷(Co)或鉑(Pt)中的至少一者的金屬或金屬合金。金屬氮化物層可包含例如氮化鈦(TiN)層、氮化鉭(TaN)層、氮化鎢(WN)層、氮化鎳(NiN)層、氮化鈷(CoN)層或氮化鉑(PtN)層中的至少一者。
主動接觸件AC可為自對準接觸件(self-aligned contact)。換言之，主動接觸件AC可使用閘極頂蓋圖案GP及閘極間隔件GS形成為自對準的。舉例而言，主動接觸件AC可覆蓋閘極間隔件GS的側壁的至少部分。主動接觸件AC可覆蓋閘極頂蓋圖案GP的頂表面的部分。
主動接觸件AC與第一源極/汲極圖案SD1之間以及主動接觸件AC與第二源極/汲極圖案SD2之間可分別設置有矽化物圖案SC，以提供可靠的金屬-半導體接觸且減小主動接觸件AC與第一源極/汲極圖案SD1之間以及主動接觸件AC與第二源極/汲極圖案SD2之間的電阻。主動接觸件AC可經由矽化物圖案SC電性連接至源極/汲極圖案SD1或SD2。矽化物圖案SC可包含金屬矽化物，且可包含例如矽化鈦(TiSi)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鎳(NiSi)或矽化鈷(CoSi)中的至少一者。
閘極接觸件GC可穿透第二層間絕緣層120及閘極頂蓋 圖案GP，以便電性連接至第一閘極電極GE1。閘極接觸件GC可設置於第一PMOSFET區PR1與第一NMOSFET區NR1之間的裝置隔離層ST上，且當在平面圖中觀察時，可具有在第二方向D2上延伸的棒形狀(參見圖1)。如同主動接觸件AC一樣，閘極接觸件GC可包括導電圖案FM及環繞導電圖案FM的障壁圖案BM。
第二層間絕緣層120上可設置有第三層間絕緣層130。第三層間絕緣層130中可設置有第一金屬層。舉例而言，第三層間絕緣層130可包括氧化矽(SiO2)層。第一金屬層可包括第一互連線M1、第一通孔V1及第二通孔V2。第一通孔V1及第二通孔V2可設置於第一互連線M1下方。
第一互連線M1可在第二方向D2上彼此平行地延伸，且可在第一方向D1上進行排列。第一通孔V1可設置於主動接觸件AC與第一互連線M1中對應的一者之間，以將主動接觸件AC電性連接至第一互連線M1中所述對應的一者。第二通孔V2可設置於閘極接觸件GC與第一互連線M1中對應的一者之間，以將閘極接觸件GC電性連接至第一互連線M1中所述對應的一者。
第一互連線M1與設置於第一互連線M1下方的第一通孔V1或第二通孔V2可以單一個一元體彼此連接，以構成單一導電結構。換言之，第一互連線M1與第一通孔V1或第二通孔V2可一起形成。第一互連線M1與第一通孔V1或第二通孔V2可藉由雙鑲嵌製程(dual damascene process)形成為單一導電結構。舉例而言，由第一互連線M1與第一通孔V1或第二通孔V2形成的 單一導電結構可包含例如鋁(Al)、銅(Cu)、鎢(W)、鉬(Mo)或鈷(Co)中的至少一種金屬。第三層間絕緣層130上可另外設置有堆疊的金屬層(例如，M2、M3、M4等)。
在下文中，將參照圖1及圖2E至圖2H詳細闡述邏輯單元區LGC的電晶體。出於闡釋容易及方便的目的，將省略對與參照圖1及圖2A至圖2D提及的週邊區PER的電晶體相同的技術特徵的說明。換言之，將主要闡述邏輯單元區LGC的電晶體與週邊區PER的電晶體之間的差異。
邏輯單元區LGC可包括第二PMOSFET區PR2及第二NMOSFET區NR2。第二PMOSFET區PR2及第二NMOSFET區NR2可由形成於基板100的上部部分中的第四溝槽TR4界定。換言之，第四溝槽TR4可設置於第二PMOSFET區PR2與第二NMOSFET區NR2之間，且可將第二PMOSFET區PR2與第二NMOSFET區NR2分隔開。形成於基板100的上部部分中的第三溝槽TR3可界定第三主動圖案AP3及第四主動圖案AP4。第三主動圖案AP3及第四主動圖案AP4可分別設置於第二PMOSFET區PR2及第二NMOSFET區NR2上。裝置隔離層ST亦可設置於第三溝槽TR3及第四溝槽TR4中。第三主動圖案AP3及第四主動圖案AP4的上部部分可自裝置隔離層ST垂直向上突出(參見圖2G)。
第三主動圖案AP3及第四主動圖案AP4中的每一者的上部部分可包括堆疊且彼此間隔開的第一半導體圖案SP1。堆疊的第一半導體圖案SP1可在第三方向D3上彼此間隔開。與上述 週邊區PER的電晶體不同，第三主動圖案AP3及第四主動圖案AP4可不包括第二半導體圖案SP2。舉例而言，在第一半導體圖案SP1之間未形成第二半導體圖案SP2的情況下，第一半導體圖案SP1可在第三方向D3上彼此電性絕緣。
第三主動圖案AP3的上部部分中可設置有第三源極/汲極圖案SD3。第四主動圖案AP4的上部部分中可設置有第四源極/汲極圖案SD4。成對的第三源極/汲極圖案SD3之間可界定有第三通道圖案CH3，且第三通道圖案CH3連接至所述成對的第三源極/汲極圖案SD3。成對的第四源極/汲極圖案SD4之間可界定有第四通道圖案CH4，且第四通道圖案CH4連接至所述成對的第四源極/汲極圖案SD4。第三通道圖案CH3及第四通道圖案CH4中的每一者可包括堆疊且彼此間隔開的第一半導體圖案SP1。
第三源極/汲極圖案SD3中的每一者可為包含為第一導電類型(例如，P型)的摻雜劑的磊晶圖案。第四源極/汲極圖案SD4中的每一者可為包含為第二導電類型(例如，N型)的摻雜劑的磊晶圖案。在本發明概念的示例性實施例中，第三源極/汲極圖案SD3及第四源極/汲極圖案SD4中的每一者的頂表面可設置於與第一半導體圖案SP1中最上部的一者的頂表面的水平高度實質上相同的水平高度處。
第二閘極電極GE2可在第一方向D1上彼此平行地延伸，且可與在第二方向D2上延伸的第三主動圖案AP3及第四主動圖案AP4的第三通道圖案CH3及第四通道圖案CH4相交(參 見圖1)。第二閘極電極GE2可與第三通道圖案CH3及第四通道圖案CH4垂直交疊。成對的閘極間隔件GS可分別設置於第二閘極電極GE2的兩個側壁上，且可在第一方向D1上沿著第二閘極電極GE2延伸。第二閘極電極GE2上可設置有閘極頂蓋圖案GP。
再次參照圖2G，第二閘極電極GE2可環繞第一半導體圖案SP1中的每一者。第二閘極電極GE2可設置於第一半導體圖案SP1的頂表面TS、兩個側壁SW及底表面BS上，且可環繞構成通道的第一半導體圖案SP1。換言之，根據本示例性實施例的邏輯單元區LGC的電晶體可為其中第二閘極電極GE2三維地環繞通道的3D場效電晶體(例如，閘極全環繞(gate-all-around，GAA)式多橋通道MOSFET(multi-bridge-channel MOSFET，MBCFET))。由於第二閘極電極GE2可包繞在所述多個第一半導體圖案SP1(通道)週圍，因此邏輯單元區LGC的電晶體可具有閘極全環繞(GAA)式電晶體結構。
再次參照圖1及圖2E至圖2H，第二閘極電極GE2與第三通道圖案CH3之間、第二閘極電極GE2與閘極間隔件GS之間以及第二閘極電極GE2與第四通道圖案CH4之間可設置有第二閘極絕緣層GI2。第二閘極絕緣層GI2可包括直接覆蓋第一半導體圖案SP1中的每一者的第二絕緣層IL，且可更包括形成於第二絕緣層IL上的高介電常數介電層HK。與上述第一閘極絕緣層GI1不同，第二閘極絕緣層GI2可不包括第一絕緣層EG。換言之，在邏輯單元區LGC的電晶體中可省略第一絕緣層EG。第二閘極 電極GE2及第二閘極絕緣層GI2可填充彼此垂直相鄰的第一半導體圖案SP1之間的空間。舉例而言，第二閘極電極GE2及第二閘極絕緣層GI2可環繞第一半導體圖案SP1中的每一者，同時分別覆蓋第三主動圖案AP3及第四主動圖案AP4的第三通道圖案CH3及第四通道圖案CH4。
第二NMOSFET區NR2上、第二閘極絕緣層GI2與第四源極/汲極圖案SD4之間可設置有絕緣圖案IP。第二閘極電極GE2可藉由第二閘極絕緣層GI2及絕緣圖案IP與第四源極/汲極圖案SD4間隔開。在本發明概念的示例性實施例中，絕緣圖案IP可包含例如氮化矽(Si3N4)、碳氮化矽(SiCN)、氮化矽硼(SiBN)、氮氧化矽(SiON)、碳氮氧化矽(SiOCN)、碳氮矽硼(SiBCN)、碳氧化矽(SiOC)、氧化矽(SiO2)或其組合。在本發明概念的示例性實施例中，絕緣圖案IP可包括空氣隙(air gap)。另一方面，可在第二PMOSFET區PR2上省略絕緣圖案IP。
第一層間絕緣層110及第二層間絕緣層120可設置於基板100的整個頂表面上。主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110，以便分別電性連接至第三源極/汲極圖案SD3及第四源極/汲極圖案SD4。閘極接觸件GC可穿透第二層間絕緣層120及閘極頂蓋圖案GP，以便電性連接至第二閘極電極GE2。主動接觸件AC及閘極接觸件GC可與以上參照圖1及圖2A至圖2D所述者實質上相同。
第三層間絕緣層130可設置於第二層間絕緣層120上。 第三層間絕緣層130中可設置有第一金屬層。第一金屬層可包括第一互連線M1、第一通孔V1及第二通孔V2。第三層間絕緣層130上可另外設置有堆疊的金屬層(例如，M2、M3、M4等)。第一通孔V1可將主動接觸件AC電性連接至第一互連線M1中對應的一者。第二通孔V2可將閘極接觸件GC電性連接至第一互連線M1中對應的一者。
在下文中，將更詳細地闡述週邊區PER的電晶體的第一閘極絕緣層GI1及邏輯單元區LGC的電晶體的第二閘極絕緣層GI2。
再次參照圖2A，第一閘極絕緣層GI1可包含偶極元素。因此，週邊區PER的電晶體的臨限電壓可使用第一閘極絕緣層GI1中所包含的偶極元素來調節。所述偶極元素可包括例如鑭(La)、鋁(Al)或其組合。換言之，第一閘極絕緣層GI1可包含例如鑭(La)、鋁(Al)或其組合作為雜質。
第一閘極絕緣層GI1可包括由偶極元素形成於第二絕緣層IL中或第二絕緣層IL附近的偶極介面。當第一閘極絕緣層GI1包含鑭(La)時，第一閘極電極GE1的有效功函數可降低。當第一閘極絕緣層GI1包含鋁(Al)時，第一閘極電極GE1的有效功函數可增加。藉由控制第一閘極電極GE1的有效功函數，週邊區PER的電晶體的臨限電壓可得到控制。因此，根據本示例性實施例的半導體裝置可具有高可靠性及極佳的電性特性。
第一閘極絕緣層GI1可在第一PMOSFET區PR1與第一 NMOSFET區NR1二者上包含相同的偶極元素。然而，本發明概念不限於此。為設定週邊區PER的電晶體的較低的臨限電壓，對於NMOSFET可能需要較低的功函數，或者對於PMOSFET可能需要較高的功函數。在本發明概念的示例性實施例中，第一閘極絕緣層GI1可在第一PMOSFET區PR1上包含鋁(Al)且可在第一NMOSFET區NR1上包含鑭(La)，以為週邊區PER的電晶體獲得較低的臨限電壓。在本發明概念的示例性實施例中，第一閘極絕緣層GI1可在第一PMOSFET區PR1上包含鑭(La)且可在第一NMOSFET區NR1上包含鋁(Al)，以為週邊區PER的電晶體獲得較高的臨限電壓。
圖3是圖2A所示的區「M」的放大剖視圖。圖3中示出第一閘極絕緣層GI1的偶極元素的濃度分佈曲線。參照圖3，偶極元素的濃度可自第一閘極電極GE1與高介電常數介電層HK之間的介面向第二絕緣層IL增加，可達到最大值，且然後可向第一絕緣層EG與第一半導體圖案SP1之間的介面降低。此處的第一半導體圖案SP1是第一半導體圖案SP1中相鄰於第一絕緣層EG且與第一絕緣層EG直接接觸的一者(例如，如圖2A中所示的位於頂部的一者)。
偶極元素可在第一閘極電極GE1與高介電常數介電層HK之間的介面處具有第一濃度CN1，在第二絕緣層IL中具有第二濃度CN2，且在第一絕緣層EG與第一半導體圖案SP1之間的介面處具有第三濃度CN3。第二濃度CN2可為第一閘極絕緣層 GI1中偶極元素的濃度的最大值。第三濃度CN3可大於第一濃度CN1。
再次參照圖2E，邏輯單元區LGC的電晶體的第二閘極絕緣層GI2亦可包含偶極元素。因此，邏輯單元區LGC的電晶體的臨限電壓可使用第二閘極絕緣層GI2中所包含的偶極元素來調節。換言之，第二閘極絕緣層GI2可包含例如鑭(La)或鋁(Al)作為雜質。然而，在本發明概念的示例性實施例中，第二閘極絕緣層GI2可不包含偶極元素。當第二閘極絕緣層GI2包含偶極元素時，第二閘極絕緣層GI2可包括形成於高介電常數介電層HK與第二絕緣層IL之間的偶極介面。第二閘極電極GE2的有效功函數可使用偶極元素來調節。藉由控制第二閘極電極GE2的有效功函數，邏輯單元區LGC的電晶體的臨限電壓可得到控制。因此，根據本示例性實施例的半導體裝置可具有高可靠性及極佳的電性特性。
第二閘極絕緣層GI2可在第二PMOSFET區PR2與第二NMOSFET區NR2二者上包含相同的偶極元素。然而，本發明概念不限於此。為設定邏輯單元區LGC的電晶體的較低的臨限電壓，對於NMOSFET可能需要較低的功函數，或者對於PMOSFET可能需要較高的功函數。在本發明概念的示例性實施例中，第二閘極絕緣層GI2可在第二PMOSFET區PR2上包含鋁(Al)且可在第二NMOSFET區NR2上包含鑭(La)，以為邏輯單元區LGC的電晶體獲得較低的臨限電壓。在本發明概念的示例性實施例中，第二 閘極絕緣層GI2可在第二PMOSFET區PR2上包含鑭(La)且可在第二NMOSFET區NR2上包含鋁(Al)，以為邏輯單元區LGC的電晶體獲得較高的臨限電壓。
在本發明概念的示例性實施例中，第一閘極絕緣層GI1中的偶極元素的最大濃度(即，CN2)可大於第二閘極絕緣層GI2中的偶極元素的最大濃度。第一閘極絕緣層GI1中的偶極元素可與第二閘極絕緣層GI2中的偶極元素相同或不同。
如上所述，週邊區PER的電晶體的操作功率可高於邏輯單元區LGC的電晶體的操作功率。週邊區PER的電晶體可控制例如邏輯單元區LGC的電晶體的功能。第一閘極絕緣層GI1可較第二閘極絕緣層GI2厚。此可能是因為相較於第二閘極絕緣層GI2，第一閘極絕緣層GI1更包括第一絕緣層EG。詳言之，如圖2A中所示，第一閘極絕緣層GI1可在第一半導體圖案SP1的頂表面上具有第一厚度T1。參照圖2E，在第一半導體圖案SP1的頂表面上，第二閘極絕緣層GI2可具有較第一厚度T1小的第二厚度T2。另外，再次參照圖1，第一閘極電極GE1在第二方向D2上的第一寬度W1可大於第二閘極電極GE2在第二方向D2上的第二寬度W2。
圖4、圖6、圖8、圖10、圖12及圖14是示出根據本發明概念的示例性實施例的製造半導體裝置的方法的平面圖。圖5A、圖7A、圖9A、圖11A、圖13A及圖15A分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線A-A’截取的剖視圖。 圖5B、圖7B、圖9B、圖11B、圖13B及圖15B分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線B-B’截取的剖視圖。圖5C、圖7C、圖9C、圖11C、圖13C及圖15C分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線C-C’截取的剖視圖。圖5D、圖7D、圖9D、圖11D、圖13D及圖15D分別是沿著圖4、圖6、圖8、圖10、圖12及圖14所示的線D-D’截取的剖視圖。圖11E、圖13E及圖15E分別是沿著圖10、圖12及圖14所示的線E-E’截取的剖視圖。圖11F、圖13F及圖15F分別是沿著圖10、圖12及圖14所示的線F-F’截取的剖視圖。
參照圖4及圖5A至圖5D，可提供包括週邊區PER及邏輯單元區LGC的基板100。可在基板100上交替地形成第一半導體層與第二半導體層。第一半導體層可包含矽(Si)、鍺(Ge)及矽鍺(SiGe)中的一者，且第二半導體層可包含矽(Si)、鍺(Ge)及矽鍺(SiGe)中與第一半導體層中所包含的所述一者不同的另一者。舉例而言，第一半導體層可包含矽(Si)，且第二半導體層可包含矽鍺(SiGe)。
可對基板100執行第一圖案化製程，以形成界定第一主動圖案AP1至第四主動圖案AP4的第一溝槽TR1及第三溝槽TR3。第一圖案化製程可包括微影製程(photolithography process)及蝕刻製程(etch process)。在第一圖案化製程中，可將第一半導體層及第二半導體層圖案化以形成第一半導體圖案SP1及第二半導體圖案SP2。第一半導體圖案SP1與第二半導體圖案SP2可交替堆 疊於第一主動圖案AP1至第四主動圖案AP4中的每一者上。
可對基板100執行第二圖案化製程以形成第二溝槽TR2及第四溝槽TR4，第二溝槽TR2及第四溝槽TR4界定第一PMOSFET區PR1、第一NMOSFET區NR1、第二PMOSFET區PR2及第二NMOSFET區NR2。第二圖案化製程可包括微影製程及蝕刻製程。第二溝槽TR2及第四溝槽TR4可較第一溝槽TR1及第三溝槽TR3深。第二溝槽TR2可形成於第一PMOSFET區PR1與第一NMOSFET區NR1之間，且可將第一PMOSFET區PR1與第一NMOSFET區NR1分隔開。第四溝槽TR4可形成於第二PMOSFET區PR2與第二NMOSFET區NR2之間，且可將第二PMOSFET區PR2與第二NMOSFET區NR2分隔開。
第一PMOSFET區PR1及第一NMOSFET區NR1可設置於週邊區PER中。第一主動圖案AP1及第二主動圖案AP2可分別形成於第一PMOSFET區PR1及第一NMOSFET區NR1上。第二PMOSFET區PR2及第二NMOSFET區NR2可設置於邏輯單元區LGC中。第三主動圖案AP3及第四主動圖案AP4可分別形成於第二PMOSFET區PR2及第二NMOSFET區NR2上。
可在基板100上形成裝置隔離層ST以填充第一溝槽TR1至第四溝槽TR4，且可包含例如氧化矽(SiO2)層等絕緣材料。可使裝置隔離層ST凹陷，直至暴露出第一主動圖案AP1至第四主動圖案AP4的上部部分為止。因此，第一主動圖案AP1至第四主動圖案AP4的上部部分可自裝置隔離層ST垂直向上突出。
參照圖6及圖7A至圖7D，可在邏輯單元區LGC上形成遮罩層MA。遮罩層MA可覆蓋邏輯單元區LGC，但可暴露出週邊區PER。
可在週邊區PER的第一主動圖案AP1及第二主動圖案AP2上形成第一絕緣層EG，且可不在邏輯單元區上形成第一絕緣層EG。第一絕緣層EG可包括例如氧化矽(SiO2)層或氮氧化矽(SiON)層。舉例而言，可使用氧化製程(oxidation process)形成第一絕緣層EG。
可在週邊區PER的第一絕緣層EG上形成第一金屬氧化物層DPL1。第一金屬氧化物層DPL1可包含例如作為偶極元素的鑭(La)或鋁(Al)。舉例而言，第一金屬氧化物層DPL1可包括氧化鑭(La2O3)層或氧化鋁(Al2O3)層。
由於遮罩層MA，第一絕緣層EG及第一金屬氧化物層DPL1可能不會形成於邏輯單元區LGC的第三主動圖案AP3及第四主動圖案AP4上。
在形成第一金屬氧化物層DPL1之後，可對週邊區PER執行退火製程，以將第一金屬氧化物層DPL1的偶極元素擴散至第一絕緣層EG中。換言之，可將自第一金屬氧化物層DPL1擴散的偶極元素作為雜質注入至第一絕緣層EG中。舉例而言，由於第一金屬氧化物層DPL1可包含例如鑭(La)或鋁(Al)作為偶極元素，因此在退火製程之後，週邊區PER的第一絕緣層EG可包含鑭(La)或鋁(Al)作為雜質。此後，可選擇性地移除第一金屬氧 化物層DPL1。
參照圖8及圖9A至圖9D，可移除遮罩層MA。可在週邊區PER上形成與第一主動圖案AP1及第二主動圖案AP2相交的第一犧牲圖案PP1。可在邏輯單元區LGC上形成與第三主動圖案AP3及第四主動圖案AP4相交的第二犧牲圖案PP2。第一犧牲圖案PP1及第二犧牲圖案PP2中的每一者可具有在第一方向D1上延伸的線形狀或棒形狀。第二犧牲圖案PP2可在第一方向D1上彼此平行地延伸，且可在第二方向D2上排列且彼此間隔開。第一犧牲圖案PP1的寬度可大於第二犧牲圖案PP2的寬度。
所述形成第一犧牲圖案PP1及第二犧牲圖案PP2可包括在基板100的整個頂表面上形成犧牲層、在犧牲層上形成硬遮罩圖案MP、以及使用硬遮罩圖案MP作為蝕刻遮罩來將犧牲層圖案化。犧牲層可包含多晶矽(p-Si)。
再次參照圖9A，在週邊區PER上，第一絕緣層EG的被第一犧牲圖案PP1覆蓋的一部分可保留下來，但可移除第一絕緣層EG的未被第一犧牲圖案PP1覆蓋的另一部分。舉例而言，在將犧牲層圖案化以形成第一犧牲圖案PP1的製程期間，可移除第一絕緣層EG的未被第一犧牲圖案PP1覆蓋的所述另一部分。
可分別在第一犧牲圖案PP1及第二犧牲圖案PP2中的每一者的兩個側壁上形成成對的閘極間隔件GS。所述形成閘極間隔件GS可包括在基板100的整個頂表面上共形地形成閘極間隔件層以及各向異性地蝕刻閘極間隔件層。為形成閘極間隔件層，可 使用例如(舉例而言)原子層沈積(atomic layer deposition，ALD)製程、化學氣相沈積(chemical vapor deposition，CVD)製程或其組合等製程。舉例而言，閘極間隔件層可包含例如碳氮化矽(SiCN)、氮氧化矽碳(SiCON)或氮化矽(Si3N4)中的至少一者。在本發明概念的示例性實施例中，閘極間隔件可由包含碳氮化矽(SiCN)、氮氧化矽碳(SiCON)或氮化矽(Si3N4)中的至少兩者的多層形成。
參照圖10及圖11A至圖11F，可分別在第一主動圖案AP1至第四主動圖案AP4的上部部分中形成第一源極/汲極圖案SD1至第四源極/汲極圖案SD4。
可在第一主動圖案AP1的上部部分中形成第一源極/汲極圖案SD1。可分別在第一犧牲圖案PP1的兩側處形成成對的第一源極/汲極圖案SD1。詳言之，可使用硬遮罩圖案MP及閘極間隔件GS作為蝕刻遮罩來蝕刻第一主動圖案AP1的上部部分，以形成第一凹陷區RS1。在蝕刻第一主動圖案AP1的上部部分時，可使第一主動圖案AP1的兩側處的裝置隔離層ST凹陷(參見圖11C)。
可藉由使用第一主動圖案AP1的第一凹陷區RS1的內表面作為晶種層執行選擇性磊晶生長(SEG)製程來形成第一源極/汲極圖案SD1。舉例而言，SEG製程可包括化學氣相沈積(CVD)製程或分子束磊晶(molecular beam epitaxy，MBE)製程。第一源極/汲極圖案SD1可包含晶格常數大於基板100的半導體元素(例 如，Si)的晶格常數的半導體元素(例如，SiGe)。在本發明概念的示例性實施例中，第一源極/汲極圖案SD1中的每一者可由多個堆疊的半導體層形成。
在本發明概念的示例性實施例中，在用於形成第一源極/汲極圖案SD1的SEG製程期間，可將摻雜劑原位注入至第一源極/汲極圖案SD1中。在本發明概念的示例性實施例中，在用於形成第一源極/汲極圖案SD1的SEG製程之後，可將摻雜劑注入或植入至第一源極/汲極圖案SD1中。舉例而言，在SEG製程之後，可使用離子植入製程將摻雜劑注入至第一源極/汲極圖案SD1中。可利用第一導電類型(例如，P型)的摻雜劑來摻雜第一源極/汲極圖案SD1。在本發明概念的示例性實施例中，第一源極/汲極圖案SD1中的每一者可包括摻雜有例如(舉例而言)硼(B)、鋁(Al)、鎵(Ga)或銦(In)等P型摻雜劑的矽鍺(SiGe)層。
可在第二主動圖案AP2的上部部分中形成第二源極/汲極圖案SD2。可分別在第一犧牲圖案PP1的兩側處形成成對的第二源極/汲極圖案SD2。
可使用硬遮罩圖案MP及閘極間隔件GS作為蝕刻遮罩來蝕刻第二主動圖案AP2的上部部分，以形成第二凹陷區RS2。可藉由使用第二主動圖案AP2的第二凹陷區RS2的內表面作為晶種層執行SEG製程來形成第二源極/汲極圖案SD2。舉例而言，第二源極/汲極圖案SD2可包含與基板100的半導體元素相同的半導體元素(例如，矽)。可利用第二導電類型(例如，N型)的摻雜 劑來摻雜第二源極/汲極圖案SD2。在本發明概念的示例性實施例中，第二源極/汲極圖案SD2中的每一者可包括摻雜有例如(舉例而言)磷(P)、砷(As)、銻(Sb)或鉍(Bi)等N型摻雜劑的矽(Si)層。
在第三主動圖案AP3的上部部分中形成第三源極/汲極圖案SD3的方法可與前述形成第一源極/汲極圖案SD1的方法實質上相同。可同時形成第一源極/汲極圖案SD1與第三源極/汲極圖案SD3。在第四主動圖案AP4的上部部分中形成第四源極/汲極圖案SD4的方法可與前述形成第二源極/汲極圖案SD2的方法實質上相同。可同時形成第二源極/汲極圖案SD2與第四源極/汲極圖案SD4。
參照圖12及圖13A至圖13F，可形成第一層間絕緣層110以覆蓋第一源極/汲極圖案SD1至第四源極/汲極圖案SD4、硬遮罩圖案MP及閘極間隔件GS。舉例而言，第一層間絕緣層110可包括氧化矽(SiO2)層。
可對第一層間絕緣層110進行平坦化，直至暴露出第一犧牲圖案PP1及第二犧牲圖案PP2的頂表面為止。可使用回蝕製程(etch-back process)或化學機械研磨(chemical mechanical polishing，CMP)製程來執行第一層間絕緣層110的平坦化製程(planarization process)。在平坦化製程期間，可完全移除硬遮罩圖案MP。因此，第一層間絕緣層110的頂表面可與第一犧牲圖案PP1及第二犧牲圖案PP2的頂表面以及閘極間隔件GS的頂表面 實質上共面。
可選擇性地移除第一犧牲圖案PP1及第二犧牲圖案PP2。可藉由移除第一犧牲圖案PP1來形成暴露出第一主動圖案AP1及第二主動圖案AP2的第一空的空間ET1(參見圖13C)。可藉由移除第二犧牲圖案PP2來形成暴露出第三主動圖案AP3及第四主動圖案AP4的第二空的空間ET2(參見圖13F)。
可選擇性地移除邏輯單元區LGC上的第二半導體圖案SP2，同時可不移除週邊區PER上的第二半導體圖案SP2。舉例而言，在移除邏輯單元區LGC上的第二半導體圖案SP2的製程期間，週邊區PER上的第二半導體圖案SP2可被覆蓋且不暴露於蝕刻劑。詳言之，再次參照圖13F，第二半導體圖案SP2可由第二空的空間ET2暴露出，且可藉由執行用於選擇性地移除第二半導體圖案SP2的蝕刻製程來移除第二半導體圖案SP2。可不移除、而是可保留第一半導體圖案SP1。可藉由移除第二半導體圖案SP2來形成第三空的空間ET3。舉例而言，為形成第三空的空間ET3，可藉由使用第二半導體圖案SP2與第一半導體圖案SP1之間的蝕刻選擇性差異來選擇性地蝕刻第二半導體圖案SP2。在本發明概念的示例性實施例中，可藉由濕法蝕刻製程(wet etching process)來形成第三空的空間ET3。可在彼此垂直相鄰的第一半導體圖案SP1之間界定第三空的空間ET3中的每一者。
再次參照圖13E，可在第二NMOSFET區NR2上的第三空的空間ET3中形成絕緣圖案IP，且絕緣圖案IP可部分地填充第 三空的空間ET3。絕緣圖案IP可與第四源極/汲極圖案SD4接觸。
參照圖14及圖15A至圖15F，可分別在第一空的空間ET1及第二空的空間ET2中形成第一閘極絕緣層GI1及第二閘極絕緣層GI2。詳言之，可在第一空的空間ET1及第二空的空間ET2中形成第二絕緣層IL。形成於週邊區PER上的第二絕緣層IL可覆蓋第一絕緣層EG。形成於邏輯單元區LGC上的第二絕緣層IL可環繞第一半導體圖案SP1中的每一者。亦可在第三空的空間ET3中形成於邏輯單元區LGC上形成的第二絕緣層IL。
此後，可在週邊區PER及邏輯單元區LGC上共形地形成高介電常數介電層HK，且可覆蓋第二絕緣層IL。亦可在第三空的空間ET3中形成邏輯單元區LGC上的高介電常數介電層HK。
週邊區PER上的第一絕緣層EG、第二絕緣層IL及高介電常數介電層HK可構成第一閘極絕緣層GI1。可將擴散於第一絕緣層EG中的偶極元素擴散至第二絕緣層IL中，且因此第一閘極絕緣層GI1可具有圖3所示的偶極元素的濃度分佈曲線。舉例而言，如圖3中所示，第二絕緣層IL中的第二濃度CN2可為第一閘極絕緣層GI1中的偶極元素的濃度的最大值。
邏輯單元區LGC上的第二絕緣層IL及高介電常數介電層HK可構成第二閘極絕緣層GI2。第二閘極絕緣層GI2可較第一閘極絕緣層GI1薄。此可能是因為相較於第二閘極絕緣層GI2，第一閘極絕緣層GI1更包括第一絕緣層EG。
可分別在第一空的空間ET1及第二空的空間ET2中形 成第一閘極電極GE1及第二閘極電極GE2。可在第一閘極電極GE1及第二閘極電極GE2中的每一者上形成閘極頂蓋圖案GP。邏輯單元區LGC上的第二閘極電極GE2可完全填充第三空的空間ET3。
再次參照圖1及圖2A至圖2H，可在第一層間絕緣層110上形成第二層間絕緣層120。第二層間絕緣層120可包括氧化矽(SiO2)層。可在第二層間絕緣層120及第一層間絕緣層110中形成主動接觸件AC，且主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110，以便電性連接至第一源極/汲極圖案SD1至第四源極/汲極圖案SD4。可將閘極接觸件GC形成為穿透第二層間絕緣層120及閘極頂蓋圖案GP，且可將閘極接觸件GC電性連接至第一閘極電極GE1及第二閘極電極GE2。
可在主動接觸件AC及閘極接觸件GC上形成第三層間絕緣層130。可在第三層間絕緣層130中形成第一金屬層，且第一金屬層可包括第一互連線M1、第一通孔V1及第二通孔V2。第一通孔V1可將主動接觸件AC電性連接至第一互連線M1中對應的一者。第二通孔V2可將閘極接觸件GC電性連接至第一互連線M1中對應的一者。
可能需要在高溫下執行退火製程，以將金屬氧化物層中所包含的偶極元素擴散至位於金屬氧化物層下方的閘極絕緣層中。源極/汲極圖案及通道圖案可能由於退火製程而劣化。此可能降低半導體裝置的效能。然而，根據本發明概念的示例性實施例，偶極 元素可在形成第一源極/汲極圖案SD1至第四源極/汲極圖案SD4之前自第一金屬氧化物層DPL1擴散至第一絕緣層EG中，如以上參照圖6及圖7A至圖7D所述。因此，可防止半導體裝置由於退火製程而劣化。
圖16A及圖16B分別是沿著圖12所示的線C-C’及F-F’截取以示出根據本發明概念的示例性實施例的製造半導體裝置的方法的剖視圖。在本示例性實施例中，出於闡釋容易及方便的目的，將省略對與圖4至圖15F所示示例性實施例中相同的技術特徵的說明。換言之，在下文中，將主要闡述本示例性實施例與圖4至圖15F所示示例性實施例之間的差異。
參照圖16A及圖16B，可在圖12及圖13A至圖13F所示所得結構上形成第一閘極絕緣層GI1及第二閘極絕緣層GI2。可在第一閘極絕緣層GI1及第二閘極絕緣層GI2中的每一者的高介電常數介電層HK上形成第二金屬氧化物層DPL2。第二金屬氧化物層DPL2可包含例如作為偶極元素的鑭(La)或鋁(Al)。舉例而言，第二金屬氧化物層DPL2可包括氧化鑭(La2O3)層或氧化鋁(Al2O3)層。
在形成第二金屬氧化物層DPL2之後，可執行退火製程以將第二金屬氧化物層DPL2中所包含的偶極元素擴散至第一閘極絕緣層GI1及第二閘極絕緣層GI2中。換言之，可將自第二金屬氧化物層DPL2擴散的偶極元素作為雜質注入至第一閘極絕緣層GI1及第二閘極絕緣層GI2中。舉例而言，由於第二金屬氧化 物層DPL2可包含例如鑭(La)或鋁(Al)作為偶極元素，因此在退火製程之後，第一閘極絕緣層GI1及第二閘極絕緣層GI2可包含鑭(La)或鋁(Al)作為雜質。
根據本示例性實施例，可使用第二金屬氧化物層DPL2將偶極元素注入至第一閘極絕緣層GI1及第二閘極絕緣層GI2中。因此，可調節週邊區PER的電晶體的臨限電壓及邏輯單元區LGC的電晶體的臨限電壓。因此，根據本示例性實施例的半導體裝置可具有高可靠性及極佳的電性特性。
藉由透過圖6及圖7A至圖7D所示的第一金屬氧化物層DPL1注入偶極元素以及透過圖16A及圖16B所示的第二金屬氧化物層DPL2注入偶極元素，週邊區PER上的第一閘極絕緣層GI1中的偶極元素的濃度可相對高。因此，第一閘極絕緣層GI1中的偶極元素的濃度可高於第二閘極絕緣層GI2中的偶極元素的濃度。
第一閘極絕緣層GI1與第二閘極絕緣層GI2可包含彼此不同的偶極元素。舉例而言，第一閘極絕緣層GI1可包含鑭(La)及鋁(Al)。另一方面，第二閘極絕緣層GI2可包含單一偶極元素(即，鑭(La)或鋁(Al))。此可能是由於第一閘極絕緣層GI1分別自第一金屬氧化物層DPL1與第二金屬氧化物層DPL2接收不同的偶極元素。然而，本發明概念不限於此。舉例而言，在本發明概念的示例性實施例中，第一閘極絕緣層GI1及第二閘極絕緣層GI2可各自包含單一偶極元素(即，鑭(La)或鋁(Al))，第一閘 極絕緣層GI1中所包含的單一偶極元素的濃度高於第二閘極絕緣層GI2中所包含的單一偶極元素的濃度。
如上所述，根據本示例性實施例，可使用第一閘極絕緣層GI1中的偶極元素的濃度及組合來調節週邊區PER上的電晶體的臨限電壓。因此，根據本示例性實施例的半導體裝置可具有高可靠性及極佳的電性特性。
圖17A、圖17B及圖17C分別是沿著圖1所示的線A-A’、B-B’及C-C’截取以示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。在本示例性實施例中，出於闡釋容易及方便的目的，將省略對與圖1及圖2A至圖2H所示示例性實施例中的技術特徵相同的技術特徵的說明。換言之，在下文中，將主要闡述本示例性實施例與圖1及圖2A至圖2H所示示例性實施例之間的差異。
參照圖1及圖17A至圖17C，與圖1及圖2A至圖2C所示的第一主動圖案AP1及第二主動圖案AP2不同，第一主動圖案AP1及第二主動圖案AP2可不包括交替堆疊的第一半導體圖案SP1與第二半導體圖案SP2。換言之，第一主動圖案AP1及第二主動圖案AP2的上部部分中的每一者可具有自裝置隔離層ST向上突出的單一鰭形狀。即，根據本示例性實施例的週邊區PER的電晶體可為鰭式場效電晶體(fin field-effect transistor，FinFET)。
儘管週邊區PER的電晶體可為不具有第一半導體圖案SP1及第二半導體圖案SP2的FinFET，然而邏輯單元區LGC上的 電晶體可為其中第二閘極電極GE2三維地環繞第一半導體圖案SP1(即，通道)中的每一者的MBCFET，如以上參照圖1及圖2E至圖2H所述。根據本示例性實施例，FinFET的第一閘極絕緣層GI1及MBCFET的第二閘極絕緣層GI2可包含一或多種偶極元素作為雜質。因此，可調節週邊區PER的FinFET的臨限電壓及邏輯單元區LGC的MBCFET的臨限電壓。
根據本發明概念的示例性實施例，偶極元素可穩定地注入至閘極絕緣層中，而不會由於退火製程而使裝置劣化。電晶體的臨限電壓可使用偶極元素來調節。因此，根據本發明概念的示例性實施例的半導體裝置可具有高可靠性及極佳的電性特性。
儘管已參照較佳的示例性實施例闡述本發明概念，然而對於熟習此項技術者而言將顯而易見，在不背離本發明概念的精神及範圍的條件下，可作出各種改變及修改。因此，應理解，以上示例性實施例不是限制性的，而是例示性的。因此，本發明概念的範圍要藉由以下申請專利範圍及其等效範圍的最廣泛可允許解釋來確定，且不應由前述說明來約束或限制。
100:基板
A-A’、B-B’、C-C’、D-D’、E-E’、F-F’、G-G’、H-H’:線
AC:主動接觸件
AP1:第一主動圖案
AP2:第二主動圖案
AP3:第三主動圖案
AP4:第四主動圖案
D1:第一方向
D2:第二方向
D3:第三方向
GC:閘極接觸件
GE1:第一閘極電極
GE2:第二閘極電極
LGC:邏輯單元區
NR1:第一N型MOSFET(NMOSFET)區
NR2:第二NMOSFET區
PER:週邊區
PR1:第一犧牲圖案
PR2:第二犧牲圖案
SD1:源極/汲極圖案/第一源極/汲極圖案
SD2:源極/汲極圖案/第二源極/汲極圖案
SD3:第三源極/汲極圖案
SD4:第四源極/汲極圖案
W1:第一寬度
W2:第二寬度

Claims (20)

  1. 一種半導體裝置，包括：基板，包括週邊區；第一主動圖案，設置於所述基板的所述週邊區上，所述第一主動圖案所具有的上部部分包括交替堆疊的第一半導體圖案與第二半導體圖案；第一閘極電極，與所述第一主動圖案相交；成對的第一源極/汲極圖案，分別設置於所述第一閘極電極的兩側處；以及第一閘極絕緣層，設置於所述第一閘極電極與所述第一主動圖案之間，其中所述第一閘極絕緣層包括：第一絕緣層，形成於所述第一主動圖案上；第二絕緣層，形成於所述第一絕緣層上；以及高介電常數介電層，形成於所述第二絕緣層上，其中所述第一閘極絕緣層包含第一偶極元素，所述第一偶極元素包括鑭(La)、鋁(Al)或其組合，且其中所述第一閘極絕緣層中的所述第一偶極元素的濃度自所述第一閘極電極與所述高介電常數介電層之間的介面向所述第二絕緣層增加，達到最大值，且然後向所述第一絕緣層與所述第一半導體圖案中相鄰的一者之間的介面降低。
  2. 如請求項1所述的半導體裝置，更包括： 第二主動圖案，設置於所述基板的邏輯單元區上，其中所述第二主動圖案的上部部分包括堆疊且彼此間隔開的第三半導體圖案；第二閘極電極，與所述第二主動圖案相交；成對的第二源極/汲極圖案，分別設置於所述第二閘極電極的兩側處；以及第二閘極絕緣層，設置於所述第二閘極電極與所述第二主動圖案之間，其中所述第一半導體圖案與所述第三半導體圖案包含相同的半導體材料，且其中所述第一閘極絕緣層的厚度大於所述第二閘極絕緣層的厚度。
  3. 如請求項2所述的半導體裝置，其中所述第二閘極電極及所述第二閘極絕緣層填充彼此垂直相鄰的所述第三半導體圖案之間的空間。
  4. 如請求項2所述的半導體裝置，其中所述第一閘極電極的寬度大於所述第二閘極電極的寬度。
  5. 如請求項2所述的半導體裝置，其中所述第二閘極絕緣層包含第二偶極元素，所述第二偶極元素包括鑭(La)或鋁(Al)，且所述第一閘極絕緣層中的所述第一偶極元素的最大濃度大於所述第二閘極絕緣層中的所述第二偶極元素的最大濃度。
  6. 如請求項1所述的半導體裝置，其中所述第一偶極元素在所述第一閘極電極與所述高介電常數介電層之間的所述介面處的濃度小於所述第一偶極元素在所述第一絕緣層與所述第一半導體圖案中相鄰的所述一者之間的所述介面處的濃度。
  7. 如請求項1所述的半導體裝置，其中所述第一偶極元素包括鑭(La)與鋁(Al)的組合。
  8. 如請求項1所述的半導體裝置，其中所述第一半導體圖案及所述第二半導體圖案構成連接所述成對的第一源極/汲極圖案的通道圖案。
  9. 如請求項1所述的半導體裝置，更包括：第一層間絕緣層，設置於所述第一閘極電極上；主動接觸件，穿透所述第一層間絕緣層且電性連接至所述成對的第一源極/汲極圖案中的至少一者；第二層間絕緣層，設置於所述第一層間絕緣層上；以及第一金屬層，設置於所述第二層間絕緣層中且電性連接至所述主動接觸件。
  10. 一種半導體裝置，包括：基板，包括第一區及第二區；第一主動圖案及第二主動圖案，分別設置於所述基板的所述第一區及所述第二區上；第一閘極電極及第二閘極電極，分別與所述第一主動圖案及所述第二主動圖案相交； 第一閘極絕緣層，設置於所述第一閘極電極與所述第一主動圖案之間；以及第二閘極絕緣層，設置於所述第二閘極電極與所述第二主動圖案之間，其中所述第一閘極絕緣層包含第一偶極元素，所述第一偶極元素包括鑭(La)、鋁(Al)或其組合，其中所述第二閘極絕緣層包含第二偶極元素，所述第二偶極元素包括鑭(La)或鋁(Al)，其中所述第一閘極絕緣層的厚度大於所述第二閘極絕緣層的厚度，且其中所述第一閘極絕緣層中的所述第一偶極元素的最大濃度大於所述第二閘極絕緣層中的所述第二偶極元素的最大濃度。
  11. 如請求項10所述的半導體裝置，其中所述第一閘極電極的寬度大於所述第二閘極電極的寬度。
  12. 如請求項10所述的半導體裝置，其中所述第一主動圖案的上部部分包括交替堆疊的第一半導體圖案與第二半導體圖案，所述第二主動圖案的上部部分包括堆疊且彼此間隔開的第三半導體圖案，且所述第一半導體圖案與所述第三半導體圖案包含相同的半導體材料。
  13. 如請求項12所述的半導體裝置，其中所述第二閘極 電極及所述第二閘極絕緣層填充彼此垂直相鄰的所述第三半導體圖案之間的空間。
  14. 如請求項10所述的半導體裝置，其中所述第一區是週邊區，且所述第二區是邏輯單元區。
  15. 如請求項10所述的半導體裝置，其中所述第一閘極絕緣層包括：第一絕緣層，形成於所述第一主動圖案上；第二絕緣層，形成於所述第一絕緣層上；以及高介電常數介電層，形成於所述第二絕緣層上，其中所述第一閘極絕緣層中的所述第一偶極元素的濃度自所述第一閘極電極與所述高介電常數介電層之間的介面向所述第二絕緣層增加，達到最大值，且然後向所述第一絕緣層與所述第一主動圖案之間的介面降低。
  16. 如請求項15所述的半導體裝置，其中所述第一偶極元素在所述第一閘極電極與所述高介電常數介電層之間的所述介面處的濃度小於所述第一偶極元素在所述第一絕緣層與所述第一主動圖案之間的所述介面處的濃度。
  17. 一種半導體裝置，包括：基板，包括週邊區；裝置隔離層，設置於所述基板的所述週邊區上以界定第一主動圖案； 成對的第一源極/汲極圖案，設置於所述第一主動圖案上；第一半導體圖案及第二半導體圖案，設置於所述成對的第一源極/汲極圖案之間，其中所述第一半導體圖案與所述第二半導體圖案交替堆疊於所述第一主動圖案上，且所述第二半導體圖案中最下部的一者的底表面高於所述裝置隔離層的頂表面；第一閘極電極，在所述第一主動圖案上與所述第一半導體圖案及所述第二半導體圖案相交；第一閘極絕緣層，設置於所述第一閘極電極與所述第一半導體圖案及所述第二半導體圖案之間；成對的閘極間隔件，分別設置於所述第一閘極電極的兩個側壁上；閘極頂蓋圖案，設置於所述第一閘極電極上；第一層間絕緣層，設置於所述閘極頂蓋圖案上；主動接觸件，穿透所述第一層間絕緣層且電性連接至所述成對的第一源極/汲極圖案中的至少一者；第二層間絕緣層，設置於所述第一層間絕緣層上；以及第一金屬層，設置於所述第二層間絕緣層中且電性連接至所述主動接觸件，其中所述第一閘極絕緣層包括：第一絕緣層，形成於所述第一半導體圖案及所述第二半導體圖案上；第二絕緣層，形成於所述第一絕緣層上；以及 高介電常數介電層，形成於所述第二絕緣層上，其中所述高介電常數介電層設置於所述第二絕緣層與所述第一閘極電極之間，其中所述第一閘極絕緣層包含偶極元素，且其中所述偶極元素在所述第一閘極電極與所述高介電常數介電層之間的介面處的濃度小於所述偶極元素在所述第一絕緣層與所述第一半導體圖案中相鄰的一者之間的介面處的濃度。
  18. 如請求項17所述的半導體裝置，其中所述偶極元素包括鑭(La)、鋁(Al)或其組合。
  19. 如請求項17所述的半導體裝置，其中所述第一閘極絕緣層中的所述偶極元素的濃度自所述第一閘極電極與所述高介電常數介電層之間的所述介面向所述第二絕緣層增加，達到最大值，且然後向所述第一絕緣層與所述第一半導體圖案中相鄰的所述一者之間的所述介面降低。
  20. 如請求項17所述的半導體裝置，其中所述基板更包括邏輯單元區，且所述裝置隔離層亦在所述邏輯單元區上界定第二主動圖案，所述半導體裝置更包括：成對的第二源極/汲極圖案，設置於所述第二主動圖案上；第三半導體圖案，設置於所述成對的第二源極/汲極圖案之間，所述第三半導體圖案堆疊於所述第二主動圖案上且彼此間隔開；第二閘極電極，與所述第三半導體圖案相交且環繞所述第三半導體圖案中的每一者；以及 第二閘極絕緣層，設置於所述第二閘極電極與所述第三半導體圖案之間，其中所述第一半導體圖案與所述第三半導體圖案包含相同的半導體材料，且其中所述第一閘極絕緣層的厚度大於所述第二閘極絕緣層的厚度。
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