TWI826443B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI826443B TWI826443B TW108114942A TW108114942A TWI826443B TW I826443 B TWI826443 B TW I826443B TW 108114942 A TW108114942 A TW 108114942A TW 108114942 A TW108114942 A TW 108114942A TW I826443 B TWI826443 B TW I826443B
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- Prior art keywords
- gate
- layer
- gate electrode
- electrode layer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 125000006850 spacer group Chemical group 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 484
- 238000000034 method Methods 0.000 description 38
- 239000011229 interlayer Substances 0.000 description 32
- 239000000463 material Substances 0.000 description 25
- 238000002955 isolation Methods 0.000 description 16
- 238000004891 communication Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 229910010041 TiAlC Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910017414 LaAl Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MIQVEZFSDIJTMW-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O-2].[Al+3].[Hf+4] MIQVEZFSDIJTMW-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910001392 phosphorus oxide Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract
一種半導體裝置包括:基板,具有主動區;閘極結構,
位於主動區上,閘極結構包括閘極介電層及閘極電極層,且閘極電極層具有圓形上隅角;以及閘極間隔件層,位於閘極結構的側表面上,閘極間隔件層具有位於較閘極電極層的上表面低的高度水平處的上表面。本揭露亦提供一種製造半導體裝置的方法。
Description
本揭露是有關於一種半導體裝置及其製造方法。
於2018年8月14日在韓國智慧財產局提出申請且名稱為:「半導體裝置及其製造方法(Semiconductor Device and Method of Manufacturing the Same)」的韓國專利申請案第10-2018-0094973號全文併入本案供參考。
隨著對半導體裝置的高效能、高速度、多功能化及/或類似方面的需求增加,半導體裝置的積體度亦增加。因此,在製造半導體裝置時,需要實施與半導體裝置的高積體度對應的具有精細寬度或精細間隔的圖案。此外,為克服由於平面金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)的大小減小而造成的其操作特性的限制,正在努力開發包括具有三維結構通道(three-dimensional structure channel)的鰭式場效電晶體(fin field effect transistor,FinFET)的半導體裝置。
根據本揭露的態樣,一種半導體裝置可包括:基板,具有主動區;閘極結構,安置於所述主動區上且包括閘極介電層及閘極電極層;以及閘極間隔件層,安置於所述閘極結構的兩個側表面上且具有位於較所述閘極電極層的上表面的水平高度低的水平高度上的上表面。所述閘極電極層具有上隅角為圓形的形狀。
根據本揭露的態樣,一種半導體裝置可包括:基板,具有主動區且具有第一區及第二區;第一閘極電極層,安置於所述第一區上以在第一方向上延伸且在與所述第一方向垂直的第二方向上具有第一長度;以及第二閘極電極層,安置於所述第二區上以在所述第一方向上延伸且在所述第二方向上具有較所述第一長度大的第二長度。所述第一閘極電極層及所述第二閘極電極層在設置於所述第二方向上的邊緣區中具有第一厚度,且在位於所述邊緣區內部的區中具有較所述第一厚度大的第二厚度。
根據本揭露的態樣,一種製造半導體裝置的方法可包括:在具有主動區的基板上形成閘極電極層及面對所述閘極電極層的側壁的閘極間隔件層;自上表面部分地移除所述閘極間隔件層,以暴露出所述閘極電極層的側表面的部分;自上表面及被所述閘極間隔件層暴露出的所述側表面部分地移除所述閘極電極層;以及形成覆蓋所述閘極間隔件層的上表面及所述閘極電極層的上表面的閘極頂蓋層。
100、100a、100b、100c:半導體裝置
101:基板
105:主動鰭
107:裝置隔離層
112:第一閘極介電層
114:第二閘極介電層/閘極介電層
114E:上端部
120、120a、120b、120c、120d:閘極電極層
120P:閘極電極層
122:第一層
124:第二層
123c、123d:第一導電層/導電層
125c、126d:第二導電層/導電層
130、130P:閘極間隔件層
130a:閘極間隔件層
140:閘極頂蓋層
150:源極/汲極區
160:接觸插塞
162:擴散障壁層
165:插塞導電層
180:犧牲閘極結構
182:犧牲閘極絕緣層
185:犧牲閘極電極層
192:第一層間絕緣層
194:第二層間絕緣層
1000:電子裝置
1010:通訊單元
1020:輸入單元
1030:輸出單元
1040、2300:記憶體
1050:處理器
2000:系統
2100:控制器
2200:輸入/輸出裝置
2400:介面
2500:匯流排
A:區
CL:塗層
D1:預定長度/長度
D2:預定長度/延伸長度
D3:預定深度/深度
GR:凹陷區
GS1、GS1b、GS1c:第一閘極結構
GS2、GS2a、GS2b、GS2c:第二閘極結構
GS3:第三閘極結構
H1:第一最大高度/第一高度/最大高度
H2:第二最大高度
H3:第三高度
H4:第四高度
H5:最大高度
I-I、II-II'、III-III'、IV-IV':線
L1:第一長度
L2:第二長度
L3:分隔距離
OP:開口
PH:接觸孔
R1:第一區
R2:第二區
R3:第三區
S110、S120、S130、S140、S150、S160、S170、180:操作
ST:隧道部分
T1:第一厚度
T2:第二厚度
TC:上圓形隅角/頂隅角/上隅角/圓形上隅角/圓形隅角
TR1:第一電晶體/電晶體
TR2:第二電晶體/電晶體
TR3:第三電晶體/電晶體
X、Y、Z:方向
藉由參照附圖詳細闡述示範性實施例,對於熟習此項技
術者而言,特徵將變得顯而易見,在附圖中:圖1示出根據示例性實施例的半導體裝置的平面圖。
圖2A及圖2B示出根據示例性實施例的半導體裝置的剖視圖。
圖3示出根據示例性實施例的半導體裝置的一部分的局部分解立體圖。
圖4A及圖4B示出根據示例性實施例的半導體裝置的一部分的局部放大圖。
圖5及圖6示出根據示例性實施例的半導體裝置的剖視圖。
圖7示出根據示例性實施例的半導體裝置的剖視圖。
圖8示出根據示例性實施例的製造半導體裝置的方法的流程圖。
圖9A至圖9J示出根據示例性實施例的製造半導體裝置的方法中的階段的剖視圖。
圖10示出根據示例性實施例的包括半導體裝置的電子設備的方塊圖。
圖11示出根據示例性實施例的包括半導體裝置的系統的示意圖。
在下文中,將參照附圖闡述示例性實施例。
圖1是根據示例性實施例的半導體裝置的平面圖。為便
於闡釋,圖1中僅示出半導體裝置的主要組件。
圖2A及圖2B是示出根據示例性實施例的半導體裝置的剖視圖。圖2A示出沿圖1中的線I-I'及II-II'的剖視圖,且圖2B示出沿圖1中的線III-III'及IV-IV'的剖視圖。
參照圖1至圖2B,半導體裝置100可包括具有第一區R1及第二區R2的基板101、主動鰭105、第一閘極介電層112及第二閘極介電層114、閘極電極層120、閘極間隔件層130、閘極頂蓋層140、源極/汲極區150以及接觸插塞160。半導體裝置100可更包括裝置隔離層107以及第一層間絕緣層192及第二層間絕緣層194。
半導體裝置100可包括FinFET裝置,即主動鰭105具有鰭結構的電晶體。FinFET裝置可包括:第一電晶體TR1及第二電晶體TR2,基於主動鰭105定位;以及彼此相交的第一閘極結構GS1及第二閘極結構GS2。第一電晶體TR1及第二電晶體TR2可為n型或p型MOS場效電晶體(MOSFET)。第一電晶體TR1與第二電晶體TR2可具有不同的臨限電壓從而具有不同的工作電壓。舉例而言,當第一電晶體TR1與第二電晶體TR2是相同導電類型的電晶體時,第一電晶體TR1可具有較第二電晶體TR2的臨限電壓及工作電壓低的臨限電壓及低的工作電壓。根據示例性實施例,臨限電壓及工作電壓的量值(magnitude)可使用臨限電壓及工作電壓的絕對值來比較。第一電晶體TR1及第二電晶體TR2可構成半導體裝置100中的相同的電路或不同的電路。
基板101可具有不同的第一區R1及第二區R2,且第一區R1及第二區R2可為分別安置有第一電晶體TR1及第二電晶體TR2的區。第一區R1及第二區R2可被安置成在半導體裝置100中彼此間隔開或彼此相鄰。
基板101可具有在X方向及Y方向上延伸的上表面。基板101可包含半導體材料,例如IV族半導體、III-V族化合物半導體或II-VI族化合物半導體。舉例而言,IV族半導體可包括矽、鍺或矽-鍺。基板101可被設置成塊狀晶圓、磊晶層、絕緣體上矽(silicon-on-insulator,SOI)層、絕緣體上半導體(semiconductor-on-insulator,SeOI)層等。
裝置隔離層107可在基板101中界定主動鰭105,如圖2B中所示。裝置隔離層107可例如藉由淺溝槽隔離(shallow trench isolation,STI)製程形成。根據示例性實施例,裝置隔離層107可包括在相鄰的主動鰭105之間延伸至基板101的下部分中的區,以在所述區中相對更深。根據示例性實施例,裝置隔離層107亦可具有彎曲的上表面,所述彎曲的上表面在高度方向上具有朝主動鰭105增加的水平高度,且裝置隔離層107的上表面及下表面的形式並不限於圖的例示。裝置隔離層107可由絕緣材料形成。裝置隔離層107可由例如氧化物、氮化物或其組合形成。
主動鰭105在基板101中可由裝置隔離層107界定,且可被安置成在一個方向(例如,X方向)上延伸。主動鰭105可具有線形狀或桿形狀,例如,具有在X方向上延伸的縱向方向,
且自基板101突出以在裝置隔離層107之間延伸。儘管圖1示出在第一區R1及第二區R2中的每一者中三個主動鰭105在Y方向上彼此間隔開,然而主動鰭105的排列及數目並不限於此。此外,在示例性實施例中,對構成第一電晶體TR1及第二電晶體TR2中的每一者的主動鰭105的數目可進行各種改變。
主動鰭105可由基板101的部分形成,或者可包括自基板101生長的磊晶層。主動鰭105可部分地凹陷入第一閘極結構GS1及第二閘極結構GS2以及閘極間隔件層130的兩側中,且源極/汲極區150可形成於凹陷的主動鰭105上。因此,如圖2A中所示,第一閘極結構GS1及第二閘極結構GS2下方的主動鰭105可具有相對高的高度。在示例性實施例中,主動鰭105可包含雜質。
第一閘極結構GS1及第二閘極結構GS2可被安置成在主動鰭105上在例如Y方向的方向上延伸同時與主動鰭105相交。第一閘極結構GS1及第二閘極結構GS2可各自包括第一閘極介電層112及第二閘極介電層114以及閘極電極層120。第一閘極結構GS1與第二閘極結構GS2可具有相同的結構或者可具有不同的結構。舉例而言,在第一閘極結構GS1及第二閘極結構GS2中,第一閘極介電層112與第二閘極介電層114可具有不同的組成物及/或厚度,且閘極電極層120的配置可彼此不同。
第一閘極介電層112及第二閘極介電層114可安置於主動鰭105與閘極電極層120之間。舉例而言,如圖2A中所示,第
一閘極介電層112可安置於閘極電極層120的下表面上,且第二閘極介電層114可被安置成覆蓋閘極電極層120的下表面及側表面,例如第一閘極介電層112可僅位於第二閘極介電層114的下表面與主動鰭105之間。在另一實例中,第二閘極介電層114亦可僅安置於閘極電極層120的下表面上。
第二閘極介電層114可具有在閘極電極層120的側表面上的上端部,所述上端部位於與閘極電極層120的上表面的水平高度相同的水平高度上或位於較閘極電極層120的上表面的水平高度低的水平高度上。第二閘極介電層114的上端部可被定位成更靠近閘極間隔件層130的上表面,而不靠近在中心區中具有最大高度的閘極電極層120的最上部分。第二閘極介電層114的上端部可具有與閘極電極層120的上表面連續的輪廓。舉例而言,在剖視圖中,第二閘極介電層114的上表面可與閘極電極層120的上表面形成實質上連續的曲線而沒有反曲點(inflection point)。在第二閘極介電層114的上端部處,第二閘極介電層114的與閘極電極層120接觸的內側表面的高度可高於第二閘極介電層114的與閘極間隔件層130接觸的外側表面的高度。
第一閘極介電層112與第二閘極介電層114可包含不同的材料。第一閘極介電層112可由介電材料(例如,氧化矽、氮氧化矽或其組合)形成。第二閘極介電層114可包含具有較第一閘極介電層112的介電常數高的介電常數的材料,且可包含例如氧化物、氮化物或高介電常數(k)材料。然而,其示例性實施例
並不限於此。高介電常數材料可指示具有較氧化矽(SiO2)的介電常數高的介電常數的介電材料。高介電常數材料可為例如以下中的一者:氧化鋁(Al2O3)、氧化鉭(Ta2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、氧化鋯(ZrO2)、氧化鋯矽(ZrSixOy)、氧化鉿(HfO2)、氧化鉿矽(HfSixOy)、氧化鑭(La2O3)、氧化鑭鋁(LaAlxOy)、氧化鑭鉿(LaHfxOy)、氧化鉿鋁(HfAlxOy)及氧化鐠(Pr2O3)。在示例性實施例中,第二閘極介電層114亦可包含用於增大電晶體的臨限電壓的元素,例如稀土元素,例如鑭(La)、釓(Gd)、釕(Lu)、釔(Y)或鈧(Sc)。該些元素可用於藉由形成例如電偶極(electric dipole)來增大臨限電壓。
可在與閘極電極層120相交的主動鰭105中形成第一電晶體TR1及第二電晶體TR2的通道區。閘極電極層120可分別在第一區R1及第二區R2中在通道方向上(例如,在X方向上)具有第一長度L1及第二長度L2。第一長度L1及第二長度L2可分別與第一電晶體TR1及第二電晶體TR2的通道長度相同或對應。第二長度L2可大於第一長度L1。舉例而言,第一長度L1可介於約3奈米至約100奈米的範圍內,且第二長度L2可介於約150奈米至約1000奈米的範圍內。閘極電極層120可分別在第一區R1及第二區R2中沿Z方向具有第一最大高度H1及第二最大高度H2。第一最大高度H1與第二最大高度H2可實質上彼此相等,但並不限於此。
閘極電極層120可具有上圓形隅角TC。詳言之,如圖
2A中所示,閘極電極層120可具有在X方向上的兩側上的隅角是圓形的形狀,例如,閘極電極層120中的每一者的頂隅角可在X方向上彼此間隔開且可為圓形的。因此,閘極電極層120在其延伸方向上(例如在Y方向上)在邊緣區中可具有最小厚度。舉例而言,閘極電極層120中的每一者的頂隅角TC沿相應閘極電極層120在Y方向上的整個長度可為例如連續圓形的(例如,彎曲的),以在相應閘極電極層120的頂邊緣區處具有減小的厚度,例如,如沿X方向所量測的。
由於閘極電極層120具有此種形狀(即,在頂邊緣區處在X方向上的減小的寬度),因此閘極電極層120可確保X方向上的分隔距離L3。分隔距離L3是指自閘極電極層120的與接觸插塞160相鄰的外側表面至相鄰接觸插塞160的外側表面的沿X方向的距離。因此,即使在發生接觸插塞160的未對準及/或閘極電極層120的高度偏差的情形中,仍可防止在閘極電極層120與接觸插塞160之間發生電性短路。
閘極電極層120的上表面整體上可具有向上凸起的形狀。閘極電極層120的上表面在第一閘極結構GS1及第二閘極結構GS2中可具有不同的輪廓。然而,在示例性實施例中,閘極電極層120在兩個上隅角TC不為角狀的範圍內可具有各種形狀,但其角度減輕。以下將參照圖3更詳細地闡述閘極電極層120的形狀。
根據示例性實施例,閘極電極層120可分別由單個層形
成,或者可具有堆疊多個層的形式。閘極電極層120可包含例如TiN、TaN、W、WCN、TiAl、TiAlC、TiAlN或其組合,但未必由金屬材料形成。在另一實例中,根據示例性實施例,閘極電極層120可由半導體材料(例如,多晶矽)形成。
閘極間隔件層130可安置於第一閘極結構GS1及第二閘極結構GS2的兩側上。閘極間隔件層130可將源極/汲極區150與閘極電極層120隔離。在閘極間隔件層130的情形中,閘極間隔件層130的面對第一閘極結構GS1及第二閘極結構GS2的內側表面可與第二閘極介電層114接觸,且其外側表面可與源極/汲極區150及第一層間絕緣層192接觸。閘極間隔件層130可具有相對於基板101的底表面較閘極電極層120的厚度小的厚度,例如沿Z方向的高度。閘極間隔件層130的上表面可因此位於與閘極電極層120的上表面的水平高度相同或較閘極電極層120的上表面的水平高度低的水平高度上,且可位於較閘極電極層120的最上部分的水平高度低的水平高度上。閘極間隔件層130的上表面可具有向下凹陷的形狀。因此,閘極間隔件層130在X方向上在其中心區中可具有最小厚度且在其邊緣區中可具有最大厚度。
根據示例性實施例,閘極間隔件層130亦可由多個層形成。閘極間隔件層130可由低介電常數材料形成,且可包含例如SiO、SiN、SiCN、SiOC、SiON及SiOCN中的至少一者。
閘極頂蓋層140可被安置成覆蓋閘極電極層120及閘極間隔件層130的上表面。因此,閘極頂蓋層140的下表面可具有
沿閘極電極層120及閘極間隔件層130的上表面的輪廓。閘極頂蓋層140的下表面在X方向上在中心區中可具有凹陷的區,且在其邊緣區中可具有向下突出的區。閘極頂蓋層140的上表面可為平坦的表面,且閘極頂蓋層140整體上可具有馬蹄形狀,例如,環繞閘極電極層120的上表面及側表面(圖3)。閘極頂蓋層140在X方向上的側表面可與閘極間隔件層130的外表面共面。閘極頂蓋層140可由例如氮化矽形成,且在閘極頂蓋層140的組成物與閘極間隔件層130的組成物不同的情形中,閘極頂蓋層140與閘極間隔件層130之間的介面可被識別為不同。作為另一選擇,即使在閘極頂蓋層140的組成物相似於閘極間隔件層130的組成物的情形中,閘極頂蓋層140與閘極間隔件層130亦可藉由不同的製程形成,且閘極頂蓋層140與閘極間隔件層130的物理性質可因此不同,從而使得閘極頂蓋層140與閘極間隔件層130之間的介面可不同。
源極/汲極區150可安置於主動鰭105上、具有對應的閘極間隔件層130的第一閘極結構GS1及第二閘極結構GS2(例如,每一者)的兩側上。源極/汲極區150可被設置成第一電晶體TR1及第二電晶體TR2的源極區或汲極區。源極/汲極區150可具有源極/汲極區150的上表面被定位成高於閘極電極層120的下表面的升高的源極/汲極結構,但並不限於此。源極/汲極區150在二或更多個主動鰭105上可連接至彼此或者可彼此合併(merge),以形成為單個源極/汲極區150,但示例性實施例並不限於此。
源極/汲極區150可由磊晶層形成,且可包含雜質。舉例而言,當第一電晶體TR1及第二電晶體TR2是p型電晶體時,源極/汲極區150可包含p型摻雜的矽鍺(SiGe)。在另一實例中,當第一電晶體TR1及第二電晶體TR2是n型電晶體時,源極/汲極區150可包含n型摻雜的矽(Si)。在示例性實施例中,源極/汲極區150可包括包含不同濃度的元素及/或摻雜元素的多個區。
接觸插塞160可穿透第一層間絕緣層192及第二層間絕緣層194以連接至源極/汲極區150。接觸插塞160可電性連接至其他組件(例如配線線),以使訊號可被施加至源極/汲極區150。接觸插塞160可被形成為使源極/汲極區150的部分凹陷以連接至源極/汲極區150,但其示例性實施例並不限於此。接觸插塞160可具有在第一閘極結構GS1及第二閘極結構GS2的延伸方向上(例如,在Y方向上)延伸的細長形狀,且可具有例如矩形、橢圓形等的形狀。
接觸插塞160可包括安置於與源極/汲極區150接觸的下表面及側表面上的插塞導電層165及擴散障壁層162。擴散障壁層162可為被形成為構成插塞導電層165的材料的一部分的層,並被源極/汲極區150矽化。接觸插塞160可包含導電材料,例如,氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)、鋁(Al)、銅(Cu)、鎢(W)、鉬(Mo)等。
第一層間絕緣層192及第二層間絕緣層194可被安置成覆蓋裝置隔離層107、源極/汲極區150及閘極頂蓋層140的上表
面。第一層間絕緣層192的高度可與閘極頂蓋層140的高度實質上相同。第一層間絕緣層192與第二層間絕緣層194可為在製程中彼此區分的層,且第一層間絕緣層192及第二層間絕緣層194的相對高度及介面的位置並不限於圖中所示的位置。在另一示例性實施例中,第一層間絕緣層192及第二層間絕緣層194可由單個層形成。第一層間絕緣層192及第二層間絕緣層194可包含例如氧化物、氮化物及氮氧化物中的至少一者,且可包含低介電常數材料。
圖3是示出根據示例性實施例的半導體裝置的一部分的局部分解立體圖。
參照圖3,圖3示出圖1至圖2B的半導體裝置100的第一閘極結構GS1、閘極間隔件層130及閘極頂蓋層140。第一閘極結構GS1可在一個方向上(例如,在Y方向上)延伸,且閘極間隔件層130及閘極頂蓋層140亦可沿第一閘極結構GS1在Y方向上延伸。
在第一閘極結構GS1中,閘極電極層120可具有在X方向上彼此間隔開的兩個上隅角TC均為圓形的形狀。閘極電極層120可被形成為具有較閘極電極層120的兩側上的閘極間隔件層130的厚度大的厚度(即,在Z方向上的高度),因此,閘極電極層120(例如,閘極電極層120的中心)在閘極間隔件層130上方突出預定長度D1。舉例而言,如圖3中所示,閘極電極層120的最上點(例如,閘極電極層120的中心)在閘極間隔件層130的
最上點上方突出長度D1。
詳言之,閘極電極層120可具有第一高度H1(即,在其中心區中沿Z方向的最大高度),且可具有第三高度H3(即,在與閘極間隔件層130接觸的邊緣區處沿Z方向的最小高度)。閘極電極層120可具有在包括中心區的至少一部分中具有平的上表面的區,但其示例性實施例並不限於此。第一閘極結構GS1可在Y方向上延伸預定長度D2,且延伸長度D2可根據示例性實施例及第一電晶體TR1的結構進行各種改變。
閘極間隔件層130可被安置成在第一閘極結構GS1的兩側上具有第四高度H4(即,最大高度)。第四高度H4可小於第一高度H1(即,閘極電極層120的最大高度),且可與第三高度H3(即,閘極電極層120的最小高度)實質上相同或者小於第三高度H3。
閘極頂蓋層140可安置於第一閘極結構GS1及閘極間隔件層130上。閘極頂蓋層140可具有平坦的上表面,且可具有沿第一閘極結構及閘極間隔件層130彎曲的彎曲下表面。閘極頂蓋層140在與閘極頂蓋層140的中心區對應的閘極電極層120上可具有第一厚度T1(即,最小厚度),且在與閘極頂蓋層140的周邊區對應的閘極間隔件層130上可具有第二厚度T2(即,最大厚度)。
圖4A及圖4B是示出根據其他示例性實施例的半導體裝置的一部分的局部放大圖。圖4A及圖4B示出與圖2A的區「A」
對應的區。
參照圖4A,第一閘極結構GS1中的第二閘極介電層114的上端部114E在閘極電極層120與閘極間隔件層130之間可具有平坦的上表面。因此,以與圖2A及圖3的示例性實施例不同的方式,第二閘極介電層114的上端部114E可不具有與閘極電極層120連續的輪廓。第二閘極介電層114的上端部114E可具有與閘極電極層120不連續的輪廓,以使得可在其與閘極電極層120的介面處形成台階。另外,第二閘極介電層114的上端部114E可具有與閘極間隔件層130不連續的輪廓,且可在第二閘極介電層114的上端部114E與閘極間隔件層130之間的介面處形成台階。
參照圖4B,與圖2A及圖3的示例性實施例不同,第一閘極結構GS1中的第二閘極介電層114的上端部114E可不具有與閘極電極層120連續的輪廓,且可具有與閘極間隔件層130連續的輪廓。
如上參照圖4A及圖4B所述,根據示例性實施例,第一閘極結構GS1及第二閘極結構GS2中的第二閘極介電層114的上端部的形狀可進行各種修改。此種結構可藉由包括以下將參照圖9H闡述的製程的製程操作中的製程條件、第二閘極介電層114及閘極電極層120的材料、閘極介電層114的蝕刻速率、閘極介電層114相對於閘極電極層120的相對蝕刻速率等來控制。
圖5及圖6是示出根據其他示例性實施例的半導體裝置的剖視圖。圖5及圖6示出對應於圖2A的橫截面。
參照圖5,在半導體裝置100a中,構成第二閘極結構GS2a的閘極電極層120a的上表面可分別具有兩條或更多條曲線。第二閘極結構GS2a的閘極電極層120a中的每一者的最大高度H5可高於第一閘極結構GS1的閘極電極層120中的每一者的最大高度H1。
端視在X方向上的長度範圍而定,閘極電極層120a的上表面可具有帶有兩條或更多條曲線的形狀。此種形狀可藉由根據在以下將參照圖9H闡述的移除閘極電極層120a的一部分的製程期間的製程條件控制蝕刻劑的流動來獲得。在此種情形中,閘極電極層120a的上隅角TC亦可具有向上凸起的形狀,且閘極電極層120a在與閘極間隔件層130接觸的區中可具有最小厚度。
在示例性實施例中,第二閘極結構GS2a中的閘極電極層120a的最大高度H5可與第一閘極結構GS1中的閘極電極層120的最大高度H1不同。第二閘極結構GS2a的閘極電極層120a可具有相對大的長度,且可因此具有由於在閘極電極層120a的移除製程期間來自側面的蝕刻劑而受影響的程度,所述程度與第一閘極結構GS1中的影響程度不同。第二閘極結構GS2a中的閘極電極層120a的最大高度H5可高於第一閘極結構GS1中的閘極電極層120的最大高度H1。高度差可根據閘極電極層120及閘極電極層120a的長度、閘極間隔件層130的高度、製程條件等進行各種改變。另外,閘極電極層120a的高度差及上表面的形狀未必彼此相關,而是可獨立地應用於以上參照圖2A至圖4闡述的示例性實施
例。
參照圖6,在半導體裝置100b中,閘極間隔件層130a可具有平坦的上表面,且第一閘極結構GS1b及第二閘極結構GS2b的閘極電極層120b可具有較圖2A的半導體裝置100中的形狀更凸起的上表面。
端視在X方向上的寬度、高度、製程條件等而定,閘極間隔件層130a可被形成為具有平坦的上表面。在此種情形中,閘極間隔件層130a亦可被安置成低於閘極電極層120b。另外,閘極電極層120b的上表面可具有向上凸起的形狀以僅在其中心區中具有最大高度而沒有平坦區。然而,閘極間隔件層130a及閘極電極層120b的上表面的形狀彼此不相關,且可分別應用於以上參照圖2A至圖5闡述的示例性實施例。
圖7是示出根據其他示例性實施例的半導體裝置的剖視圖。
參照圖7,在半導體裝置100c中,除了第一區R1及第二區R2之外,基板101亦可具有第三區R3。可在第三區R3中安置包括第三閘極結構GS3的第三電晶體TR3。此外,在第一閘極結構GS1c及第二閘極結構GS2c中,閘極電極層120c可包括第一導電層123c及第二導電層125c。在第一電晶體TR1、第二電晶體TR2及第三電晶體TR3中,閘極電極層120c及120d的上隅角TC可具有彎曲形狀。
第三電晶體TR3可具有與第一電晶體TR1相同的通道
長度,且可具有不同的臨限電壓或工作電壓。舉例而言,第一電晶體TR1可為n型電晶體,且第三電晶體TR3可為p型電晶體。在此種情形中,在第一區R1及第三區R3中,主動鰭105可包含不同導電類型的雜質。
在第一閘極結構GS1c及第二閘極結構GS2c中,閘極電極層120c的第一導電層123c及第二導電層125c可包含不同的材料。舉例而言,第一導電層123c可用於控制功函數(work function),且可包含例如TiN、Ta、TaN、TiAl、TiAlC、TiAlN或其組合。第二導電層125c可包含例如TiN、W、WCN或其組合。
在第三閘極結構GS3中,閘極電極層120d可包括第一導電層123d及第二導電層126d。舉例而言,第一導電層123d可由與第一閘極結構GS1c及第二閘極結構GS2c的第一導電層123c的材料相同的材料形成,且第二導電層126d可由與第一閘極結構GS1c及第二閘極結構GS2c的第二導電層125c的材料不同的材料形成。另外,第二導電層126d可具有在上部分中具有相對寬的寬度且在下部分中具有相對薄且細長的延伸部(extension)的形狀。此種結構可在以下將參照圖9F闡述的形成閘極電極層120d的製程中端視第一導電層123d及第二導電層126d的相對厚度、第三閘極結構GS3的大小等來獲得。
如上所述,在示例性實施例中,半導體裝置100c可包括具有不同臨限電壓的多個電晶體TR1、TR2及TR3。在相應電晶體TR1、TR2及TR3中,構成閘極電極層120c及120d的導電
層123c、123d、125c及126d的數目、材料、結構等可進行各種改變。儘管示例性實施例藉由實例的方式示出閘極電極層120c及120d具有圓形上隅角TC,然而其示例性實施例並不限於此。舉例而言,第一電晶體TR1、第二電晶體TR2及第三電晶體TR3的閘極電極層120c及120d的一部分亦可具有實質上直角的上隅角,且第一電晶體TR1、第二電晶體TR2及第三電晶體TR3的閘極電極層120c及120d的其他部分可具有圓形上隅角TC。
圖8是示出根據示例性實施例的製造半導體裝置的方法的流程圖。圖9A至圖9J是示出根據示例性實施例的製造半導體裝置的方法中的階段的視圖。圖9A至圖9J示出對應於圖2A的區。
參照圖8及圖9A,在操作S110中,可藉由對具有第一區R1及第二區R2的基板101進行圖案化來形成主動鰭105,且可形成犧牲閘極結構180及源極/汲極區150。此外,在本操作中,亦可形成閘極間隔件層130P及第一層間絕緣層192。
第一區R1及第二區R2可分別為電晶體區,且基板101可包括導電區,例如摻雜有雜質的阱結構。主動鰭105可藉由形成裝置隔離層107(參見圖2B)來界定,且可具有自基板101突出的形狀。主動鰭105可包括雜質區。
犧牲閘極結構180可藉由後續製程形成於安置有第一閘極介電層112及第二閘極介電層114、閘極電極層120以及閘極頂蓋層140的區中,如圖2A中所示。犧牲閘極結構180中的每一者可包括犧牲閘極絕緣層182及犧牲閘極電極層185。犧牲閘極結構
180可被形成為更包括安置於犧牲閘極電極層185上的犧牲閘極頂蓋層。犧牲閘極頂蓋層可藉由在形成第一層間絕緣層192時實行的平坦化製程來移除,且因此可不保留犧牲閘極頂蓋層。犧牲閘極絕緣層182可為絕緣層,且犧牲閘極電極層185可為導電層,但並不限於此。舉例而言,犧牲閘極絕緣層182可包含例如氧化矽,且犧牲閘極電極層185可包含例如多晶矽。
閘極間隔件層130P可形成於犧牲閘極結構180的兩個側壁上。閘極間隔件層130P處於閘極間隔件層130具有如圖2A中所示的最終形狀之前的狀態,且因此,由與圖式編號130不同的圖式編號130P標示。閘極間隔件層130P可被形成為具有在其形成時變窄的頂部部分,且接著,可在形成第一層間絕緣層192時實行的平坦化製程中移除頂部部分。因此,閘極間隔件層130P可具有如圖中所示的平坦的上表面。
在移除閘極間隔件層130的兩側上的主動鰭105的一部分之後,可在凹陷的主動鰭105上形成源極/汲極區150。源極/汲極區150可使用例如選擇性磊晶生長(selective epitaxial growth,SEG)製程來形成。源極/汲極區150可包含摻雜有雜質的半導體材料,例如Si、SiGe或SiC。詳言之,源極/汲極區150可包含n型或p型雜質。雜質可在源極/汲極區150的形成期間在原位(in-situ)摻雜,或者可在源極/汲極區的生長之後單獨植入。源極/汲極區150可在生長製程期間沿結晶學上穩定的平面生長,以具有在Y方向上具有例如五邊形形狀、六邊形形狀或與其類似的
形狀的橫截面,但其示例性實施例並不限於此。
第一層間絕緣層192可藉由以下方式來形成:沈積絕緣材料以覆蓋犧牲閘極結構180及源極/汲極區150,且接著藉由平坦化製程暴露出犧牲閘極電極層185的上表面。第一層間絕緣層192可包含例如氧化物、氮化物及氮氧化物中的至少一者,且可包含低介電常數材料。
參照圖8及圖9B,在操作S120中,可移除犧牲閘極結構180,藉此形成開口OP。
犧牲閘極結構180可相對於下部的裝置隔離層107、主動鰭105及閘極間隔件層130P選擇性地移除,以形成暴露出裝置隔離層107、主動鰭105及閘極間隔件層130P的開口OP。犧牲閘極結構180的移除製程可使用乾式蝕刻製程及濕式蝕刻製程中的至少一者來實行。
參照圖8及圖9C,在S130中,可在開口OP中形成第一閘極介電層112及第二閘極介電層114。第一閘極介電層112與第二閘極介電層114可被形成為在第一區R1及第二區R2中具有實質上相同的厚度。第一閘極介電層112可形成於暴露於開口OP的下表面的主動鰭105的上表面上。根據示例性實施例,第一閘極介電層112亦可藉由對主動鰭105的一部分進行氧化來形成。第二閘極介電層114可沿開口OP的側壁及下表面實質上共形地形成。第一閘極介電層112的形成製程及第二閘極介電層114的形成製程可單獨實行。第一閘極介電層112及第二閘極介電層114
可使用例如原子層沈積(atomic layer deposition,ALD)、化學氣相沈積(chemical vapor deposition,CVD)或物理氣相沈積(physical vapor deposition,PVD)製程來形成。第一閘極介電層112及第二閘極介電層114可包含例如氧化物、氮化物或高介電常數材料。
接下來,將參照圖8以及圖9D至圖9F來闡述在操作S140中形成閘極電極層120P。圖9D至圖9F藉由實例的方式示出在閘極電極層120P(參見圖9F)由多個導電層形成的情形中的製造方法。
參照圖9D,可在開口OP中形成用於形成閘極電極層120P的第一層122。
第一層122可為藉由後續製程形成閘極電極層120P的一部分的層。舉例而言,當閘極電極層120P包括多個導電層時,第一層122可包括所述多個導電層中形成於下部分中的至少一個層。舉例而言,在圖7的半導體裝置100c的情形中,可在此操作中形成第一導電層123d。第一層122可共形地形成於開口OP中的第二閘極介電層114上。
參照圖9E,可在開口OP中部分地移除第一層122。
首先,可在第一層122上形成塗層CL,以將開口OP的下部分填充至預定高度。塗層CL可包含碳質材料,且例如可由非晶碳層(amorphous carbon layer,ACL)或碳系旋塗硬罩幕(carbon-based spin-on hardmask,C-SOH)層形成。
接下來,可將開口OP中的塗層CL上的第一層122移
除至預定深度。所述深度可介於例如開口OP的總深度的約20%至約70%的範圍內。可不移除由塗層CL覆蓋的第一層122的下部分。藉由移除第一層122的上部區,可確保用於後續形成的第二層124(參見圖9F)的間隙填充的空間。
在移除第一層122的一部分的製程期間,第一閘極介電層112及第二閘極介電層114可保留而不被移除,但其示例性實施例並不限於此。根據示例性實施例,在此操作中,亦可一起移除塗層CL上方的第二閘極介電層114。在此種情形中,在最終獲得的結構中,第二閘極介電層114可被安置成在閘極電極層120的一側上具有相對低的高度。
在移除第一層122的一部分的移除製程之後,可移除塗層CL。塗層CL可例如藉由灰化或剝落製程移除。
參照圖9F,可形成第二層124以構成開口OP中的閘極電極層120P。
第二層124可為構成閘極電極層120P的一部分的層。舉例而言,當閘極電極層120P包括多個導電層時,第二層124可為除了在以上參照圖9D闡述的操作中形成的層之外的層。舉例而言,在圖7的半導體裝置100c的情形中,可在此操作中形成第二導電層126d。第二層124可被形成為完全填充開口OP。第二層124可由與第一層122的材料相同的材料或不同的材料形成,且在第二層124由與第一層122的材料相同的材料形成的情形中,第一層與第二層之間的介面可為難以區分的。
在對形成第二層124的材料進行沈積之後,可自第一層間絕緣層192的上表面移除形成第二層124的材料。移除製程可使用例如化學機械研磨(chemical mechanical polishing,CMP)等平坦化製程來實行。因此,可形成包括第一層122及第二層124的閘極電極層120P。由於閘極電極層120P處於具有如圖2A中所示的最終獲得的形式之前的狀態,因此閘極電極層120P由與圖2A的圖式編號不同的圖式編號120P標示。在下文中,閘極電極層120P可被示出為單個層。
在示例性實施例中,舉例而言,當閘極電極層120P由單個層形成時,可藉由在以上參照圖9D闡述的操作中沈積導電材料以填充開口OP來形成閘極電極層120P。另外,即使當閘極電極層120P由多個層形成時,在所述多個層依序堆疊的情形中,可在以上參照圖9D闡述的操作中依序沈積導電材料以填充開口OP,藉此形成閘極電極層120P。
參照圖8及圖9G,在操作S150中可移除閘極間隔件層130P的部分。
閘極間隔件層130P可相對於第一層間絕緣層192及閘極電極層120P選擇性地移除。閘極間隔件層130P可使用乾式蝕刻製程或濕式蝕刻製程自暴露的上部分凹陷至預定深度D3。慮及所需閘極電極層120的最終高度,深度D3可被確定為閘極間隔件層130保持在與所需閘極電極層120的最終高度相同的高度或較所需閘極電極層120的最終高度低的高度下的深度。可在閘極間
隔件層130P已被移除的區中形成隧道部分ST。隧道部分ST可具有在Y方向上延伸的形狀。舉例而言,當移除閘極間隔件層130P的一部分時,在閘極間隔件層130P的中心區中實行相對大量蝕刻的情形中,閘極間隔件層130在上表面上可具有凹形區,但其示例性實施例並不限於此。
在此操作中,可一起移除或者可保留而不移除閘極電極層120P的側上的第二閘極介電層114。舉例而言,圖4B的示例性實施例的情形可對應於藉由在此操作中將第二閘極介電層114與閘極間隔件層130P的一部分一起移除而形成的結構。
參照圖8及圖9H,在操作S160中可移除閘極電極層120P的一部分。
閘極電極層120P可相對於第一層間絕緣層192及閘極間隔件層130選擇性地凹陷。可在閘極電極層120P已被移除的區中形成凹陷區GR。閘極電極層120P可自暴露的上表面及暴露的側表面蝕刻。在蝕刻製程中,如圖9H的放大圖中的箭頭所示,由於自側表面經由隧道部分ST以及自上表面供應(例如,引入)蝕刻劑,因此隅角區中的蝕刻量可為相對大。因此,當在適當的條件下(例如藉由等向性蝕刻製程條件而不施加偏壓或藉由對其施加顯著減小的偏壓)移除閘極電極層120P時,閘極電極層120可被形成為具有圓形隅角TC。
在此操作中,可將閘極電極層120P的側上的第二閘極介電層114與閘極電極層120P的一部分一起移除。若在以上參照
圖9E闡述的製程中,構成閘極電極層120P的第一層122的上部分被留下而不完全移除,則可在此操作中自側表面實行蝕刻,藉此移除第一層122的整個上部分。
藉由此操作,可形成包括第一閘極介電層112及第二閘極介電層114以及閘極電極層120的第一閘極結構GS1及第二閘極結構GS2。最終,閘極電極層120可被形成為向閘極間隔件層130的上部突出預定長度。
參照圖8及圖9I,在操作S170中,可在閘極電極層120上形成閘極頂蓋層140。
閘極頂蓋層140可被形成為填充凹陷區GR,同時覆蓋閘極電極層120及閘極間隔件層130的上表面。在沈積形成閘極頂蓋層140的材料之後,可實施平坦化製程。因此,閘極頂蓋層140可被形成為填充相鄰的第一層間絕緣層192之間的空間且具有平坦的上表面。閘極頂蓋層140可由例如SiN形成。由於閘極頂蓋層140可具有與閘極間隔件層130的製程步驟(procedure)不同的製程步驟,因此即使在閘極頂蓋層140與閘極間隔件層130的組成物相似的情形中,閘極頂蓋層140與閘極間隔件層130之間的介面亦可為不同的。
參照圖8及圖9J,在S180中,可形成接觸孔PH以暴露出源極/汲極區150。
首先,可在閘極頂蓋層140及第一層間絕緣層192上形成第二層間絕緣層194。可藉由移除第一層間絕緣層192及第二層
間絕緣層194來形成接觸孔PH以暴露出源極/汲極區150。端視縱橫比(aspect ratio)而定,接觸孔PH在基板101的上表面上可具有傾斜的側表面。一起參照圖2A,可在接觸孔PH中依序沈積導電材料,以形成包括擴散障壁層162及插塞導電層165的接觸插塞160。
若接觸插塞160被形成為與第一閘極結構GS1及第二閘極結構GS2相鄰,則在發生未對準時接觸插塞160可與鄰近其的閘極電極層120的側表面接觸。在此種情形中,可能發生缺陷,例如電性短路。然而,在示例性實施例中,由於閘極電極層120的上部分具有圓形隅角,因此可防止此種缺陷。
圖10是示出根據示例性實施例的包括半導體裝置的電子設備的方塊圖。
參照圖10,根據示例性實施例的電子裝置1000可包括通訊單元1010、輸入單元1020、輸出單元1030、記憶體1040及處理器1050。
通訊單元1010可包括有線/無線通訊模組,且可包括無線網際網路模組、近場通訊模組、全球定位系統(global positioning system,GPS)模組、行動通訊模組等。包括在通訊單元1010中的有線/無線通訊模組可藉由各種通訊協定連接至外部通訊網路以傳輸及接收資料。
輸入單元1020可包括機械開關、觸控螢幕、語音辨識模組等作為容許使用者控制電子裝置1000的操作的模組。另外,
輸入單元1020亦可包括使用追蹤球、激光指示器方案等操作的滑鼠,或者可包括手指滑鼠裝置。此外,輸入單元1020可更包括各種感測器模組,使用者藉由所述感測器模組輸入資料。
輸出單元1030可以語音或影像的形式輸出由電子裝置1000處理的資訊,且記憶體1040可儲存用於對處理器1050進行處理及控制的程式、資料等。處理器1050可根據需要的操作將命令傳送至記憶體1040,以因此儲存資料或自記憶體1040擷取資料。
記憶體1040可藉由嵌置於電子裝置1000中的介面或藉由單獨的介面與處理器1050進行通訊。舉例而言,當記憶體1040藉由單獨的介面與處理器1050進行通訊時,處理器1050可藉由各種介面標準(例如,安全數位(secure digital,SD)、安全數位高容量(secure digital high capacity,SDHC)、安全數位擴展容量(secure digital extended capacity,SDXC)、微型安全數位(MICRO SD)、通用串列匯流排(universal serial bus,USB)等)將資料儲存於記憶體1040中或自記憶體1040擷取資料。
處理器1050可控制包括在電子裝置1000中的各個部件的操作。處理器1050可實行對與語音通訊、視訊電話、資料通訊等相關的資料或者與多媒體再現及管理相關的資料的控制及處理。另外,處理器1050可由使用者經由輸入單元1020對輸入進行處理,且可經由輸出單元1030輸出處理結果。此外,處理器1050可將控制電子裝置1000的操作所需的資料儲存於記憶體1040
中,或者可自記憶體1040擷取資料。處理器1050及記憶體1040中的至少一者可包括根據如上參照圖1至圖7所闡述的各種示例性實施例的半導體裝置。
圖11是示出根據示例性實施例的包括半導體裝置的系統的示意圖。
參照圖11,系統2000可包括控制器2100、輸入/輸出裝置2200、記憶體2300及介面2400。系統2000可為行動系統或者傳輸或接收資訊的系統。行動系統可為例如個人數位助理(personal digital assistant,PDA)、可攜式電腦、網路平板、無線電話、行動電話、數位音樂播放機或記憶卡。
控制器2100可執行程式且可用於控制系統2000。舉例而言,控制器2100可為微處理器、數位訊號處理器、微控制器或與其類似的裝置。
輸入/輸出裝置2200可用於輸入或輸出系統2000的資料。系統2000可使用輸入/輸出裝置2200連接至外部裝置(例如個人電腦或網路),以與外部裝置交換資料。輸入/輸出裝置2200可為例如小鍵盤、鍵盤或顯示器。
記憶體2300可在其中為控制器2100的操作儲存代碼及/或資料,及/或可在其中儲存由控制器2100處理的資料。
介面2400可用作系統2000與外部不同裝置之間的資料傳輸通路。控制器2100、輸入/輸出裝置2200、記憶體2300及介面2400可經由匯流排2500彼此進行通訊。
控制器2100或記憶體2300中的至少一者可包括根據如上參照圖1至圖7所闡述的各種示例性實施例的半導體裝置。
如上所述,根據示例性實施例,藉由控制閘極電極的形狀,可提供具有改善的可靠性的半導體裝置。此外,藉由首先使閘極間隔件層凹陷且接著使閘極電極層凹陷,可提供製造具有改善的可靠性的半導體裝置的方法。亦即,在製作製程中可首先使間隔件層凹陷,然後自側表面以及上表面對閘極電極層進行蝕刻以具有圓形隅角,藉此使閘極電極的寬度最小化並增大閘極電極與相鄰的接觸插塞之間的距離。
本文中已揭露示例性實施例,且儘管採用具體用語,但該些用語僅用於並被解釋為通常意義及闡述性意義,而並非用以限制目的。在一些情況下,除非另外明確地指明,否則如在本申請案提出申請之前此項技術中具有通常知識者將理解,結合特定實施例所闡述的特徵、特性及/或元件可單獨使用或與結合其他實施例所闡述的特徵、特性及/或元件組合使用。因此,熟習此項技術者將理解,在不背離在以下申請專利範圍中所述的本發明的精神及範圍的條件下,可作出各種形式及細節上的改變。
100:半導體裝置
101:基板
105:主動鰭
112:第一閘極介電層
114:第二閘極介電層/閘極介電層
120:閘極電極層
130:閘極間隔件層
140:閘極頂蓋層
150:源極/汲極區
160:接觸插塞
162:擴散障壁層
165:插塞導電層
192:第一層間絕緣層
194:第二層間絕緣層
A:區
GS1:第一閘極結構
GS2:第二閘極結構
H1:第一最大高度/第一高度/最大高度
H2:第二最大高度
I-I'、II-II':線
L1:第一長度
L2:第二長度
L3:分隔距離
R1:第一區
R2:第二區
TC:上圓形隅角/頂隅角/上隅角/圓形上隅角/圓形隅角
TR1:第一電晶體/電晶體
TR2:第二電晶體/電晶體
X、Y、Z:方向
Claims (19)
- 一種半導體裝置,包括:基板,具有主動區;閘極結構,位於所述主動區上,所述閘極結構包括閘極介電層及閘極電極層,且所述閘極電極層具有圓形上隅角;以及閘極間隔件層,位於所述閘極結構的側表面上,所述閘極間隔件層具有位於較所述閘極電極層的上表面低的高度水平處的上表面,其中所述閘極間隔件層的所述上表面具有向下凹陷的形狀,且所述閘極間隔件層中的每一者在一方向上相較於邊緣區的中心區域中具有最小厚度。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極電極層在第一方向上延伸以與所述主動區相交,所述閘極電極層在與所述第一方向垂直的第二方向上在兩側上具有圓形隅角。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極電極層的所述上表面具有向上凸起的形狀。
- 如申請專利範圍第1項所述的半導體裝置,更包括閘極頂蓋層,所述閘極頂蓋層覆蓋所述閘極電極層的所述上表面及所述閘極間隔件層的所述上表面。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極介電層覆蓋所述閘極電極層的下表面及側表面,所述閘極介電 層具有在所述閘極電極層的所述側表面上的上端部,所述上端部位於與所述閘極電極層的所述上表面相同的高度水平處或位於較所述閘極電極層的所述上表面低的高度水平處。
- 如申請專利範圍第5項所述的半導體裝置,其中所述閘極介電層的所述上端部位於較靠近所述閘極電極層的最上部分而言更靠近所述閘極間隔件層的所述上表面的高度水平處。
- 如申請專利範圍第5項所述的半導體裝置,其中所述閘極介電層包括位於所述基板上的第一閘極介電層以及位於所述第一閘極介電層上且延伸至所述閘極電極層的所述側表面上的第二閘極介電層,且所述閘極介電層的所述上端部是所述第二閘極介電層的上端部。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極介電層的上端部具有與所述閘極電極層的所述上表面連續的輪廓。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極介電層的上端部具有與所述閘極間隔件層的所述上表面連續的輪廓。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極電極層在第一方向上延伸,所述閘極電極層的中心區處的第一厚度大於邊緣區處的第二厚度,所述第一厚度與所述第二厚度是沿與所述第一方向垂直的第二方向量測的。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極電極層的所述上表面具有兩條或更多條曲線。
- 如申請專利範圍第1項所述的半導體裝置,其中所述閘極電極層包括:第一導電層,延伸至所述閘極間隔件層的側表面上;以及第二導電層,位於在所述閘極間隔件層的所述側表面上的所述第一導電層的部分之間。
- 如申請專利範圍第1項所述的半導體裝置,更包括:源極/汲極區,在位於所述閘極結構的兩側上的所述主動區中;以及接觸插塞,連接至所述源極/汲極區。
- 一種半導體裝置,包括:基板,具有主動區且具有第一區及第二區;第一閘極電極層,位於所述第一區上以在第一方向上延伸,所述第一閘極電極層在與所述第一方向垂直的第二方向上具有第一長度;第二閘極電極層,位於所述第二區上以在所述第一方向上延伸,所述第二閘極電極層在所述第二方向上具有較所述第一長度大的第二長度;以及閘極間隔件層,分別位於所述第一閘極電極層及所述第二閘極電極層的側上,其中所述第一閘極電極層及所述第二閘極電極層在所述第二 方向上在邊緣區處具有第一厚度,且在所述邊緣區內部的區中具有較所述第一厚度大的第二厚度,其中所述閘極間隔件層的所述上表面具有向下凹陷的形狀,且所述閘極間隔件層中的每一者在一方向上相較於邊緣區的中心區域中具有最小厚度。
- 如申請專利範圍第14項所述的半導體裝置,其中所述第一閘極電極層及所述第二閘極電極層具有上圓形隅角,且所述閘極間隔件層具有位於較所述第一閘極電極層的上表面及所述第二閘極電極層的上表面低的高度水平處的上表面。
- 如申請專利範圍第14項所述的半導體裝置,其中所述第一閘極電極層的上表面具有向上凸起的形狀,且所述第二閘極電極層的上表面具有與所述第一閘極電極層的所述上表面的輪廓不同的輪廓。
- 如申請專利範圍第14項所述的半導體裝置,其中包括所述第一閘極電極層的第一電晶體的工作電壓低於包括所述第二閘極電極層的第二電晶體的工作電壓。
- 一種半導體裝置,包括:基板,具有主動區;閘極結構,位於所述主動區上,所述閘極結構包括閘極介電層及閘極電極層,且所述閘極電極層具有圓形上隅角;閘極間隔件層,位於所述閘極結構的側表面上,所述閘極間 隔件層具有位於較所述閘極電極層的上表面低的高度水平處的上表面,其中所述閘極間隔件層的所述上表面具有向下凹陷的形狀;閘極頂蓋層,覆蓋所述閘極電極層的所述上表面及所述閘極間隔件層的所述上表面,其中所述閘極間隔件層的不與所述閘極結構接觸的外側表面與所述閘極頂蓋層的側表面共面。
- 一種半導體裝置,包括:基板,具有主動區且具有第一區及第二區;第一閘極電極層,位於所述第一區上以在第一方向上延伸,所述第一閘極電極層在與所述第一方向垂直的第二方向上具有第一長度;第二閘極電極層,位於所述第二區上以在所述第一方向上延伸,所述第二閘極電極層在所述第二方向上具有較所述第一長度大的第二長度;以及閘極間隔件層,分別位於所述第一閘極電極層及所述第二閘極電極層的側上,其中所述第一閘極電極層及所述第二閘極電極層在所述第二方向上在邊緣區處具有第一厚度,且在所述邊緣區內部的區中具有較所述第一厚度大的第二厚度,其中所述閘極間隔件層的所述上表面具有向下凹陷的形狀,且其中所述第一閘極電極層的最大厚度小於所述第二閘極電極 層的最大厚度。
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