US20160204221A1 - Bottom-up metal gate formation on replacement metal gate finfet devices - Google Patents

Bottom-up metal gate formation on replacement metal gate finfet devices Download PDF

Info

Publication number
US20160204221A1
US20160204221A1 US14/592,042 US201514592042A US2016204221A1 US 20160204221 A1 US20160204221 A1 US 20160204221A1 US 201514592042 A US201514592042 A US 201514592042A US 2016204221 A1 US2016204221 A1 US 2016204221A1
Authority
US
United States
Prior art keywords
trench
metal
gate
work function
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/592,042
Other versions
US9379221B1 (en
Inventor
Hong He
Juntao Li
Junli Wang
Chih-Chao Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HE, HONG, LI, JUNTAO, YANG, CHIH-CHAO, WANG, JUNLI
Priority to US14/592,042 priority Critical patent/US9379221B1/en
Priority to PCT/IB2016/050022 priority patent/WO2016110793A1/en
Priority to CN201680005203.7A priority patent/CN107112217B/en
Priority to JP2017530173A priority patent/JP6688301B2/en
Priority to GB1706263.9A priority patent/GB2549621B/en
Priority to DE112016000182.7T priority patent/DE112016000182B4/en
Publication of US9379221B1 publication Critical patent/US9379221B1/en
Application granted granted Critical
Publication of US20160204221A1 publication Critical patent/US20160204221A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Definitions

  • the present invention relates to metal gate formation, and more specifically, to metal gate formation on replacement metal gate fin field effect transistor (finFET) devices.
  • finFET replacement metal gate fin field effect transistor
  • a replacement metal gate (RMG) process architecture is a gate last versus a gate first architecture.
  • RMG finFET device fabrication typically includes initially forming a dummy gate structure that is subsequently removed to form a gate pocket after spacer etch and source/drain epitaxy merge.
  • a high dielectric constant (high-k) layer, work function metal, and gate metal are filled into the gate pocket, and chemical-mechanical planarization (CMP) is performed to planarize the topology.
  • CMP chemical-mechanical planarization
  • the gate metal material is then recessed partially and a dielectric cap is formed through damascene processing.
  • a method of fabricating a replacement metal gate in a transistor device includes forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer; removing the dummy gate structure so as to expose a trench within the insulating layer; conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer; recessing the work function metal layer below a top of the trench; and selectively forming a gate metal only on exposed surfaces of the work function metal layer.
  • a method of fabricating a fin field effect transistor (finFET) device includes forming a substrate; forming a fin connecting a source region and a drain region over the substrate; forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer; removing the dummy gate structure so as to expose a trench within the insulating layer; conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer; recessing the work function metal layer below a top of the trench; and selectively forming a gate metal only on exposed surfaces of the work function metal layer.
  • FIG. 1 is a top-down view of a finFET device fabricated according to an embodiment of the invention
  • FIG. 2 is a cross-sectional view of a stage in the formation of an exemplary finFET device according to an embodiment of the invention
  • FIG. 3 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to an embodiment of the invention.
  • FIG. 4 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 5 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 6 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 7 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 8 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 9 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 10 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 11 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 12 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 13 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 14 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 15 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 16 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 17 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention.
  • FIG. 18 is a cross-sectional view of another stage in the formation of an exemplary finFET according to an embodiment of the invention.
  • part of the fabrication of an RMG finFET device involves forming a partial recess in the metal gate for formation of a dielectric cap. This partial recessing of the gate metal can present a challenge from the standpoint of the reactive ion etch (RIE) required.
  • RIE reactive ion etch
  • conventional gate metal fill techniques may result in a seam or void within the gate metal layer.
  • Embodiments of the RMG finFET device and process of fabricating the device detailed herein include bottom-up formation through selective metal growth.
  • FIG. 1 is a top-down view of a finFET device 100 fabricated according to an embodiment of the invention.
  • the conducting channel between the source and gate is wrapped in a silicon fin 125 and finFETs are generally known.
  • the description herein focuses on the differences in fabrication of a gate region 101 .
  • ILD inter-level dielectric
  • Two fins 125 wrapped in silicon, for example, are shown with source 102 and drain 103 sides in the exemplary finFET device 100 . In alternate embodiments, one or a different number of fins 125 may be formed.
  • the gate region 101 is shown in the top-down view of FIG. 1 .
  • the gate region 101 is formed by removing and replacing a dummy gate 140 ( FIG. 2 ) with the gate metal 190 ( FIGS. 14, 15 ).
  • embodiments of the invention relate to bottom-up formation of the replacement gate 101 through growth of the gate metal 190 .
  • Two figures are shown for each stage of the processing to illustrate two different gate widths. The stages shown in subsequent figures are cross sectional views across the gate as indicated by A-A.
  • the cross-sections indicated by A-A and B-B are both detailed in FIG. 1 .
  • the cross-section indicated by A-A is through a fin 125 .
  • the cross-sectional structure 104 includes a substrate 110 with a silicon layer 130 representing the fin 125 above it.
  • the ILD 120 forms a trench in which the gate region 101 is formed.
  • the cross-section indicated by B-B is through the gate region 101 .
  • the cross-sectional structure 105 includes a substrate 110 with ILD 120 formed above and also including the trench in which the gate region 101 is formed.
  • FIGS. 2 through 18 show cross-sectional views at A-A.
  • FIG. 2 is a cross-sectional view of a stage 200 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 3 is a cross-sectional view of the stage 200 - 2 in the formation of another exemplary finFET device according to an embodiment of the invention.
  • the trench 121 is wider in stage 200 - 2 shown in FIG. 3 than the trench 121 shown in FIG. 2 .
  • a silicon layer 130 indicating the fin 125 is shown as being formed on the substrate 110 .
  • a trench 121 is formed in the ILD 120 .
  • the silicon layer 130 may represent an epitaxial merge of the fins 125 shown in FIG. 1 .
  • a dummy gate 140 of a poly-silicon or amorphous-silicon is shown beneath a gate hardmask 150 in the trench 121 of the ILD 120 .
  • An oxide layer 145 which may be the same material as the ILD 120 or a different oxide is beneath the dummy gate 140 .
  • the gate hardmask 155 is above the dummy gate 140 .
  • the same material as the gate hardmask 155 or a different material may acts as a sidewall spacer 150 between the dummy gate 140 and the ILD 120 based on etching.
  • the material of the gate hardmask 155 may be silicon nitride (SiN).
  • SiN silicon nitride
  • the stages 200 - 1 and 200 - 2 shown in FIGS. 2 and 3 are considered the initial stages in the formation of a finFET device 100 , because stages preceding stages 200 - 1 and 200 - 2 are the same as those of prior finFET device formation processes.
  • FIG. 4 is a cross-sectional view of another stage 300 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 5 is a cross-sectional view of the stage 300 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • the oxide layer 145 , dummy gate 140 , and gate hardmask 155 are pulled to result in the stages 300 - 1 and 300 - 2 .
  • a dry etch is first performed to etch back the hardmask 155 (which may have some effect on the sidewall spacer 150 , as well).
  • a wet etch is performed to etch the dummy gate 140 and oxide layer 145 .
  • the sidewall spacer 150 which may be somewhat shortened by the dry etch process, is left as shown in FIGS. 4 and 5 .
  • FIG. 6 is a cross-sectional view of another stage 400 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 7 is a cross-sectional view of the stage 400 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • a high dielectric constant (high-k) dielectric layer 160 and a work function metal 170 are deposited conformally along the gate hardmask 150 and on a surface of the silicon layer 130 .
  • a blanket conformal deposition is followed by CMP down to the ILD 120 .
  • Exemplary materials used for the dielectric layer 160 include hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), a hafnium silicate (HfSiO x ), zirconium dioxide (ZrO 2 ), or a hafnium zirconate (HfZrO x ).
  • the work function metal 170 may be tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum carbide (TiAlC), or TiC, for example.
  • FIG. 8 is a cross-sectional view of another stage 500 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 9 is a cross-sectional view of the stage 500 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • An organic planarizing layer (OPL) 180 is deposited and etched back below the top of the trench 121 , as shown in FIGS. 8 and 9 , so that the OPL 180 is recessed in the trench coated with the work function metal 170 .
  • the OPL 180 is a photoresist-like material used to reduce the topography.
  • An organic dielectric layer (ODL) may be used as an OPL 180 .
  • FIG. 1 is deposited and etched back below the top of the trench 121 , as shown in FIGS. 8 and 9 , so that the OPL 180 is recessed in the trench coated with the work function metal 170 .
  • the OPL 180 is a photoresist-like material
  • FIG. 10 is a cross-sectional view of another stage 600 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 11 is a cross-sectional view of the stage 600 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • the work function metal 170 is etched to be partially recessed to the level of the recessed OPL 180 .
  • FIG. 12 is a cross-sectional view of another stage 700 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 13 is a cross-sectional view of the stage 700 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • the OPL 180 is stripped leaving the recessed work function metal 170 exposed.
  • the OPL 180 may be stripped with a gas including carbon dioxide, for example.
  • FIG. 14 is a cross-sectional view of another stage 800 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 15 is a cross-sectional view of the stage 800 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • a gate metal 190 is grown via selective metal growth on the work function metal 170 surface.
  • FIGS. 14 and 15 illustrate a key difference in the embodiments described herein as compared with current processes for forming the replacement gate.
  • the gate metal 190 is grown via selective metal growth such that deposition and etching via RIE is not required according to the embodiments.
  • the work function metal 170 acts as a seeding layer that the gate metal 190 cannot grow without, such that the gate metal 190 grows only on the surfaces of the workfunction metal 170 .
  • the gate metal 190 can be grown to be recessed, as well, without requiring any etching.
  • the gate metal 190 may be tungsten (W), aluminum (Al), cobalt (Co), phosphorous (P), or boron (B), for example.
  • the gate metal 190 may instead be W, P, or B doped with Co, for example.
  • stages 800 - 1 and 800 - 2 indicate that when the trench 121 is sufficiently narrow (as in stage 800 - 1 ), growth of the gate metal 190 will result in a continuous fill. That is, the growth of the gate metal 190 at the two sides of the trench 121 in the cross-sectional view shown in FIG. 14 will be close enough to form a continuous gate metal 190 layer as shown. To the contrary, the growth of the gate metal 190 at the two sides of the trench 121 in the cross-sectional view shown in FIG. 15 will be sufficiently separated such that a gap 191 will result.
  • FIG. 16 is a cross-sectional view of another stage 900 - 1 in the formation of an exemplary finFET device according to an embodiment of the invention.
  • FIG. 17 is a cross-sectional view of the stage 900 - 2 in the formation of another exemplary finFET device according to another embodiment of the invention.
  • a dielectric cap 195 is formed over the gate metal 190 in a damascene process.
  • the dielectric cap 195 may be a silicon nitride (SiN) material.
  • the SiN material may be formed at a temperature below 500 degrees Celsius.
  • the dielectric cap 195 fills the gap 191 , as well. As noted above, no such gap 191 is present in the embodiment shown in FIGS.
  • FIG. 18 is a cross-sectional view of another stage 1000 in the formation of an exemplary finFET 100 according to an embodiment of the invention.
  • This stage 1000 applies to the finFET device with the relatively wider gate 101 (and, thus, the gap 191 ).
  • the dielectric cap 195 is removed and a tungsten (W) 197 refill is performed as shown.
  • This W 197 fill provides the necessary gate conductivity that cannot be achieved with the gap 191 .

Abstract

A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure over a substrate, the dummy gate structure being surrounded by an insulating layer, and removing the dummy gate structure so as to expose a trench within the insulating layer. The method also includes conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer, recessing the work function metal layer below a top of the trench, and selectively forming a gate metal only on exposed surfaces of the work function metal layer

Description

    BACKGROUND
  • The present invention relates to metal gate formation, and more specifically, to metal gate formation on replacement metal gate fin field effect transistor (finFET) devices.
  • Generally, a replacement metal gate (RMG) process architecture is a gate last versus a gate first architecture. RMG finFET device fabrication typically includes initially forming a dummy gate structure that is subsequently removed to form a gate pocket after spacer etch and source/drain epitaxy merge. A high dielectric constant (high-k) layer, work function metal, and gate metal are filled into the gate pocket, and chemical-mechanical planarization (CMP) is performed to planarize the topology. The gate metal material is then recessed partially and a dielectric cap is formed through damascene processing.
    • SUMMARY
  • According to one embodiment of the present invention, a method of fabricating a replacement metal gate in a transistor device includes forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer; removing the dummy gate structure so as to expose a trench within the insulating layer; conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer; recessing the work function metal layer below a top of the trench; and selectively forming a gate metal only on exposed surfaces of the work function metal layer.
  • According to another embodiment, a method of fabricating a fin field effect transistor (finFET) device includes forming a substrate; forming a fin connecting a source region and a drain region over the substrate; forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer; removing the dummy gate structure so as to expose a trench within the insulating layer; conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer; recessing the work function metal layer below a top of the trench; and selectively forming a gate metal only on exposed surfaces of the work function metal layer.
  • Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
  • FIG. 1 is a top-down view of a finFET device fabricated according to an embodiment of the invention;
  • FIG. 2 is a cross-sectional view of a stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 3 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to an embodiment of the invention;
  • FIG. 4 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 5 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 6 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 7 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 8 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 9 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 10 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 11 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 12 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 13 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 14 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 15 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention;
  • FIG. 16 is a cross-sectional view of another stage in the formation of an exemplary finFET device according to an embodiment of the invention;
  • FIG. 17 is a cross-sectional view of the stage in the formation of another exemplary finFET device according to another embodiment of the invention; and
  • FIG. 18 is a cross-sectional view of another stage in the formation of an exemplary finFET according to an embodiment of the invention.
    •  DETAILED DESCRIPTION
  • As noted above, part of the fabrication of an RMG finFET device involves forming a partial recess in the metal gate for formation of a dielectric cap. This partial recessing of the gate metal can present a challenge from the standpoint of the reactive ion etch (RIE) required. In addition, conventional gate metal fill techniques may result in a seam or void within the gate metal layer. Embodiments of the RMG finFET device and process of fabricating the device detailed herein include bottom-up formation through selective metal growth.
  • FIG. 1 is a top-down view of a finFET device 100 fabricated according to an embodiment of the invention. The conducting channel between the source and gate is wrapped in a silicon fin 125 and finFETs are generally known. The description herein focuses on the differences in fabrication of a gate region 101. An inter-level dielectric (ILD) 120 including a dielectric material such as silicon oxide or silicon nitride, for example, forms the trench in which the gate region 101 is formed. Two fins 125 wrapped in silicon, for example, are shown with source 102 and drain 103 sides in the exemplary finFET device 100. In alternate embodiments, one or a different number of fins 125 may be formed. The gate region 101 is shown in the top-down view of FIG. 1. Generally, in both currently used processes and according to embodiments of the invention, the gate region 101 is formed by removing and replacing a dummy gate 140 (FIG. 2) with the gate metal 190 (FIGS. 14, 15). As further detailed below with reference to FIGS. 2 through 18, embodiments of the invention relate to bottom-up formation of the replacement gate 101 through growth of the gate metal 190. Two figures are shown for each stage of the processing to illustrate two different gate widths. The stages shown in subsequent figures are cross sectional views across the gate as indicated by A-A.
  • The cross-sections indicated by A-A and B-B are both detailed in FIG. 1. The cross-section indicated by A-A is through a fin 125. The cross-sectional structure 104 includes a substrate 110 with a silicon layer 130 representing the fin 125 above it. The ILD 120 forms a trench in which the gate region 101 is formed. The cross-section indicated by B-B is through the gate region 101. The cross-sectional structure 105 includes a substrate 110 with ILD 120 formed above and also including the trench in which the gate region 101 is formed. The gate region 101 and its formation are further detailed below. As noted above, FIGS. 2 through 18 show cross-sectional views at A-A.
  • FIG. 2 is a cross-sectional view of a stage 200-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 3 is a cross-sectional view of the stage 200-2 in the formation of another exemplary finFET device according to an embodiment of the invention. The trench 121 is wider in stage 200-2 shown in FIG. 3 than the trench 121 shown in FIG. 2. In both stages 200-1 and 200-2 shown in FIGS. 2 and 3, respectively, a silicon layer 130 indicating the fin 125 is shown as being formed on the substrate 110. Above the fin 125 (silicon layer 130), a trench 121 is formed in the ILD 120. The silicon layer 130 may represent an epitaxial merge of the fins 125 shown in FIG. 1. A dummy gate 140 of a poly-silicon or amorphous-silicon is shown beneath a gate hardmask 150 in the trench 121 of the ILD 120. An oxide layer 145, which may be the same material as the ILD 120 or a different oxide is beneath the dummy gate 140. As shown in FIGS. 2 and 3, the gate hardmask 155 is above the dummy gate 140. The same material as the gate hardmask 155 or a different material may acts as a sidewall spacer 150 between the dummy gate 140 and the ILD 120 based on etching. The material of the gate hardmask 155 may be silicon nitride (SiN). For purposes of explaining the embodiments herein, the stages 200-1 and 200-2 shown in FIGS. 2 and 3 are considered the initial stages in the formation of a finFET device 100, because stages preceding stages 200-1 and 200-2 are the same as those of prior finFET device formation processes.
  • FIG. 4 is a cross-sectional view of another stage 300-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 5 is a cross-sectional view of the stage 300-2 in the formation of another exemplary finFET device according to another embodiment of the invention. As FIGS. 4 and 5 indicate, the oxide layer 145, dummy gate 140, and gate hardmask 155 are pulled to result in the stages 300-1 and 300-2. Specifically, a dry etch is first performed to etch back the hardmask 155 (which may have some effect on the sidewall spacer 150, as well). Then, a wet etch is performed to etch the dummy gate 140 and oxide layer 145. The sidewall spacer 150, which may be somewhat shortened by the dry etch process, is left as shown in FIGS. 4 and 5.
  • FIG. 6 is a cross-sectional view of another stage 400-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 7 is a cross-sectional view of the stage 400-2 in the formation of another exemplary finFET device according to another embodiment of the invention. As FIGS. 6 and 7 indicate, a high dielectric constant (high-k) dielectric layer 160 and a work function metal 170 are deposited conformally along the gate hardmask 150 and on a surface of the silicon layer 130. A blanket conformal deposition is followed by CMP down to the ILD 120. Exemplary materials used for the dielectric layer 160 include hafnium oxide (HfO2), aluminum oxide (Al2O3), a hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), or a hafnium zirconate (HfZrOx). The work function metal 170 may be tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum carbide (TiAlC), or TiC, for example.
  • FIG. 8 is a cross-sectional view of another stage 500-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 9 is a cross-sectional view of the stage 500-2 in the formation of another exemplary finFET device according to another embodiment of the invention. An organic planarizing layer (OPL) 180 is deposited and etched back below the top of the trench 121, as shown in FIGS. 8 and 9, so that the OPL 180 is recessed in the trench coated with the work function metal 170. The OPL 180 is a photoresist-like material used to reduce the topography. An organic dielectric layer (ODL) may be used as an OPL 180. FIG. 10 is a cross-sectional view of another stage 600-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 11 is a cross-sectional view of the stage 600-2 in the formation of another exemplary finFET device according to another embodiment of the invention. The work function metal 170 is etched to be partially recessed to the level of the recessed OPL 180. FIG. 12 is a cross-sectional view of another stage 700-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 13 is a cross-sectional view of the stage 700-2 in the formation of another exemplary finFET device according to another embodiment of the invention. The OPL 180 is stripped leaving the recessed work function metal 170 exposed. The OPL 180 may be stripped with a gas including carbon dioxide, for example.
  • FIG. 14 is a cross-sectional view of another stage 800-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 15 is a cross-sectional view of the stage 800-2 in the formation of another exemplary finFET device according to another embodiment of the invention. A gate metal 190 is grown via selective metal growth on the work function metal 170 surface. FIGS. 14 and 15 illustrate a key difference in the embodiments described herein as compared with current processes for forming the replacement gate. The gate metal 190 is grown via selective metal growth such that deposition and etching via RIE is not required according to the embodiments. That is, the work function metal 170 acts as a seeding layer that the gate metal 190 cannot grow without, such that the gate metal 190 grows only on the surfaces of the workfunction metal 170. Thus, due to recessing the work function metal 170 at stages 600-1 and 600-2, the gate metal 190 can be grown to be recessed, as well, without requiring any etching. The gate metal 190 may be tungsten (W), aluminum (Al), cobalt (Co), phosphorous (P), or boron (B), for example. The gate metal 190 may instead be W, P, or B doped with Co, for example. As a comparison of stages 800-1 and 800-2 indicates, when the trench 121 is sufficiently narrow (as in stage 800-1), growth of the gate metal 190 will result in a continuous fill. That is, the growth of the gate metal 190 at the two sides of the trench 121 in the cross-sectional view shown in FIG. 14 will be close enough to form a continuous gate metal 190 layer as shown. To the contrary, the growth of the gate metal 190 at the two sides of the trench 121 in the cross-sectional view shown in FIG. 15 will be sufficiently separated such that a gap 191 will result.
  • FIG. 16 is a cross-sectional view of another stage 900-1 in the formation of an exemplary finFET device according to an embodiment of the invention. FIG. 17 is a cross-sectional view of the stage 900-2 in the formation of another exemplary finFET device according to another embodiment of the invention. A dielectric cap 195 is formed over the gate metal 190 in a damascene process. The dielectric cap 195 may be a silicon nitride (SiN) material. The SiN material may be formed at a temperature below 500 degrees Celsius. As FIG. 17 shows, the dielectric cap 195 fills the gap 191, as well. As noted above, no such gap 191 is present in the embodiment shown in FIGS. 14 and 16 such that the dielectric cap 195 is formed above a continuous gate metal 190 layer. FIG. 18 is a cross-sectional view of another stage 1000 in the formation of an exemplary finFET 100 according to an embodiment of the invention. This stage 1000 applies to the finFET device with the relatively wider gate 101 (and, thus, the gap 191). The dielectric cap 195 is removed and a tungsten (W) 197 refill is performed as shown. This W 197 fill provides the necessary gate conductivity that cannot be achieved with the gap 191.
  • The processes detailed above not only address the challenges associated with obtaining a recessed gate metal but also prevent voids in the gate metal region. That is, conventional gate metal fill techniques are susceptible to developing a seam or void in the gate metal fill. Based on the selective growth described above (and the W fill according to some embodiments), a continuous gate metal layer without any seams or voids is obtained.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
  • The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
  • The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
  • While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
  • The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (16)

1. A method of fabricating a replacement metal gate in a transistor device, the method comprising:
forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer;
removing the dummy gate structure so as to expose a trench within the insulating layer;
conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a top surface of the insulating layer;
recessing the work function metal layer below a top of the trench; and
selectively growing a gate metal only on exposed surfaces of the work function metal layer;
forming a dielectric cap over the gate metal to fill the trench; and
removing the dielectric cap and performing a metal fill of the trench, wherein the removing the dielectric cap and the performing the metal fill is performed when the selectively growing the gate metal results in a gap within the inner wall of the trench.
2. The method according to claim 1, wherein the forming the dummy gate structure includes depositing a dummy gate over an oxide layer in the trench at a depth less than a depth of the trench.
3. The method according to claim 2, wherein the forming the dummy gate structure also includes forming a hardmask over the dummy gate to fill the depth of the trench.
4. The method according to claim 1, further comprising, prior to the selectively growing the gate metal, forming an organic planarizing layer (OPL) in the trench over the work function metal.
5. The method according to claim 4, further comprising etching the OPL to form a recessed OPL with a thickness less than a depth of the trench.
6. The method according to claim 5, further comprising etching the work function metal to the depth of the recessed OPL.
7. The method according to claim 6, further comprising stripping the OPL prior to selectively growing the gate metal.
8-10. (canceled)
11. A finFET device comprising:
a replacement metal gate fabricated according to the method of claim 1; and
source and drain regions with a fin channel region therebetween, the fin channel region extending in an axial direction perpendicular to an axial direction of the replacement metal gate.
12. A method of fabricating a fin field effect transistor (finFET) device, the method comprising:
forming a substrate;
forming a fin connecting a source region and a drain region over the substrate;
forming a dummy gate structure over a substrate, the dummy gate structure surrounded by an insulating layer;
removing the dummy gate structure so as to expose a trench within the insulating layer;
conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a top surface of the insulating layer;
recessing the work function metal layer below a top of the trench;
selectively growing a gate metal only on exposed surfaces of the work function metal layer;
forming a dielectric cap over the gate metal to fill the trench; and
removing the dielectric cap and performing a metal fill of the trench, wherein the removing the dielectric cap and the performing the metal fill is performed when the selectively growing the gate metal results in a gap within the inner wall of the trench.
13. The method according to claim 12, wherein the forming the dummy gate structure includes depositing a dummy gate in the trench at a depth less than a depth of the trench.
14. The method according to claim 13, wherein the forming the dummy gate structure also includes forming a hardmask over the dummy gate to fill the depth of the trench.
15. The method according to claim 12, further comprising, prior to the selectively growing the gate metal, forming an organic planarizing layer (OPL) in the trench over the work function metal.
16. The method according to claim 15, further comprising etching the OPL to form a recessed OPL with a thickness less than a depth of the trench.
17. The method according to claim 16, further comprising etching the work function metal to the depth of the recessed OPL, and stripping the OPL prior to selectively forming the gate metal.
18-20. (canceled)
US14/592,042 2015-01-08 2015-01-08 Bottom-up metal gate formation on replacement metal gate finFET devices Active US9379221B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US14/592,042 US9379221B1 (en) 2015-01-08 2015-01-08 Bottom-up metal gate formation on replacement metal gate finFET devices
GB1706263.9A GB2549621B (en) 2015-01-08 2016-01-04 Bottom-up metal gate formation on replacement metal gate finfet devices
CN201680005203.7A CN107112217B (en) 2015-01-08 2016-01-04 Manufacturing method of replacement metal gate, finFET device and manufacturing method of finFET device
JP2017530173A JP6688301B2 (en) 2015-01-08 2016-01-04 Method of manufacturing a replacement metal gate in a transistor device, fin field effect transistor device and method of manufacturing the same
PCT/IB2016/050022 WO2016110793A1 (en) 2015-01-08 2016-01-04 Bottom-up metal gate formation on replacement metal gate finfet devices
DE112016000182.7T DE112016000182B4 (en) 2015-01-08 2016-01-04 Bottom-up metal gate formation on finfet devices with a replacement metal gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/592,042 US9379221B1 (en) 2015-01-08 2015-01-08 Bottom-up metal gate formation on replacement metal gate finFET devices

Publications (2)

Publication Number Publication Date
US9379221B1 US9379221B1 (en) 2016-06-28
US20160204221A1 true US20160204221A1 (en) 2016-07-14

Family

ID=56136484

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/592,042 Active US9379221B1 (en) 2015-01-08 2015-01-08 Bottom-up metal gate formation on replacement metal gate finFET devices

Country Status (6)

Country Link
US (1) US9379221B1 (en)
JP (1) JP6688301B2 (en)
CN (1) CN107112217B (en)
DE (1) DE112016000182B4 (en)
GB (1) GB2549621B (en)
WO (1) WO2016110793A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170256640A1 (en) * 2015-07-01 2017-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Structure and Method for Forming the Same
US20180175165A1 (en) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Etching Back and Selective Deposition of Metal Gate
US10217839B2 (en) 2017-03-24 2019-02-26 Globalfoundries Inc. Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET
US10263113B2 (en) 2016-08-03 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20220278224A1 (en) * 2016-12-15 2022-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Etching Back and Selective Deposition of Metal Gate
TWI826443B (en) * 2018-08-14 2023-12-21 南韓商三星電子股份有限公司 Semiconductor device
US11862453B2 (en) 2020-08-27 2024-01-02 Marvell Asia Pte, Ltd. Gate stack for metal gate transistor

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10014180B1 (en) 2017-08-21 2018-07-03 Globalfoundries Inc. Tungsten gate and method for forming
US10164053B1 (en) * 2017-08-31 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10204828B1 (en) 2018-02-09 2019-02-12 International Business Machines Corporation Enabling low resistance gates and contacts integrated with bilayer dielectrics
CN110164760B (en) * 2018-02-12 2021-05-04 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
JP7195106B2 (en) * 2018-10-12 2022-12-23 東京エレクトロン株式会社 Film forming method and substrate processing system
US11721695B2 (en) * 2021-07-16 2023-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stacks and methods of fabricating the same in multi-gate field-effect transistors

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5695810A (en) 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6342733B1 (en) 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US6706625B1 (en) 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6975032B2 (en) 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
US6967131B2 (en) 2003-10-29 2005-11-22 International Business Machines Corp. Field effect transistor with electroplated metal gate
US8193641B2 (en) * 2006-05-09 2012-06-05 Intel Corporation Recessed workfunction metal in CMOS transistor gates
US8013401B2 (en) 2007-03-15 2011-09-06 Intel Corporation Selectively depositing aluminum in a replacement metal gate process
US8350335B2 (en) * 2007-04-18 2013-01-08 Sony Corporation Semiconductor device including off-set spacers formed as a portion of the sidewall
US8779530B2 (en) 2009-12-21 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate structure of a field effect transistor
US8088685B2 (en) 2010-02-09 2012-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of bottom-up metal film deposition
US8373239B2 (en) 2010-06-08 2013-02-12 International Business Machines Corporation Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric
DE102010030756B4 (en) 2010-06-30 2013-06-06 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg An exchange gate method for large ε metal gate stacks based on a non-conforming inter-layer dielectric
DE102011005639B4 (en) 2011-03-16 2016-05-25 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Reduce the defect rate during the deposition of a channel semiconductor alloy into an in situ lowered active area
KR101850703B1 (en) * 2011-05-17 2018-04-23 삼성전자 주식회사 Semiconductor device and method for fabricating the device
US8629007B2 (en) 2011-07-14 2014-01-14 International Business Machines Corporation Method of improving replacement metal gate fill
US8557666B2 (en) 2011-09-13 2013-10-15 GlobalFoundries, Inc. Methods for fabricating integrated circuits
US8772168B2 (en) * 2012-01-19 2014-07-08 Globalfoundries Singapore Pte. Ltd. Formation of the dielectric cap layer for a replacement gate structure
KR101929185B1 (en) 2012-05-02 2018-12-17 삼성전자 주식회사 Method for manufacturing semiconductor device
KR101909091B1 (en) 2012-05-11 2018-10-17 삼성전자 주식회사 Semiconductor device and fabricating method thereof
US8679909B2 (en) * 2012-06-08 2014-03-25 Globalfoundries Singapore Pte. Ltd. Recessing and capping of gate structures with varying metal compositions
US8507979B1 (en) * 2012-07-31 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit with metal gate
CN103915386B (en) * 2013-01-08 2017-05-17 中芯国际集成电路制造(上海)有限公司 Cmos transistor and forming method thereof
KR101996244B1 (en) * 2013-06-27 2019-07-05 삼성전자 주식회사 Method for fabricating semiconductor device
US9018711B1 (en) * 2013-10-17 2015-04-28 Globalfoundries Inc. Selective growth of a work-function metal in a replacement metal gate of a semiconductor device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10790394B2 (en) 2015-07-01 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11532748B2 (en) 2015-07-01 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US20170256640A1 (en) * 2015-07-01 2017-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Structure and Method for Forming the Same
US10269963B2 (en) * 2015-07-01 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US10868188B2 (en) 2016-08-03 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
TWI659514B (en) * 2016-08-03 2019-05-11 台灣積體電路製造股份有限公司 Semiconductor device and manufacturing method thereof
US11855217B2 (en) 2016-08-03 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer
US10516052B2 (en) 2016-08-03 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10263113B2 (en) 2016-08-03 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10879370B2 (en) * 2016-12-15 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Etching back and selective deposition of metal gate
US20180175165A1 (en) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Etching Back and Selective Deposition of Metal Gate
US20220278224A1 (en) * 2016-12-15 2022-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Etching Back and Selective Deposition of Metal Gate
US11380774B2 (en) * 2016-12-15 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Etching back and selective deposition of metal gate
TWI668744B (en) * 2016-12-15 2019-08-11 台灣積體電路製造股份有限公司 Semiconductor devices and methods for forming the same
US10217839B2 (en) 2017-03-24 2019-02-26 Globalfoundries Inc. Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET
TWI826443B (en) * 2018-08-14 2023-12-21 南韓商三星電子股份有限公司 Semiconductor device
US11862453B2 (en) 2020-08-27 2024-01-02 Marvell Asia Pte, Ltd. Gate stack for metal gate transistor

Also Published As

Publication number Publication date
JP2018506170A (en) 2018-03-01
GB201706263D0 (en) 2017-06-07
CN107112217A (en) 2017-08-29
GB2549621A (en) 2017-10-25
DE112016000182B4 (en) 2023-10-05
JP6688301B2 (en) 2020-04-28
DE112016000182T5 (en) 2017-08-24
GB2549621B (en) 2018-06-13
CN107112217B (en) 2020-07-31
US9379221B1 (en) 2016-06-28
WO2016110793A1 (en) 2016-07-14

Similar Documents

Publication Publication Date Title
US9379221B1 (en) Bottom-up metal gate formation on replacement metal gate finFET devices
US10121786B2 (en) FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers
US10347719B2 (en) Nanosheet transistors on bulk material
US9653573B2 (en) Replacement metal gate including dielectric gate material
US9490129B2 (en) Integrated circuits having improved gate structures and methods for fabricating same
US9391075B2 (en) Integrated circuit and method for fabricating the same having a replacement gate structure
US9466494B2 (en) Selective growth for high-aspect ration metal fill
US9431514B2 (en) FinFET device having a high germanium content fin structure and method of making same
CN109727916A (en) The manufacturing method of semiconductor device
US9660050B1 (en) Replacement low-k spacer
US8936979B2 (en) Semiconductor devices having improved gate height uniformity and methods for fabricating same
US9147696B2 (en) Devices and methods of forming finFETs with self aligned fin formation
US9536985B2 (en) Epitaxial growth of material on source/drain regions of FinFET structure
US20160172380A1 (en) Modified fin cut after epitaxial growth
US10529862B2 (en) Semiconductor device and method of forming semiconductor fin thereof
US10153341B2 (en) Method of forming internal spacer for nanowires
US11569361B2 (en) Nanosheet transistors with wrap around contact
US10504998B2 (en) Semiconductor structure and method of forming the same
US20190198399A1 (en) Vertical FET with Various Gate Lengths by an Oxidation Process

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HE, HONG;LI, JUNTAO;WANG, JUNLI;AND OTHERS;SIGNING DATES FROM 20150105 TO 20150107;REEL/FRAME:034662/0629

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY