TWI822197B - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure includes a circuit substrate, a first circuit layer and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate, and is electrically connected with the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.

Description

Circuit board structure and manufacturing method

The present invention relates to a substrate structure and a manufacturing method thereof, and in particular, to a circuit board structure and a manufacturing method thereof.

High-density interconnect (HDI) has the advantages of small size, fast speed and high frequency. It is a major component of personal computers, portable computers, mobile phones and personal digital assistants. Generally speaking, the connection between thin-film redistribution layers and high-density connection boards requires the formation of a transfer layer before forming a circuit layer with fine line width. Because a transfer layer is required, the process complexity is increased, and a transmission path is added to the signal transmission, thereby reducing signal integrity. Furthermore, the uppermost layer of high-density connection boards is mostly produced using the subtractive method, and the circuit process limit of the transfer layer is that the ratio of line width/copper thickness is 1/1.25. In today's market trend of pursuing thin line width, when the required line width is limited to 10 microns, the copper thickness can only be 12.5 microns. When using the multi-layer organic (MLO) board at the test end of the probe card, the Because the cross-sectional area of the circuit is too small and the resistance is too large, there is a risk of circuit fusion. In addition, if it is formed by soldering and filling colloid If a connection layer is formed to connect the redistribution layer (RLD) and the high-density connection board, there will be a problem of poor coplanarity after joining.

The present invention provides a circuit board structure that can shorten the signal transmission path and have better signal integrity.

The present invention provides a method for manufacturing a circuit board structure, which is used to manufacture the above-mentioned circuit board structure.

The circuit board structure of the present invention includes a circuit substrate, a first circuit layer and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is flush with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and is electrically connected to the conductive structure. The line width of the first circuit layer is less than or equal to 1/4 of the line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and is electrically connected to the first circuit layer.

In an embodiment of the present invention, the above-mentioned circuit substrate includes a high-density interconnection substrate.

In an embodiment of the present invention, the above-mentioned first circuit layer includes at least one circuit. The line width/thickness ratio of the line is greater than or equal to 1/2.5.

In an embodiment of the present invention, the line width and line spacing of the above-mentioned lines are respectively less than or equal to 10 microns.

In an embodiment of the present invention, the above-mentioned first circuit layer includes at least one Pad. The diameter of the pad is less than or equal to 1/5 of the diameter of the conductive structure.

The manufacturing method of the circuit board structure of the present invention includes the following steps. A circuit substrate is provided. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is flush with the surface. Form a first circuit layer on the surface of the circuit substrate. The first circuit layer directly contacts the surface and is electrically connected to the conductive structure. The line width of the first circuit layer is less than or equal to 1/4 of the line width of the patterned circuit layer. A second circuit layer is formed on the first circuit layer, wherein the second circuit layer directly contacts the first circuit layer and is electrically connected to the first circuit layer.

In an embodiment of the present invention, the step of forming the first circuit layer on the surface of the circuit substrate includes: forming a sub-layer on the surface of the circuit substrate. Form a patterned photoresist layer on the seed layer. The patterned photoresist layer is used as an electroplating mask, and a conductive material is electroplated on the seed layer. The patterned photoresist layer and part of the seed layer underneath are removed to form a first circuit layer.

In an embodiment of the present invention, when the circuit substrate is provided, a copper foil layer covers the surface and the conductive structure. The step of forming the first circuit layer on the surface of the circuit substrate includes: forming a patterned photoresist layer on the surface of the circuit substrate. on the copper foil layer. The etching exposes the copper foil layer outside the patterned photoresist layer, thereby exposing part of the surface of the circuit substrate. The patterned photoresist layer is removed to form a first circuit layer on the surface of the circuit substrate.

In one embodiment of the present invention, when the circuit substrate is provided, a copper foil layer covers the surface and the conductive structure. The step of forming the first circuit layer on the surface of the circuit substrate includes performing a laser process on the copper foil layer. , and the first circuit layer is formed on the electrical on the surface of the road base plate.

In an embodiment of the present invention, the above-mentioned circuit substrate includes a high-density interconnection substrate.

Based on the above, in the design of the circuit board structure of the present invention, the first circuit layer is directly disposed on the surface of the circuit substrate and is electrically connected to the conductive structure of the circuit substrate, wherein the line width of the first circuit layer is less than or equal to 1/4 of the line width of the patterned circuit layer of the circuit substrate. That is to say, the circuit board structure of the present invention does not need to provide a transfer layer in the prior art, but can directly form a first circuit layer with a thin line width on the circuit substrate, which can effectively shorten the signal transmission path and has better Signal integrity.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100a, 100b: Circuit board structure

110, 110’: circuit substrate

111:Core layer

112:Conductive via

113: Patterned circuit layer

114, 115: Conductive structure

115a: Upper surface

116:Dielectric layer

117: Solder mask

118: First metal layer

119: Second metal layer

120a, 120b: first line layer

122, 142, 162, S1, S2, S3: seed layer

124:Line

125:pad

130, 150: Insulating layer

131, 151: Surface

140: Second line layer

144, 164: Conductive pattern

145: The third line layer

160: The fourth line layer

C1, C2, C3: conductive materials

D1, D2: diameter

L:Laser light

L1, L2: line width

M, M’: Copper foil layer

O1, O2, O3: opening

P: Photoresist layer

P1, P2, P3, P4: patterned photoresist layer

T: Surface

1A is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention.

FIG. 1B is a partial top view of the patterned circuit layer and the circuits of the first circuit layer of the circuit board structure of FIG. 1A .

FIG. 1C is a partial top view of the conductive structure of the circuit substrate and the pads of the first circuit layer of the circuit board structure of FIG. 1A .

FIGS. 2A to 2Q are schematic cross-sectional views of the manufacturing method of the circuit board structure of FIG. 1 .

FIG. 3 is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention.

4A to 4D are partial cross-sectional schematic diagrams of a manufacturing method of the circuit board structure of FIG. 3 .

FIG. 5 is a partial cross-sectional schematic diagram of another manufacturing method of the circuit board structure of FIG. 3 .

1A is a schematic cross-sectional view of a circuit board structure according to an embodiment of the present invention. FIG. 1B is a partial top view of the patterned circuit layer and the circuits of the first circuit layer of the circuit board structure of FIG. 1A . FIG. 1C is a partial top view of the conductive structure of the circuit substrate and the pads of the first circuit layer of the circuit board structure of FIG. 1A .

Please refer to FIG. 1A first. In this embodiment, the circuit board structure 100a includes a circuit substrate 110, a first circuit layer 120a and a second circuit layer 140. The circuit substrate 110 has a surface T and includes at least one conductive structure 115 (a plurality is schematically shown) and at least one patterned circuit layer 113 (a plurality is schematically shown). The conductive structure 115 is electrically connected to the patterned circuit layer 113, and an upper surface 115a of the conductive structure 115 is flush with the surface T of the circuit substrate 110. The first circuit layer 120a is directly disposed on the surface T of the circuit substrate 110 and is electrically connected to the conductive structure 115. The line width of the first circuit layer 120a is less than or equal to 1/4 of the line width of the patterned circuit layer 113. The second circuit layer 140 is directly disposed on the first circuit layer 120a and connected with the first circuit layer 120a. Electrical connection.

In this embodiment, the circuit substrate 110 is, for example, a high-density interconnection substrate. In detail, the circuit substrate 110 includes a core layer 111, a plurality of conductive vias 112 that penetrate the core layer 111 and are separated from each other, and patterned circuit layers that connect opposite ends of the conductive vias 112 and are alternately arranged with the multi-layer dielectric layers 116. 113 and a conductive structure 114 connecting two adjacent patterned circuit layers. The patterned circuit layer 113, the dielectric layer 116 and the conductive structure 114 can define a build-up circuit structure, which are respectively located on opposite sides of the core layer 111. That is to say, the circuit substrate 110 is a high-density double-sided circuit board. One side of the core layer 111 includes a conductive structure 115, wherein the conductive structure 115 is electrically connected to the patterned circuit layer 113, and the surface 115a of the conductive structure 115 is flush with the surface T of the circuit substrate 110. Here, the surface T of the circuit substrate 110 and the surface 115a of the conductive structure 115 can define a connection surface for structural and electrical connection with the first circuit layer 120a. The other side of the core layer 111 also includes a solder mask layer 117 and a surface treatment layer, where the solder mask layer 117 covers the surface of the dielectric layer 116 and exposes the patterned circuit layer 113, and the surface treatment layer is configured to be soldered The patterned circuit layer 113 is exposed by the layer 117 . Here, the surface treatment layer includes a first metal layer 118 and a second metal layer 119 disposed on the first metal layer 118. The material of the first metal layer 118 and the second metal layer 119 is, for example, a nickel layer, gold layer, etc. layer, silver layer, nickel-palladium-gold layer or other suitable metal or alloy to protect the patterned circuit layer 113 from oxidation.

Please refer to FIGS. 1A, 1B and 1C at the same time. In this embodiment, the first circuit layer 120a includes at least one circuit 124. In particular, the line width/thickness ratio of the circuit 124 is, for example, greater than or equal to 1/2.5, meaning that That is, it has a higher aspect ratio. Yu Yi In the embodiment, the line width of the line 124 is L1, and the line width of the patterned line layer 113 is L2. The line width L1 and line spacing of the line 124 are, for example, less than or equal to 10 microns respectively, and the lines of the patterned line layer 113 are The width L2 and the line spacing are, for example, 40 microns respectively. Furthermore, the first circuit layer 120a of this embodiment further includes at least one pad 125. In particular, the diameter D1 of the pad 125 is, for example, less than or equal to 1/5 of the diameter D2 of the conductive structure 115. Here, the diameter D1 of the pad 125 is, for example, less than 50 microns, which can increase the wiring area of the first circuit layer 120a. Due to the manufacturing process, the first circuit layer 120a of this embodiment also includes a seed layer 122, where the seed layer 122 is located below the circuit 124 and the pad 125, and is directly connected to and disposed corresponding to the circuit 124 and the pad 125.

In addition, please refer to FIG. 1A again. The circuit board structure 100a of this embodiment may also include an insulating layer 130, an insulating layer 150, a third circuit layer 145 and a fourth circuit layer 160. The insulating layer 130 covers the first circuit layer 120a, and the second circuit layer 140 is buried in the insulating layer 150 and is electrically connected to the first circuit layer 120a. The second circuit layer 140 includes a conductive pattern 144 and a seed layer 142 located under the conductive pattern 144 . The third circuit layer 145 and the second circuit layer 140 are electrically connected. The third circuit layer 145 and the second circuit layer 140 are formed by the same process, so they are seamlessly connected to each other. The insulating layer 150 covers the third circuit layer 145, and the fourth circuit layer 160 is disposed on the insulating layer 150 and is electrically connected to the third circuit layer 145 through the insulating layer 150. The fourth circuit layer 160 includes a conductive pattern 164 and a seed layer 162 located under the conductive pattern 164 .

The circuit board structure 100a of this embodiment has a four-layer circuit structure on the circuit substrate 110. Compared with the prior art which has a five-layer circuit structure due to an additional transfer layer, the circuit board structure 100a of this embodiment can reduce the number of layers to effectively shorten the message signal transmission path and has better signal integrity. Furthermore, the first circuit layer 120a is directly disposed on the surface T of the circuit substrate 110 and is electrically connected to the conductive structure 115 of the circuit substrate 110. The line width of the first circuit layer 120a is less than or equal to the pattern of the circuit substrate 110. 1/4 of the line width of the line layer 113. That is to say, the circuit board structure 100a of this embodiment can directly form the first circuit layer 120a with a thin line width on the circuit substrate 110, which can increase the wiring area and reduce the number of wiring layers. In addition, since this embodiment does not use the connection layer formed by solder and filling colloid in the prior art, the circuit board structure 100a of this embodiment can have better coplanarity.

FIGS. 2A to 2Q are schematic cross-sectional views of the manufacturing method of the circuit board structure of FIG. 1A . In terms of the manufacturing process, first, please refer to FIG. 2A to provide a circuit substrate 110', where the circuit substrate 110' is, for example, a high-density interconnection substrate. The circuit substrate 110' includes a core layer 111, a plurality of conductive vias 112 that penetrate the core layer 111 and are separated from each other, a patterned circuit layer 113 that connects opposite ends of the conductive vias 112 and is alternately arranged with the multi-layer dielectric layer 116, and connections The conductive structures 114 of two adjacent patterned circuit layers. The patterned circuit layer 113, the dielectric layer 116 and the conductive structure 114 can define a build-up circuit structure, which are respectively located on opposite sides of the core layer 111. The circuit substrate 110 also includes a copper foil layer M on two opposite sides, wherein the copper foil layer M is disposed on the outermost dielectric layer 116 and covers the outermost conductive structures 114 and 115 .

Next, please refer to FIG. 2A and FIG. 2B simultaneously to perform an etching process to completely remove the copper foil layer M above the core layer 111 and expose the outermost dielectric layer 116 and the outermost conductive structure 115 . The surface 115a of the conductive structure 115 is flush with the surface T, where the surface T and the surface 115a of the conductive structure 115 can define a connection surface. Here, the connection surface may be the outermost surface of the circuit substrate 110 or called the upper surface. Next, a photolithography process is performed on the copper foil layer M below the core layer 111 to form the outermost patterned circuit layer 113 below. Next, a solder resist layer 117 and a surface treatment layer are formed on the outermost patterned circuit layer 113 below the core layer 111 . The solder resist layer 117 covers the surface of the dielectric layer 116 and exposes the patterned circuit layer 113 , and the surface treatment layer is disposed on the patterned circuit layer 113 exposed by the solder resist layer 117 . Here, the surface treatment layer includes a first metal layer 118 and a second metal layer 119 disposed on the first metal layer 118. The material of the first metal layer 118 and the second metal layer 119 is, for example, a nickel layer, gold layer, etc. layer, silver layer, nickel-palladium-gold layer or other suitable metal or alloy to protect the patterned circuit layer 113 from oxidation. Here, the production of the ball grid array package (Ball Grid Array) surface has been completed, where the ball grid array package surface can be regarded as the outermost surface of the circuit substrate 110 or called the lower surface. It should be noted that this embodiment does not limit the order of manufacturing the connection surface and the ball grid array packaging surface. In one embodiment, the ball grid array packaging surface can also be fabricated first, and then the connection surface can be fabricated, which still falls within the scope of protection of the present invention. At this point, the production of the circuit substrate 110 has been completed.

Next, please refer to FIG. 2C , the seed layer S1 is sputtered on the surface T of the circuit substrate 110 to cover the surface T of the circuit substrate 110 and the surface 115 a of the conductive structure 115 . At this time, the seed layer S1 is formed on the connection surface.

Next, please refer to Figure 2D. A patterned photoresist layer P1 is formed on the seed layer S1 by coating wet film photoresist and yellow light lithography photoresist. The patterned photoresist layer P1 has a plurality of openings O1, and the opening O1 is exposed. Extract part of the seed layer S1. Here, pattern The patterned photoresist layer P1 is a wet film photoresist, which is formed on the seed layer S1 by coating, and is then photolithographically etched to form a patterned photoresist layer P1.

Next, please refer to FIG. 2E, using the patterned photoresist layer P1 as an electroplating mask, a conductive material C1 is electroplated on the seed layer S1, where the conductive material C1 fills the opening O1 and connects the seed layer S1.

Next, please refer to FIG. 2E and FIG. 2F simultaneously to remove the patterned photoresist layer P1 and part of the seed layer S1 thereunder to form the first circuit layer 120 a on the surface T of the circuit substrate 110 . At this time, the surface T of the circuit substrate 110 is also exposed, and the first circuit layer 120a directly contacts the surface T and is structurally and electrically connected to the conductive structure 115 . Preferably, the line width L1 of the first circuit layer 120a (see FIG. 1B) is less than or equal to 1/4 of the line width L2 of the patterned circuit layer 113 (see FIG. 1B).

Next, please refer to FIG. 2G , an insulating layer 130 is formed by coating to cover the first circuit layer 120 a, the surface T of the circuit substrate 110 and the surface 115 a of the conductive structure 115 .

Next, please refer to FIG. 2H. The insulating layer 130 is lithographed with a yellow light to form a blind hole 135 on the insulating layer 130. The blind hole 135 exposes part of the first circuit layer 120a.

Next, please refer to FIG. 2I , a seed layer S2 is sputtered on the insulating layer 130 , where the seed layer S2 covers the surface of the insulating layer 130 and the inner wall of the blind hole 135 .

Next, please refer to Figure 2J. A photoresist layer is coated, and the photoresist layer is lithographed with yellow light to form a patterned photoresist layer P2 on the seed layer S2. The patterned photoresist layer P2 has a plurality of openings O2, among which the openings O2 Part of the seed layer S2 is exposed.

Next, please refer to Figure 2K to use the patterned photoresist layer P2 as the electroplating mask. A conductive material C2 is electroplated on the seed layer S2, wherein the conductive material C2 fills the opening O2 and connects the seed layer S2.

Next, please refer to FIG. 2K and FIG. 2L at the same time, remove the patterned photoresist layer P2 and part of the seed layer S2 thereunder, and form the second circuit layer 140 in the blind hole 135 of the insulating layer 130 and form the third circuit layer. 145 on the surface 131 of the insulating layer 130 . At this time, the second circuit layer 140 is formed on the first circuit layer 120a, where the second circuit layer 140 directly contacts the first circuit layer 120a and is electrically connected to the first circuit layer 120a.

Next, please refer to FIG. 2M , an insulating layer 150 is formed by coating to cover the third circuit layer 145 . The insulating layer 150 is lithographed using yellow light to form a blind hole 155 , wherein the blind hole 155 exposes a portion of the third circuit layer 145 .

Next, please refer to FIG. 2N , a seed layer S3 is sputtered on the insulating layer 150 , where the seed layer S3 covers the surface of the insulating layer 150 and the inner wall of the blind hole 155 .

Next, please refer to FIG. 2O, a photoresist layer is coated, and the photoresist layer is lithographed with yellow light to form a patterned photoresist layer P3 on the seed layer S3. The patterned photoresist layer P3 has a plurality of openings O3, and the opening O3 Part of the seed layer S3 is exposed.

After that, please refer to FIG. 2P, using the patterned photoresist layer P3 as an electroplating mask, a conductive material C3 is electroplated on the seed layer S3, where the conductive material C3 fills the opening O3 and connects the seed layer S3.

Finally, please refer to FIG. 2P and FIG. 2Q at the same time, remove the patterned photoresist layer P3 and part of the seed layer S3 thereunder, and form the fourth circuit layer 160 including the conductive pattern 164 and the underlying seed layer 162 on the insulating layer 150 Blind hole 155 (please see Figure 2M) inside and on the surface 151 of the insulating layer 150 . At this point, the fabrication of the circuit board structure 100a has been completed.

Since the first circuit layer 120a can be directly formed on the surface T of the circuit substrate 110, the manufacturing method of the circuit board structure 100a of this embodiment can reduce the number of process layers and manufacturing processes, increase the wiring area and improve production efficiency, and The advantage of reducing the signal transmission path and improving signal integrity.

It must be noted here that the following embodiments follow the component numbers and part of the content of the previous embodiments, where the same numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be repeated in the following embodiments.

FIG. 3 is a schematic cross-sectional view of a circuit board structure according to another embodiment of the present invention. Please refer to FIG. 1A and FIG. 3 at the same time. The circuit board structure 100b of this embodiment is similar to the circuit board structure 100a of FIG. 1A. The difference between the two is that the first circuit layer 120b of this embodiment is a single-layer structure, and its material is such as It is copper foil, but it is not limited to this.

4A to 4D are partial cross-sectional schematic diagrams of a manufacturing method of the circuit board structure of FIG. 3 . In terms of the manufacturing process, after the steps in Figure 2A, please refer to Figure 4A. You can optionally complete the production of the ball grid array packaging surface below the core layer 111 first, and then thin the copper foil layer M above the core layer 111. procedure to form the copper foil layer M'. Next, please refer to FIG. 4B to form a photoresist layer P on the copper foil layer M' by coating. Here, the photoresist layer P is a wet film photoresist, which is suitable for making thin circuits and has better resolution. Next, please refer to FIG. 4C. The photoresist layer P is lithographed with yellow light to form a patterned photoresist layer P4 on the copper foil layer M'. After that, please refer to both Figure 4C and Figure 4D, etching the copper foil layer M′ exposed outside the patterned photoresist layer P4 to expose part of the surface T of the circuit substrate 110. Then, the patterned photoresist layer P4 is removed, and the first circuit layer 120b is formed on the surface T of the circuit substrate 110 . Finally, by continuing the steps of FIG. 2G to FIG. 2Q , the circuit board structure 100b of FIG. 3 can be completed. In short, in this embodiment, the first circuit layer 120b is formed by etching the copper foil layer M' on the circuit substrate 110'.

FIG. 5 is a partial cross-sectional schematic diagram of another manufacturing method of the circuit board structure of FIG. 3 . In terms of the manufacturing process, after the steps of Figure 4A, please refer to Figure 5 to perform a laser process on the copper foil layer M', using laser light L to laser the copper foil layer M' to form the first circuit layer 120b on the circuit substrate 110 on the surface T. After that, finally, by continuing the steps of FIG. 2G to FIG. 2Q , the circuit board structure 100b of FIG. 3 can be completed. In short, in this embodiment, the first circuit layer 120b is formed by laser engraving the copper foil layer M' on the circuit substrate 110'.

To sum up, in the design of the circuit board structure of the present invention, the first circuit layer is directly disposed on the surface of the circuit substrate and is electrically connected to the conductive structure of the circuit substrate, wherein the line width of the first circuit layer is less than Or equal to 1/4 of the line width of the patterned circuit layer of the circuit substrate. That is to say, the circuit board structure of the present invention does not need to provide a transfer layer in the prior art, but can directly form a first circuit layer with a thin line width on the circuit substrate, which can effectively shorten the signal transmission path and has better Signal integrity.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, Protection scope of the invention The scope of the patent application shall be determined by the attached patent application.

100a: Circuit board structure

110:Circuit substrate

111:Core layer

112:Conductive via

113: Patterned circuit layer

114, 115: Conductive structure

115a: Upper surface

116:Dielectric layer

117: Solder mask

118: First metal layer

119: Second metal layer

120a: First line layer

122, 142, 162: seed layer

124:Line

125:pad

130, 150: Insulating layer

140: Second line layer

144, 164: Conductive pattern

145: The third line layer

160: The fourth line layer

T: Surface

Claims (10)

A circuit board structure includes: a circuit substrate having a surface and including at least one conductive structure and at least one patterned circuit layer, wherein the at least one conductive structure is electrically connected to the at least one patterned circuit layer, and the at least one An upper surface of the conductive structure is flush with the surface; a first circuit layer is directly disposed on the surface of the circuit substrate and is electrically connected to the at least one conductive structure, wherein the line width of the first circuit layer is less than Or equal to 1/4 of the line width of the at least one patterned circuit layer; and a second circuit layer directly disposed on the first circuit layer and electrically connected to the first circuit layer. The circuit board structure of claim 1, wherein the circuit substrate includes a high-density interconnection substrate. The circuit board structure of claim 1, wherein the first circuit layer includes at least one circuit, and the line width/thickness ratio of the at least one circuit is greater than or equal to 1/2.5. The circuit board structure according to claim 3, wherein the line width and line spacing of the at least one line are respectively less than or equal to 10 microns. The circuit board structure of claim 1, wherein the first circuit layer includes at least one pad, and the diameter of the at least one pad is less than or equal to 1/5 of the diameter of the at least one conductive structure. A method for manufacturing a circuit board structure, including: providing a circuit substrate having a surface and including at least one conductive structure and at least one patterned circuit layer, wherein the at least one conductive structure is electrically connected to the at least one patterned circuit layer, and an upper surface of the at least one conductive structure is flush with the surface; forming a first circuit layer on On the surface of the circuit substrate, wherein the first circuit layer directly contacts the surface and is electrically connected to the at least one conductive structure, the line width of the first circuit layer is less than or equal to the line width of the at least one patterned circuit layer 1/4; and forming a second circuit layer on the first circuit layer, wherein the second circuit layer directly contacts the first circuit layer and is electrically connected to the first circuit layer. The manufacturing method of a circuit board structure as claimed in claim 6, wherein the step of forming the first circuit layer on the surface of the circuit substrate includes: forming a sub-layer on the surface of the circuit substrate; forming a pattern Put a photoresist layer on the seed layer; use the patterned photoresist layer as an electroplating mask to electroplating a conductive material on the seed layer; and remove the patterned photoresist layer and the part of the seed layer underneath, The first circuit layer is formed. The manufacturing method of a circuit board structure as claimed in claim 6, wherein when the circuit substrate is provided, a copper foil layer covers the surface and the at least one conductive structure to form the first circuit layer on the surface of the circuit substrate. The above steps include: forming a patterned photoresist layer on the copper foil layer; etching the copper foil layer exposed outside the patterned photoresist layer to expose part of the surface of the circuit substrate; and The patterned photoresist layer is removed to form the first circuit layer on the surface of the circuit substrate. The manufacturing method of a circuit board structure as claimed in claim 6, wherein when the circuit substrate is provided, a copper foil layer covers the surface and the at least one conductive structure to form the first circuit layer on the surface of the circuit substrate. The above step includes: performing a laser process on the copper foil layer to form the first circuit layer on the surface of the circuit substrate. The method of manufacturing a circuit board structure as claimed in claim 6, wherein the circuit substrate includes a high-density interconnection substrate.

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