TWI818091B - Wafer processing methods - Google Patents

Wafer processing methods Download PDF

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TWI818091B
TWI818091B TW108135500A TW108135500A TWI818091B TW I818091 B TWI818091 B TW I818091B TW 108135500 A TW108135500 A TW 108135500A TW 108135500 A TW108135500 A TW 108135500A TW I818091 B TWI818091 B TW I818091B
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wafer
grinding
polishing
processing method
back side
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TW202015121A (en
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白濱智宏
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日商迪思科股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation

Abstract

[課題]提供一種儘管抑制所需工時的增加仍然可以賦與去疵能力之晶圓的加工方法。 [解決手段]一種晶圓的加工方法，為薄化晶圓的加工方法，並具備以下步驟：保護構件貼附步驟，在晶圓的正面側貼附保護構件；磨削步驟，以工作夾台的保持面保持晶圓的保護構件側，且以磨削磨石來磨削晶圓的背面側而進行薄化，其中前述磨削磨石是以黏結材固定有磨粒之磨削磨石；以及研磨步驟，在磨削步驟之後，一邊對晶圓的背面側供給研磨漿料一邊按壓旋轉的研磨墊，以將晶圓的背面側研磨到成為稍微殘留經磨削而形成之磨削應變層的狀態，來生成去疵層。[Problem] To provide a wafer processing method that can provide defect removal capabilities while suppressing an increase in required man-hours. [Solution] A wafer processing method, which is a processing method for thinning the wafer, and has the following steps: a protective member attaching step, attaching a protective member to the front side of the wafer; a grinding step, using a work chuck The holding surface holds the protective component side of the wafer, and uses a grinding stone to grind the back side of the wafer to thin it, wherein the aforementioned grinding stone is a grinding stone with abrasive grains fixed by a bonding material; and a polishing step. After the grinding step, the rotating polishing pad is pressed while supplying polishing slurry to the back side of the wafer to grind the back side of the wafer until a grinding strained layer formed by grinding is slightly left. state to generate the defect removal layer.

Description

晶圓的加工方法Wafer processing methods

發明領域 本發明是關於一種晶圓的加工方法，特別是有關於薄化加工。Field of invention The present invention relates to a wafer processing method, in particular to thinning processing.

發明背景 半導體元件已伴隨於電子機器的輕薄短小化，而經常地被要求做得較薄且較小。例如，記憶體元件是積層大量做得較薄的元件晶片，而在不增大尺寸的情形下實現高性能化。雖然在積層大量元件晶片時，必須使各元件晶片的抗折強度提升，但為了提升較薄的元件晶片之抗折強度，藉由研磨來去除由經磨削之晶圓的磨削所造成的應變層之加工技術已有進展。Background of the invention Semiconductor components are often required to be made thinner and smaller as electronic devices become lighter, thinner and smaller. For example, memory devices stack a large number of thin device wafers to achieve high performance without increasing the size. When stacking a large number of device wafers, it is necessary to increase the flexural strength of each device wafer. However, in order to increase the flexural strength of thin device wafers, grinding is used to remove the flexural strength of the ground wafers. The processing technology of strained layers has progressed.

然而，藉由研磨來去除由磨削所造成的應變層之加工技術，伴隨於應變層之去除，使元件晶片的去疵能力消失並產生有元件之由重金屬污染所造成的特性不良之新的問題。於是，已構思有各種對研磨而去除應變層之面施行加工到具有去疵性能之程度的加工技術(參照例如專利文獻1及專利文獻2)。 先前技術文獻 專利文獻However, the processing technology of removing the strained layer caused by grinding through grinding, along with the removal of the strained layer, makes the defect removal ability of the component chip disappear and produces new components with poor characteristics caused by heavy metal contamination. problem. Therefore, various processing techniques have been conceived to process the surface from which the strain layer has been removed by grinding to the extent that it has defect removal performance (see, for example, Patent Document 1 and Patent Document 2). Prior technical literature patent documents

專利文獻1：日本專利第4871617號公報 專利文獻2 ：日本專利第6192778號公報Patent Document 1: Japanese Patent No. 4871617 Patent Document 2: Japanese Patent No. 6192778

發明概要 發明欲解決之課題 然而，專利文獻1及專利文獻2所示之加工技術已產生有如下的問題：對一旦進行研磨而被去除應變之面進行用於具有去疵能力之加工的所需工時會增加。Summary of the invention The problem to be solved by the invention However, the processing techniques shown in Patent Document 1 and Patent Document 2 have a problem in that the number of man-hours required for processing a surface whose strain has been removed by grinding to have the ability to remove defects increases.

本發明是有鑒於所述的問題點而作成的發明，其目的在於提供一種儘管抑制所需工時的增加仍然可以賦與去疵能力之晶圓的加工方法。 用以解決課題之手段The present invention was made in view of the above-described problems, and an object thereof is to provide a wafer processing method that can provide defect removal capabilities while suppressing an increase in required man-hours. means to solve problems

為了解決上述課題且達成目的，本發明之晶圓的加工方法是對晶圓進行薄化之晶圓的加工方法，其特徵在於具備以下步驟： 保護構件貼附步驟，在該晶圓的正面側貼附保護構件； 磨削步驟，以工作夾台的保持面保持該晶圓的保護構件側，且以磨削磨石來磨削該晶圓的背面側而進行薄化，其中前述磨削磨石是以黏結材固定有磨粒之磨削磨石；以及 研磨步驟，在該磨削步驟之後，一邊對該晶圓的背面側供給研磨漿料一邊按壓旋轉的研磨墊，以將該晶圓的背面側研磨到成為稍微殘留經磨削而形成之磨削應變層的狀態，來生成去疵層。In order to solve the above problems and achieve the purpose, the wafer processing method of the present invention is a wafer processing method for thinning the wafer, and is characterized by having the following steps: a protective member attaching step, attaching a protective member to the front side of the wafer; In the grinding step, the holding surface of the work chuck is used to hold the protective member side of the wafer, and a grinding stone is used to grind the back side of the wafer to thin it, wherein the aforementioned grinding stone is made of a bonding material Grinding stones with fixed abrasive grains; and In the polishing step, after the grinding step, the rotating polishing pad is pressed while supplying polishing slurry to the back side of the wafer, so as to polish the back side of the wafer until a slight amount of grinding remains. The state of the strain layer is used to generate the defect removal layer.

亦可為：在前述晶圓的加工方法中，更具備研磨條件選定步驟，前述研磨條件選定步驟是為了決定該研磨步驟之研磨條件，而對該磨削步驟實施後的該晶圓進行研磨，並且按該研磨墊之按壓力或研磨時間來測定經研磨後的該晶圓的該背面側的表面粗糙度，而選定在該研磨步驟中對應於完工的表面粗糙度的研磨條件。Alternatively, the wafer processing method may further include a grinding condition selection step. The grinding condition selection step is to determine the grinding conditions for the grinding step and to grind the wafer after the grinding step is performed. And the surface roughness of the back side of the polished wafer is measured according to the pressing force of the polishing pad or the polishing time, and the polishing conditions corresponding to the finished surface roughness in the polishing step are selected.

在前述晶圓的加工方法中，在該研磨步驟中，亦可將該晶圓的背面側研磨成該磨削應變層的表面粗糙度Ra成為超過1nm且在10nm以下。In the aforementioned wafer processing method, in the polishing step, the back side of the wafer may be polished so that the surface roughness Ra of the grinding strained layer exceeds 1 nm and is less than 10 nm.

亦可為：在前述晶圓的加工方法中，該晶圓是將搭載於板狀之支撐基板的元件晶片以塑模樹脂覆蓋的封裝晶圓，在該磨削步驟中，是磨削塑模樹脂側直到該元件晶片露出為止，在該研磨步驟中，是將封裝晶圓的該塑模樹脂側之面研磨到成為以下狀態：於經磨削而露出之該元件晶片的正面稍微殘留該磨削應變層。 發明效果Alternatively, in the aforementioned wafer processing method, the wafer is a package wafer in which a component chip mounted on a plate-shaped support substrate is covered with a mold resin, and in the grinding step, the mold is ground The resin side until the component chip is exposed. In this polishing step, the surface of the mold resin side of the package wafer is polished until it becomes the following state: a slight amount of the grinding material remains on the front surface of the component chip exposed after grinding. Cut the strain layer. Invention effect

本案發明之晶圓的加工方法會發揮以下效果：儘管抑制所需工時的增加仍然可以賦與去疵能力。The wafer processing method of the present invention has the following effect: it can provide defect removal capabilities while suppressing an increase in required man-hours.

用以實施發明之形態 針對用於實施本發明之形態(實施形態)，參照圖式並且詳細地進行說明。本發明並非因以下的實施形態所記載之內容而受到限定之發明。又，在以下所記載之構成要件中，包含所屬技術領域中具有通常知識者可以輕易地設想得到的或實質上是相同的構成要件。此外，以下所記載之構成是可適當組合的。又，在不脫離本發明之要旨的範圍內，可以進行各種構成之省略，置換或變更。Form used to implement the invention Modes (embodiments) for implementing the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the structural requirements described below include those that can be easily imagined by a person with ordinary knowledge in the relevant technical field or are substantially the same. In addition, the structures described below can be combined appropriately. In addition, various configurations may be omitted, replaced or changed within the scope of the invention without departing from the gist of the invention.

[實施形態1] 依據圖式來說明本發明之實施形態1的晶圓的加工方法。圖1是顯示實施形態1之晶圓的加工方法之加工對象的晶圓之一例的立體圖。圖2是顯示實施形態1之晶圓的加工方法之流程的流程圖。[Embodiment 1] The wafer processing method according to Embodiment 1 of the present invention will be described based on the drawings. FIG. 1 is a perspective view showing an example of a wafer to be processed in the wafer processing method according to the first embodiment. FIG. 2 is a flowchart showing the flow of the wafer processing method according to the first embodiment.

實施形態1之晶圓的加工方法是將圖1所示之晶圓1薄化的加工方法。在實施形態1中，晶圓1是以矽、藍寶石、或砷化鎵等作為基板2之圓板狀的半導體晶圓或光元件晶圓。如圖1及圖2所示，晶圓1是在基板2的正面3之藉由格子狀的分割預定線4所區劃出的複數個區域中各自形成有元件5。元件5是例如IC(積體電路，Integrated Circuit)或LSI (大型積體電路，Large Scale Integration)等。The wafer processing method of Embodiment 1 is a processing method of thinning the wafer 1 shown in FIG. 1 . In Embodiment 1, the wafer 1 is a disc-shaped semiconductor wafer or an optical element wafer having a substrate 2 of silicon, sapphire, gallium arsenide, or the like. As shown in FIGS. 1 and 2 , the wafer 1 has elements 5 formed in each of a plurality of areas demarcated by grid-like dividing lines 4 on the front surface 3 of the substrate 2 . The element 5 is, for example, an IC (Integrated Circuit) or an LSI (Large Scale Integration).

實施形態1之晶圓的加工方法是將晶圓1薄化至預定的成品厚度100之方法。如圖2所示，實施形態1之晶圓的加工方法具備保護構件貼附步驟ST2、磨削步驟ST3、研磨步驟ST4、及研磨條件選定步驟ST5。在實施形態1之晶圓的加工方法中，是操作人員等判定研磨步驟ST4中的研磨條件是否決定完畢(步驟ST1)，當判定為研磨條件決定完畢(步驟ST1：是)後，即進行到保護構件貼附步驟ST2。再者，在實施形態1中，研磨步驟ST4中的研磨條件，是在製造新的種類的晶圓1之時等決定。The wafer processing method in Embodiment 1 is a method of thinning the wafer 1 to a predetermined finished product thickness 100. As shown in FIG. 2 , the wafer processing method according to Embodiment 1 includes a protective member attaching step ST2, a grinding step ST3, a polishing step ST4, and a polishing condition selection step ST5. In the wafer processing method of Embodiment 1, the operator determines whether the polishing conditions have been determined in the polishing step ST4 (step ST1). When it is determined that the polishing conditions have been determined (step ST1: Yes), the process proceeds to Protective member attaching step ST2. Furthermore, in Embodiment 1, the polishing conditions in the polishing step ST4 are determined when a new type of wafer 1 is manufactured.

(保護構件貼附步驟) 圖3是顯示圖2所示之晶圓的加工方法的保護構件貼附步驟的立體圖。圖4是顯示圖2所示之晶圓的加工方法的保護構件貼附步驟後之晶圓的立體圖。(Steps for attaching protective components) FIG. 3 is a perspective view showing a step of attaching a protective member in the wafer processing method shown in FIG. 2 . FIG. 4 is a perspective view of the wafer after the step of attaching a protective member in the wafer processing method shown in FIG. 2 .

保護構件貼附步驟ST2是在晶圓1之基板2的正面3側貼附保護構件即黏著膠帶200之步驟。在實施形態1中，在保護構件貼附步驟ST2中，是如圖3所示，使與晶圓1相同直徑的黏著膠帶200的黏著層與晶圓1之基板2的正面3側相向後，如圖4所示，將黏著膠帶200的黏著層貼附到晶圓1之基板2的正面3。在實施形態1中，雖然是使用與晶圓1相同直徑的黏著膠帶200來作為保護構件，但在本發明中，保護構件並不限定於黏著膠帶200，亦可使用例如與晶圓1相同直徑且硬質的圓板狀的基板。當將黏著膠帶200貼附在晶圓1之基板2的正面3側後，晶圓的加工方法即進行到磨削步驟ST3。The protective member attaching step ST2 is a step of attaching an adhesive tape 200 as a protective member on the front surface 3 side of the substrate 2 of the wafer 1 . In Embodiment 1, in the protective member attaching step ST2, as shown in FIG. 3, the adhesive layer of the adhesive tape 200 having the same diameter as the wafer 1 is opposed to the front surface 3 side of the substrate 2 of the wafer 1. As shown in FIG. 4 , the adhesive layer of the adhesive tape 200 is attached to the front surface 3 of the substrate 2 of the wafer 1 . In Embodiment 1, the adhesive tape 200 with the same diameter as the wafer 1 is used as the protective member. However, in the present invention, the protective member is not limited to the adhesive tape 200. For example, the protective member may also be used with the same diameter as the wafer 1. And a hard disc-shaped substrate. After the adhesive tape 200 is attached to the front three sides of the substrate 2 of the wafer 1, the wafer processing method proceeds to the grinding step ST3.

(磨削步驟) 圖5是將圖2所示之晶圓的加工方法的磨削步驟以局部截面來顯示的側面圖。圖6是圖2所示之晶圓的加工方法的磨削步驟後之晶圓的主要部分的截面圖。磨削步驟ST3是如下之步驟：以磨削裝置20的工作夾台21的保持面22來保持晶圓1的黏著膠帶200側，並且以磨削磨石23來磨削晶圓1的正面3之背側的背面6側而進行薄化，其中前述磨削磨石23是以黏結材固定有磨粒之磨削磨石23。(grinding step) FIG. 5 is a side view showing a partial cross-section of a grinding step of the wafer processing method shown in FIG. 2 . FIG. 6 is a cross-sectional view of a main part of the wafer after the grinding step of the wafer processing method shown in FIG. 2 . The grinding step ST3 is a step of holding the adhesive tape 200 side of the wafer 1 with the holding surface 22 of the work chuck 21 of the grinding device 20 and grinding the front surface 3 of the wafer 1 with the grinding stone 23 The back side of the back side is thinned, and the aforementioned grinding stone 23 is a grinding stone 23 with abrasive grains fixed by a bonding material.

在磨削步驟ST3中，是讓磨削裝置20隔著黏著膠帶200將晶圓1的正面3側吸引保持於工作夾台21的保持面22。在磨削步驟ST3中，是如圖5所示，讓磨削裝置20藉由主軸24旋轉磨削輪25且一邊使工作夾台21繞著軸心旋轉一邊將磨削水26供給至晶圓1的背面6上，並且以預定之進給速度使磨削輪25的磨削磨石23接近於工作夾台21，藉此以磨削磨石23磨削晶圓1之基板2的背面6。In the grinding step ST3 , the grinding device 20 attracts and holds the front surface 3 side of the wafer 1 to the holding surface 22 of the chuck 21 via the adhesive tape 200 . In the grinding step ST3, as shown in FIG. 5, the grinding device 20 rotates the grinding wheel 25 through the spindle 24 and supplies the grinding water 26 to the wafer while rotating the work chuck 21 around the axis. on the back side 6 of the wafer 1, and the grinding stone 23 of the grinding wheel 25 is brought close to the work chuck 21 at a predetermined feed speed, thereby grinding the back side 6 of the substrate 2 of the wafer 1 with the grinding stone 23 .

如圖6所示，當將晶圓1薄化至比成品厚度100更厚一些的預定的厚度101後，晶圓的加工方法即進行到研磨步驟ST4。如圖6所示，磨削步驟ST3後的晶圓1是藉由磨削步驟ST3的磨削加工而將磨削應變層7形成在背面6整體。磨削應變層7是在晶圓1之基板2的背面6的表層形成有結晶缺陷、應變之層，且為捕捉附著於晶圓1之以銅(Cu)等金屬為主的不純物，而抑制元件5之由不純物所造成的金屬污染之所謂發揮去疵能力之層。再者，較理想的是，預定的厚度101是以下的厚度：將在研磨步驟ST4中所決定的研磨條件下研磨晶圓1時去除磨削應變層7之厚度方向的尺寸(以下記為去除量)102加上成品厚度100。As shown in FIG. 6 , after the wafer 1 is thinned to a predetermined thickness 101 that is thicker than the finished product thickness 100 , the wafer processing method proceeds to the grinding step ST4 . As shown in FIG. 6 , the grinding strain layer 7 is formed on the entire back surface 6 of the wafer 1 after the grinding step ST3 by the grinding process of the grinding step ST3 . The grinding strain layer 7 is a layer with crystal defects and strains formed on the surface layer of the back surface 6 of the substrate 2 of the wafer 1, and is used to capture impurities, mainly metals such as copper (Cu), that adhere to the wafer 1 and suppress them. The metal contamination caused by impurities in component 5 is the so-called layer that exerts the ability to remove defects. Furthermore, it is preferable that the predetermined thickness 101 is a thickness in which the thickness direction dimension of the grinding strain layer 7 is removed when the wafer 1 is polished under the polishing conditions determined in the polishing step ST4 (hereinafter referred to as removal). Quantity) 102 plus finished product thickness 100.

(研磨步驟) 圖7是顯示圖2所示之晶圓的加工方法的研磨步驟的側面圖。圖8是圖2所示之晶圓的加工方法的研磨步驟後之晶圓的主要部分的側面圖。研磨步驟ST4是如下之步驟：在磨削步驟ST3之後，對晶圓1的背面6側一邊供給研磨漿料一邊按壓旋轉的研磨裝置30之研磨墊33，而將晶圓1的背面6側研磨到成為稍微殘留經磨削而形成之磨削應變層7的狀態，來生成去疵層7-1。(grinding step) FIG. 7 is a side view showing a polishing step of the wafer processing method shown in FIG. 2 . FIG. 8 is a side view of a main part of the wafer after the polishing step of the wafer processing method shown in FIG. 2 . The polishing step ST4 is a step in which, after the grinding step ST3 , the polishing slurry is supplied to the backside 6 of the wafer 1 while pressing the polishing pad 33 of the rotating polishing device 30 to polish the backside 6 of the wafer 1 The defect removal layer 7-1 is formed in a state where the grinding strain layer 7 formed by grinding remains slightly.

在研磨步驟ST4中，是讓研磨裝置30隔著黏著膠帶200將晶圓1的正面3側吸引保持於工作夾台31的保持面32。在研磨步驟ST4中，是如圖6所示，藉由主軸34旋轉研磨輪35且一邊使工作夾台31繞著軸心旋轉一邊從研磨漿料供給源36通過開關閥37及設於研磨輪35內等之供給路38將研磨液即研磨漿料供給至研磨輪35的研磨墊33與晶圓1的背面6之間，並且以預定之進給速度使研磨墊33接近於工作夾台31，藉此以研磨墊33研磨晶圓1的背面6。In the polishing step ST4 , the polishing device 30 attracts and holds the front 3 sides of the wafer 1 to the holding surface 32 of the chuck 31 via the adhesive tape 200 . In the grinding step ST4, as shown in FIG. 6, the grinding wheel 35 is rotated by the spindle 34 and the work chuck 31 is rotated around the axis while the grinding slurry supply source 36 passes through the on-off valve 37 and is provided on the grinding wheel. The supply path 38 within 35 supplies the polishing fluid, that is, the polishing slurry, between the polishing pad 33 of the polishing wheel 35 and the back surface 6 of the wafer 1, and brings the polishing pad 33 close to the work chuck 31 at a predetermined feed speed. , thereby polishing the backside 6 of the wafer 1 with the polishing pad 33 .

實施形態1中，在研磨步驟ST4中，雖然是讓研磨裝置30一邊供給含有磨粒的研磨漿料來作為研磨液一邊研磨晶圓1的背面6，但在本發明中，亦可一邊供給純水來作為研磨液一邊使用具有固定磨粒的研磨墊33來研磨晶圓1的背面6，且亦可一邊供給鹼性的研磨液來作為研磨液一邊使用研磨墊33來實施化學機械研磨(CMP：Chemical Mechanical Polishing)。In Embodiment 1, in the polishing step ST4, the polishing device 30 is allowed to polish the back surface 6 of the wafer 1 while supplying the polishing slurry containing abrasive grains as the polishing fluid. However, in the present invention, the polishing device 30 may also supply the polishing slurry as the polishing liquid. Water is used as the polishing liquid to polish the backside 6 of the wafer 1 using the polishing pad 33 with fixed abrasive grains. Alternatively, alkaline polishing liquid is supplied as the polishing liquid and the polishing pad 33 is used to perform chemical mechanical polishing (CMP). : Chemical Mechanical Polishing).

又，在研磨步驟ST4中，是按照預先決定的研磨條件來研磨晶圓1的背面6。在實施形態1中，研磨條件為將研磨墊33按壓於晶圓1的背面6之按壓力、研磨時間，且是如下之條件：在研磨步驟ST4中，藉由研磨來去除磨削應變層7的表層，並且研磨成稍微殘留磨削應變層7來進行平坦化，而讓磨削應變層7的表面(亦即晶圓1的背面6)的表面粗糙度Ra成為超過1nm且在10nm以下。亦即，在本發明所謂之將晶圓1的背面6研磨至成為稍微殘留磨削應變層7的狀態，意指將晶圓1的背面6研磨成研磨後殘留的磨削應變層7的表面粗糙度Ra(亦即晶圓1的背面6的表面粗糙度Ra)成為超過1nm且在10nm以下。再者，表面粗糙度Ra為所謂的算術平均粗糙度。像這樣，在研磨步驟ST4中，研磨裝置30是薄化磨削應變層7，並且如圖8所示，對磨削應變層7的表面(亦即晶圓1之基板2的背面6)進行研磨，而將磨削應變層7形成為具有去疵能力的去疵層7-1，並且將晶圓1薄化至成品厚度100。Furthermore, in the polishing step ST4, the back surface 6 of the wafer 1 is polished according to predetermined polishing conditions. In Embodiment 1, the polishing conditions are the pressing force of the polishing pad 33 against the back surface 6 of the wafer 1 and the polishing time, and are the following conditions: in the polishing step ST4, the grinding strain layer 7 is removed by polishing. The surface layer of the wafer is polished until a slight amount of the grinding strain layer 7 remains, and the surface roughness Ra of the surface of the grinding strain layer 7 (that is, the back surface 6 of the wafer 1 ) becomes more than 1 nm and less than 10 nm. That is, in the present invention, when the back surface 6 of the wafer 1 is polished to a state where the grinding strain layer 7 remains slightly, it means that the back surface 6 of the wafer 1 is polished to the surface where the grinding strain layer 7 remains after grinding. The roughness Ra (that is, the surface roughness Ra of the back surface 6 of the wafer 1 ) exceeds 1 nm and is 10 nm or less. In addition, the surface roughness Ra is the so-called arithmetic mean roughness. In this way, in the polishing step ST4, the polishing device 30 thins and grinds the strained layer 7, and as shown in FIG. Grinding is performed to form the grinding strain layer 7 into a defect removal layer 7-1 with defect removal capability, and the wafer 1 is thinned to a finished product thickness of 100.

在實施形態1之晶圓的加工方法中，雖然是將研磨步驟ST4之加工條件的研磨墊33的按壓力設為15kPa，且設為研磨時間15sec來將去疵層7-1的表面(亦即晶圓1之基板2的背面6)的表面粗糙度Ra形成為7nm以上且8nm以下，但本發明亦可將研磨步驟ST4之加工條件的研磨墊33的按壓力設為15kPa，且設為研磨時間30sec來將去疵層7-1的表面(亦即晶圓1之基板2的背面6)的表面粗糙度Ra形成為4nm以上且6nm以下，亦可將研磨步驟ST4之加工條件的研磨墊33的按壓力設為15kPa，且設為研磨時間60sec來將去疵層7-1的表面(亦即晶圓1之基板2的背面6)的表面粗糙度Ra形成為2nm以上且3nm以下。In the wafer processing method of Embodiment 1, in the processing conditions of the polishing step ST4, the pressing force of the polishing pad 33 is set to 15 kPa, and the polishing time is set to 15 seconds to polish the surface of the defect removal layer 7-1 (also That is, the surface roughness Ra of the back surface 6) of the substrate 2 of the wafer 1 is formed to be 7 nm or more and 8 nm or less. However, the present invention can also set the pressing force of the polishing pad 33 in the processing conditions of the polishing step ST4 to 15 kPa, and set it to The polishing time is 30 seconds to form the surface roughness Ra of the surface of the defect removal layer 7-1 (that is, the back surface 6 of the substrate 2 of the wafer 1) to 4 nm or more and 6 nm or less. The polishing conditions of the polishing step ST4 can also be adjusted. The pressing force of the pad 33 is set to 15 kPa, and the polishing time is set to 60 seconds to form the surface roughness Ra of the surface of the defect removal layer 7-1 (that is, the back surface 6 of the substrate 2 of the wafer 1) to 2 nm or more and 3 nm or less. .

又，在實施形態1之晶圓的加工方法中，在研磨步驟ST4中所用的研磨墊33的直徑是例如450mm，且研磨墊33的厚度為例如4mm。又，在實施形態1之晶圓的加工方法中，在研磨步驟ST4中，主軸34的旋轉數為例如500rpm，工作夾台31的旋轉數為505rpm，且研磨漿料的供給量是0.2L/min。當在研磨步驟ST4中按照加工條件來研磨晶圓1的背面6後，晶圓的加工方法即結束。Furthermore, in the wafer processing method of Embodiment 1, the diameter of the polishing pad 33 used in the polishing step ST4 is, for example, 450 mm, and the thickness of the polishing pad 33 is, for example, 4 mm. Furthermore, in the wafer processing method of Embodiment 1, in the polishing step ST4, the rotation speed of the spindle 34 is, for example, 500 rpm, the rotation speed of the work chuck 31 is 505 rpm, and the supply amount of the polishing slurry is 0.2 L/ min. After the back surface 6 of the wafer 1 is polished according to the processing conditions in the polishing step ST4, the wafer processing method ends.

又，在晶圓的加工方法中，當判定為研磨條件尚未決定完畢(步驟ST1：否)時，即進行到研磨條件選定步驟ST5。In addition, in the wafer processing method, when it is determined that the polishing conditions have not been determined yet (step ST1: NO), the process proceeds to the polishing condition selection step ST5.

(研磨條件選定步驟) 圖9是圖2所示之晶圓的加工方法的研磨條件選定步驟前之晶圓的主要部分的截面圖。研磨條件選定步驟ST5是如下之步驟：為了決定研磨步驟ST4之研磨條件，而對磨削步驟ST3實施後的晶圓1進行研磨，並將經研磨後之晶圓1的背面6側的表面粗糙度Ra按每個研磨墊33的按壓力或研磨時間來測定，而選定在研磨步驟ST4中對應於完工的表面粗糙度Ra的研磨條件。(Steps for selecting grinding conditions) FIG. 9 is a cross-sectional view of a main part of the wafer before the step of selecting polishing conditions in the wafer processing method shown in FIG. 2 . The polishing condition selection step ST5 is the following step: in order to determine the polishing conditions of the polishing step ST4, the wafer 1 after the grinding step ST3 is performed is polished, and the surface of the backside 6 of the polished wafer 1 is roughened. The degree Ra is measured based on the pressing force or polishing time of each polishing pad 33, and the polishing conditions corresponding to the finished surface roughness Ra in the polishing step ST4 are selected.

在研磨條件選定步驟ST5中，首先，準備複數個已實施磨削步驟ST3的晶圓1，並且按各晶圓1使研磨條件不同，並與研磨步驟ST4同樣地使用研磨裝置30來研磨晶圓1的背面6，來對磨削應變層7進行薄化並且將磨削應變層7的表面(亦即晶圓1的背面6)平坦化而形成去疵層7-1。在研磨條件選定步驟ST5中，是在圖9所示之磨削步驟ST3後的晶圓中，按每個加工條件(亦即按研磨墊33之按壓力或研磨時間)而使磨削應變層7的去除量102與留下量(從磨削應變層7之厚度103扣除去除量102之量)104不同，並使研磨後的去疵層7-1的表面(亦即晶圓1的背面6)的表面粗糙度Ra不同。再者，留下量104亦為研磨步驟ST4後之去疵層7-1的厚度。In the polishing condition selection step ST5, first, a plurality of wafers 1 that have been subjected to the grinding step ST3 are prepared, the polishing conditions are different for each wafer 1, and the wafers are polished using the polishing device 30 in the same manner as in the polishing step ST4. The back side 6 of the wafer 1 is used to thin the grinding strain layer 7 and planarize the surface of the grinding strain layer 7 (that is, the back side 6 of the wafer 1) to form a defect removal layer 7-1. In the polishing condition selection step ST5, in the wafer after the grinding step ST3 shown in FIG. 9, the strained layer is ground according to each processing condition (that is, according to the pressing force of the polishing pad 33 or the polishing time). The removal amount 102 of 7 is different from the remaining amount (the amount of removal 102 deducted from the thickness 103 of the grinding strain layer 7) 104, and the surface of the polished defect removal layer 7-1 (that is, the back side of the wafer 1 6) The surface roughness Ra is different. Furthermore, the remaining amount 104 is also the thickness of the defect removal layer 7-1 after the polishing step ST4.

在實施形態1中，研磨條件選定步驟ST5的去除量102越大，去疵層7-1的表面(亦即晶圓1的背面6)的表面粗糙度Ra即變得越小。再者，在實施形態1中，雖然晶圓1之分割後的元件5，若去疵層7-1的表面的表面粗糙度Ra變大時，會提升去疵能力(捕捉不純物之能力)，但會降低抗折強度。In Embodiment 1, the larger the removal amount 102 of the polishing condition selection step ST5 is, the smaller the surface roughness Ra of the surface of the defect removal layer 7-1 (that is, the back surface 6 of the wafer 1) becomes. Furthermore, in Embodiment 1, if the surface roughness Ra of the defect removal layer 7-1 of the device 5 after the wafer 1 is divided becomes larger, the defect removal ability (the ability to capture impurities) will be improved. But it will reduce the flexural strength.

在研磨條件選定步驟ST5中，是按研磨墊33的按壓力或研磨時間而測定研磨後之晶圓1的背面6的表面粗糙度Ra，並將複數個研磨條件當中為如下之加工條件選定作為研磨步驟ST4的加工條件：背面6的表面粗糙度Ra成為在研磨步驟ST4中完工的表面粗糙度即超過1nm且在10nm以下的範圍內。再者，在研磨條件選定步驟ST5中，研磨後的晶圓1的背面6的表面粗糙度Ra為超過1nm且在10nm以下的範圍內之加工條件存在有複數個的情況下，所期望的是考量晶圓1之分割後的元件5所要求的去疵能力及抗折強度來選定加工條件。當選定研磨步驟ST4的加工條件後，晶圓的加工方法即進行到保護構件貼附步驟ST2。In the polishing condition selection step ST5, the surface roughness Ra of the backside 6 of the polished wafer 1 is measured according to the pressing force of the polishing pad 33 or the polishing time, and the following processing conditions are selected among a plurality of polishing conditions. Processing conditions of the polishing step ST4: The surface roughness Ra of the back surface 6 is the surface roughness completed in the polishing step ST4, that is, in the range of more than 1 nm and not more than 10 nm. Furthermore, in the polishing condition selection step ST5, when there are a plurality of processing conditions in which the surface roughness Ra of the back surface 6 of the polished wafer 1 exceeds 1 nm and is within the range of 10 nm or less, it is desirable that The processing conditions are selected by considering the defect removal ability and bending strength required for the divided components 5 of the wafer 1 . After the processing conditions of the grinding step ST4 are selected, the wafer processing method proceeds to the protective member attaching step ST2.

實施形態1之晶圓的加工方法，是在磨削晶圓1的背面6的磨削步驟ST3後的研磨步驟ST4中，在不將磨削應變層7完全地去除的情形下，於設定研磨成稍微殘留磨削應變層7的去除量102之後，在研磨步驟ST4研磨晶圓1的背面6。因此，晶圓的加工方法，因為是以使抗折強度提升並且形成有具有去疵能力之去疵層7-1的狀態來結束晶圓1的加工，所以可以實施有效率之晶圓的薄化與研磨。其結果，晶圓的加工方法變得不需要在研磨步驟ST4後用於進一步賦與去疵能力之步驟，而發揮以下之效果：儘管抑制所需的工時的增加，仍然可以對晶圓1及已從晶圓1單片化成一個個的元件5賦與去疵能力。The wafer processing method of Embodiment 1 is to set the polishing step ST4 after the grinding step ST3 of grinding the back surface 6 of the wafer 1 without completely removing the grinding strain layer 7 . After the removal amount 102 of the grinding strain layer 7 remains slightly, the back surface 6 of the wafer 1 is polished in the polishing step ST4. Therefore, the wafer processing method ends the processing of the wafer 1 in a state where the flexural strength is increased and the defect removal layer 7-1 with the defect removal ability is formed, so that efficient wafer thinning can be performed. Chemical and grinding. As a result, the wafer processing method eliminates the need for a step for further imparting defect removal capability after the polishing step ST4, and exhibits the following effect: It is possible to polish the wafer 1 while suppressing an increase in required man-hours. And the wafer 1 has been singulated into individual components 5 to provide defect removal capabilities.

又，實施形態1之晶圓的加工方法是在研磨條件選定步驟ST5中，使加工條件相異而和研磨步驟ST4同樣地對複數個磨削步驟ST3實施後的晶圓1進行研磨，來選定適當的研磨條件。其結果，晶圓的加工方法儘管不需 要在研磨步驟ST4後用於進一步賦與去疵能力之步驟，仍然可以謀求對已從晶圓1單片化成一個個的元件5之去疵能力的賦與及抗折強度的提升。Furthermore, in the wafer processing method of Embodiment 1, in the polishing condition selection step ST5, the wafer 1 after the plurality of grinding steps ST3 is polished in the same manner as the polishing step ST4 while changing the processing conditions to select the wafer. Proper grinding conditions. As a result, the wafer processing method does not require a step for further imparting the defect removal capability after the polishing step ST4, but it is still possible to provide the defect removal capability to the individual components 5 that have been singulated from the wafer 1. And the improvement of flexural strength.

又，實施形態1之晶圓的加工方法，由於在研磨步驟ST4中，是以磨削應變層7的表面(亦即晶圓1的背面6)的表面粗糙度Ra成為超過1nm且在10nm以下的方式來研磨晶圓1的背面6，因此儘管設成不需要在研磨步驟ST4後用於進一步賦與去疵能力的步驟，仍然可以謀求對已從晶圓1單片化成一個個的元件5之去疵能力的賦與及抗折強度的提升。In addition, in the wafer processing method of Embodiment 1, in the grinding step ST4, the surface roughness Ra of the surface of the strained layer 7 (that is, the back surface 6 of the wafer 1) is ground to exceed 1 nm and be less than 10 nm. The backside 6 of the wafer 1 is polished in such a way that although there is no need for a step for further imparting defect removal capability after the polishing step ST4, it is still possible to achieve the goal of singulating the wafer 1 into individual components 5 It provides the ability to remove defects and improves the flexural strength.

[實施形態2] 依據圖式來說明本發明之實施形態1的晶圓的加工方法。圖10是顯示實施形態2之晶圓的加工方法之加工對象的晶圓的立體圖。圖11是沿圖10中的XI-XI線的截面圖。圖12是顯示實施形態2之晶圓的加工方法之加工後的晶圓的立體圖。圖13是沿圖12中的沿XIII-XIII線的截面圖。圖14是將圖13中的XIV放大而顯示的圖。再者，在圖10、圖11、圖12、圖13及圖14中，對和實施形態1相同部分附加相同的符號而省略說明。[Embodiment 2] The wafer processing method according to Embodiment 1 of the present invention will be described based on the drawings. FIG. 10 is a perspective view of a wafer to be processed in the wafer processing method according to Embodiment 2. FIG. FIG. 11 is a cross-sectional view along line XI-XI in FIG. 10 . 12 is a perspective view of a wafer after processing according to the wafer processing method according to Embodiment 2. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12 . FIG. 14 is an enlarged view of XIV in FIG. 13 . In addition, in FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 and FIG. 14 , the same parts as those in Embodiment 1 are assigned the same reference numerals, and descriptions thereof are omitted.

實施形態2之晶圓的加工方法，除了加工對象之晶圓1-2相異以外，與實施形態1相同。實施形態2之晶圓的加工方法之加工對象的晶圓1-2，如圖10及圖11所示，具備複數個元件晶片10、圓板狀的支撐基板11、及塑模樹脂12。The wafer processing method of Embodiment 2 is the same as Embodiment 1 except that the wafer 1-2 to be processed is different. The wafer 1-2 to be processed in the wafer processing method according to the second embodiment includes a plurality of element wafers 10, a disk-shaped support substrate 11, and a mold resin 12, as shown in FIGS. 10 and 11 .

元件晶片10是例如設成將實施形態1所示之晶圓1沿著分割預定線4分割等而被製造的構成。元件晶片10是將形成有元件5的正面3重疊在支撐基板11上，而等間隔地搭載在支撐基板11上。在實施形態2中，支撐基板11雖然是具備與元件晶片10的電極連接之未圖示的配線層的構成，但在本發明中並非限定於此。塑模樹脂12是由合成樹脂所構成且被覆支撐基板11上的複數個元件晶片10。像這樣，實施形態2之晶圓的加工方法的加工對象之晶圓1-2是將搭載在支撐基板11上之元件晶片10以塑模樹脂12覆蓋之所謂的封裝晶圓。The element wafer 10 is, for example, manufactured by dividing the wafer 1 shown in Embodiment 1 along four planned dividing lines. The element wafer 10 is mounted on the support substrate 11 at equal intervals by overlapping the front surface 3 on which the elements 5 are formed on the support substrate 11 . In Embodiment 2, the support substrate 11 is configured to include a wiring layer (not shown) connected to the electrodes of the element chip 10, but the present invention is not limited to this. The mold resin 12 is made of synthetic resin and covers the plurality of element chips 10 on the support substrate 11 . As described above, the wafer 1 - 2 to be processed in the wafer processing method of Embodiment 2 is a so-called package wafer in which the element wafer 10 mounted on the support substrate 11 is covered with the mold resin 12 .

實施形態2之晶圓的加工方法，是與實施形態1同樣地具備保護構件貼附步驟ST2、磨削步驟ST3、研磨步驟ST4及研磨條件選定步驟ST5。實施形態2之晶圓的加工方法是在保護構件貼附步驟ST2中，如圖12所示，在晶圓1-2的支撐基板11的正面11-1側貼附保護構件即黏著膠帶200。實施形態2之晶圓的加工方法，是在磨削步驟ST3中，以磨削裝置20的工作夾台21保持晶圓1-2的黏著膠帶200側，並以磨削磨石23磨削晶圓1-2的背面即塑模樹脂12的表面12-1，而如圖12及圖13所示，將塑模樹脂12磨削到元件晶片10在晶圓1-2的塑模樹脂12的表面12-1側露出為止，而在元件晶片10的正面3的背側的背面6形成磨削應變層7。The wafer processing method of Embodiment 2 includes a protective member attaching step ST2, a grinding step ST3, a polishing step ST4, and a polishing condition selection step ST5 like the first embodiment. The wafer processing method according to Embodiment 2 is to attach an adhesive tape 200 as a protective member to the front surface 11 - 1 side of the support substrate 11 of the wafer 1 - 2 in the protective member attaching step ST2 as shown in FIG. 12 . The wafer processing method of Embodiment 2 is that in the grinding step ST3, the adhesive tape 200 side of the wafer 1-2 is held by the work chuck 21 of the grinding device 20, and the wafer is ground with the grinding stone 23. The back side of the circle 1-2 is the surface 12-1 of the mold resin 12. As shown in Figures 12 and 13, the mold resin 12 is ground to the component chip 10 on the surface of the mold resin 12 of the wafer 1-2. The grinding strain layer 7 is formed on the back surface 6 of the front surface 3 of the element wafer 10 until the front surface 12 - 1 side is exposed.

實施形態2之晶圓的加工方法，是在研磨步驟ST4中，一邊對晶圓1-2的塑模樹脂12的表面12-1及經磨削而露出的元件晶片10的背面6供給研磨漿料，一邊與實施形態1同樣地將晶圓1-2的塑模樹脂12側的背面6及表面12-1研磨到成為稍微殘留磨削應變層7的狀態，而如圖14所示，在元件晶片10的背面6形成與實施形態1相同的表面粗糙度Ra的去疵層7-1。The wafer processing method of Embodiment 2 supplies polishing slurry to the surface 12-1 of the mold resin 12 of the wafer 1-2 and the exposed back surface 6 of the element chip 10 after grinding in the polishing step ST4. While grinding the back surface 6 and the surface 12-1 of the wafer 1-2 on the mold resin 12 side in the same manner as in Embodiment 1 until a slight grinding strain layer 7 remains, as shown in FIG. 14, The defect removal layer 7-1 having the same surface roughness Ra as in Embodiment 1 is formed on the back surface 6 of the element wafer 10.

實施形態2之晶圓的加工方法，與實施形態1同樣地，是在磨削晶圓1-2之各元件晶片10的背面6的磨削步驟ST3後的研磨步驟ST4中，在不將磨削應變層7完全地去除的情形下，於設定研磨成稍微殘留磨削應變層7的去除量102之後，在研磨步驟ST4中研磨晶圓1-2的背面6。其結果，實施形態2之晶圓的加工方法與實施形態1同樣地，變得不需要在研磨步驟ST4後用於進一步賦與去疵能力之步驟，而發揮以下之效果：儘管抑制所需工時的增加，仍然可以對晶圓1-2及已從晶圓1-2單片化成一個個的包含元件5的元件晶片10賦與去疵能力。The wafer processing method of Embodiment 2 is the same as Embodiment 1. In the grinding step ST4 after the grinding step ST3 of grinding the back surface 6 of each element chip 10 of the wafer 1-2, the grinding step ST4 is not performed. When the grinding strain layer 7 is completely removed, the removal amount 102 of grinding is set so that the grinding strain layer 7 remains slightly, and then the back surface 6 of the wafer 1 - 2 is ground in the grinding step ST4. As a result, the wafer processing method of Embodiment 2, like Embodiment 1, eliminates the need for a step for further imparting defect removal capability after polishing step ST4, and exhibits the following effect: while suppressing the required work With the increase of time, the defect removal capability can still be provided to the wafer 1-2 and the component wafers 10 that have been singulated from the wafer 1-2 and include the components 5 one by one.

又，實施形態2之晶圓的加工方法，由於是在研磨步驟ST4中，在不將磨削應變層7完全地去除的情形下，研磨成稍微殘留磨削應變層7，而將殘留的磨削應變層7設為去疵層7-1，因此，儘管特別抑制與封裝晶圓即晶圓1-2的加工相關之所需工時，仍然可以在元件晶片10形成去疵層7-1，其中前述封裝晶圓是將已配置在支撐基板11上的元件晶片10以塑模樹脂12被覆之晶圓。In addition, in the wafer processing method of Embodiment 2, since the grinding strain layer 7 is not completely removed in the polishing step ST4, the grinding strain layer 7 is polished so that the grinding strain layer 7 slightly remains, and the remaining grinding strain layer 7 is polished. Since the shaving layer 7 is used as the defect removal layer 7-1, it is possible to form the defect removal layer 7-1 on the element wafer 10 while particularly reducing the man-hours required for processing the package wafer, that is, the wafer 1-2. , wherein the aforementioned package wafer is a wafer in which the element wafer 10 arranged on the supporting substrate 11 is coated with the molding resin 12 .

接著，本發明的發明人對本發明之晶圓的加工方法的效果作了確認。將結果列於表1。Next, the inventor of the present invention confirmed the effect of the wafer processing method of the present invention. The results are listed in Table 1.

[表1] [Table 1]

在表1中，本發明的發明人是使研磨條件不同而與研磨步驟ST4同樣地對磨削步驟ST3後的複數個晶圓1進行研磨，且生成有比較例1、比較例2、本發明品1、本發明品2及本發明品3。本發明的發明人在比較例1、比較例2、本發明品1、本發明品2及本發明品3各自中確認了：殘留的磨削應變層7(即去疵層7-1)的表面的表面粗糙度Ra、去疵能力、分割後的抗折強度。再者，在表1的比較例1、比較例2、本發明品1、本發明品2及本發明品3各自中，磨削步驟ST3後的晶圓1的磨削應變層7的表面的表面粗糙度Ra為約10nm。In Table 1, the inventor of the present invention changed the polishing conditions and polished the plurality of wafers 1 after the grinding step ST3 in the same manner as the polishing step ST4, and produced Comparative Example 1, Comparative Example 2, and the present invention. Product 1, product 2 of the invention and product 3 of the invention. The inventors of the present invention confirmed in each of Comparative Example 1, Comparative Example 2, Invention Product 1, Invention Product 2, and Invention Product 3: The residual grinding strain layer 7 (that is, the defect removal layer 7-1) Surface roughness Ra, defect removal ability, and flexural strength after segmentation. Furthermore, in each of Comparative Example 1, Comparative Example 2, Invention Product 1, Invention Product 2, and Invention Product 3 in Table 1, the surface of the grinding strain layer 7 of the wafer 1 after the grinding step ST3 was Surface roughness Ra is approximately 10 nm.

比較例1之研磨條件是將研磨墊33之按壓力設為25kPa，並將研磨時間設為2min。比較例2之研磨條件是將研磨墊33之按壓力設為15kPa，並將研磨時間設為5sec。本發明品1之研磨條件是將研磨墊33之按壓力設為15kPa，並將研磨時間設為60sec。本發明品2之研磨條件是將研磨墊33之按壓力設為15kPa，並將研磨時間設為30sec。本發明品3之研磨條件是將研磨墊33之按壓力設為15kPa，並將研磨時間設為15sec。The polishing conditions of Comparative Example 1 were to set the pressing force of the polishing pad 33 to 25 kPa and the polishing time to 2 minutes. The polishing conditions of Comparative Example 2 were to set the pressing force of the polishing pad 33 to 15 kPa and the polishing time to 5 seconds. The polishing conditions of Product 1 of the present invention are that the pressing force of the polishing pad 33 is set to 15 kPa and the polishing time is set to 60 seconds. The polishing conditions of Product 2 of the present invention are that the pressing force of the polishing pad 33 is set to 15 kPa and the polishing time is set to 30 seconds. The polishing conditions of product 3 of the present invention are to set the pressing force of the polishing pad 33 to 15 kPa and the polishing time to 15 seconds.

比較例1之去疵層7-1的表面的表面粗糙度Ra是1nm以下，比較例2之去疵層7-1的表面的表面粗糙度Ra是超過10nm。又，本發明品1的去疵層7-1的表面的表面粗糙度Ra是2nm以上且3nm以下，本發明品2的去疵層7-1的表面的表面粗糙度Ra是4nm以上且6nm以下，本發明品3的去疵層7-1的表面的表面粗糙度Ra是7nm以上且8nm以下。The surface roughness Ra of the surface of the defect removal layer 7-1 in Comparative Example 1 is 1 nm or less, and the surface roughness Ra of the surface of the defect removal layer 7-1 in Comparative Example 2 exceeds 10 nm. Moreover, the surface roughness Ra of the surface of the defect removal layer 7-1 of the invention product 1 is 2 nm or more and 3 nm or less, and the surface roughness Ra of the surface of the defect removal layer 7-1 of the invention product 2 is 4 nm or more and 6 nm. Hereinafter, the surface roughness Ra of the surface of the defect removal layer 7-1 of Product 3 of the present invention is 7 nm or more and 8 nm or less.

又，表1是以圓圈表示具有單片成一個個後所要求之去疵能力者，並將不具所要求的去疵能力者以打叉表示。又，表1是以圓圈表示具有單片成一個個後所要求之抗折強度者，並將不具所要求之抗折強度者以打叉表示。In addition, in Table 1, those who have the required defect removal ability after the individual pieces are cut into pieces are represented by circles, and those who do not have the required defect removal ability are represented by crosses. In addition, in Table 1, those that have the required flexural strength after being cut into individual pieces are represented by circles, and those that do not have the required flexural strength are represented by crosses.

根據表1，相對於比較例1是去疵能力為打叉，本發明品1、本發明品2及本發明品3是去疵能力為圓圈。據此，根據表1已很清楚的是，可以藉由在研磨步驟ST4中研磨成殘留的磨削應變層7/去疵層7-1的表面的表面粗糙度Ra成為超過1nm且在10nm以下，而將磨削步驟ST3後之晶圓1、1-2賦與所要求的去疵能力。According to Table 1, compared to Comparative Example 1, the defect removal ability is a cross, while Invention Product 1, Invention Product 2, and Invention Product 3 have defect removal capabilities as a circle. From this, it is clear from Table 1 that the surface roughness Ra of the surface of the remaining grinding strain layer 7/defect removal layer 7-1 can be polished in the polishing step ST4 to exceed 1 nm and be less than 10 nm. , and impart the required defect removal capability to the wafers 1 and 1-2 after the grinding step ST3.

又，根據表1，相對於比較例2是抗折強度為打叉，本發明品1、本發明品2及本發明品3是抗折強度為圓圈。據此，根據表1已很清楚的是，可以藉由在研磨步驟ST4中研磨成殘留的磨削應變層7/去疵層7-1的表面的表面粗糙度Ra成為超過1nm且在10nm以下，而將磨削步驟ST3後之晶圓1、1-2賦與所要求的抗折強度。據此，根據表1已很清楚的是，可以藉由在研磨步驟ST4中去疵層7-1的表面的表面粗糙度Ra成為超過1nm且在10nm以下，而將磨削步驟ST3後之晶圓1、1-2賦與所要求的去疵能力及抗折強度之雙方，且儘管設成不需要在研磨步驟ST4後用於進一步賦與去疵能力的步驟，仍然可以謀求去疵能力的賦與與抗折強度的提升。Moreover, according to Table 1, compared to Comparative Example 2, the flexural strength is a cross, while Invention Products 1, Invention Products 2, and Invention Products 3 have a circle in the flexural strength. From this, it is clear from Table 1 that the surface roughness Ra of the surface of the remaining grinding strain layer 7/defect removal layer 7-1 can be polished in the polishing step ST4 to exceed 1 nm and be less than 10 nm. , and impart the required flexural strength to the wafers 1 and 1-2 after the grinding step ST3. From this, it is clear from Table 1 that the surface roughness Ra of the surface of the defect removal layer 7-1 in the polishing step ST4 can be more than 1 nm and 10 nm or less, and the crystal after the grinding step ST3 can be improved. Circles 1 and 1-2 provide both the required defect removal ability and flexural strength, and even if it is not necessary to further provide the defect removal ability after the grinding step ST4, the defect removal ability can still be achieved. Provides an increase in flexural strength.

再者，本發明並非限定於上述實施形態之發明。亦即，在不脫離本發明之主旨的範圍內，可以進行各種變形來實施。In addition, this invention is not limited to the invention of the said embodiment. That is, various modifications can be made without departing from the gist of the present invention.

1:晶圓 1-2:晶圓(封裝晶圓) 2:基板 3、11-1:正面 4:分割預定線 5:元件 6:背面 7:磨削應變層 7-1:去疵層 11:支撐基板 12:塑模樹脂 12-1:塑模樹脂的表面(晶圓的背面) 20:磨削裝置 21、31:工作夾台 22、32:保持面 23:磨削磨石 24、34:主軸 25:磨削輪 26:磨削水 30:研磨裝置 33:研磨墊 35:研磨輪 36:研磨漿料供給源 37:開關閥 38:供給路 100:成品厚度 101、103:厚度 102:去除量 104:留下量 200:黏著膠帶(保護構件) ST1:步驟 ST2:保護構件貼附步驟 ST3:磨削步驟 ST4:研磨步驟 ST5:研磨條件選定步驟1:wafer 1-2: Wafer (packaging wafer) 2:Substrate 3. 11-1: Front 4: Split the scheduled line 5:Component 6: Back 7: Grinding strain layer 7-1: Remove defective layer 11: Support base plate 12:Molding resin 12-1: Surface of molding resin (backside of wafer) 20:Grinding device 21, 31: Work clamping table 22, 32: Maintain surface 23: Grinding stone 24, 34: Spindle 25:Grinder wheel 26:Grinding water 30:Grinding device 33: Polishing pad 35:Grinder wheel 36: Grinding slurry supply source 37: On/off valve 38:Supply Road 100: Finished product thickness 101, 103: Thickness 102: Removal amount 104: Remaining amount 200: Adhesive tape (protective member) ST1: Step ST2: Steps to attach protective components ST3: Grinding step ST4: Grinding step ST5: Steps for selecting grinding conditions

圖1是顯示實施形態1之晶圓的加工方法之加工對象的晶圓之一例的立體圖。 圖2是顯示實施形態1之晶圓的加工方法之流程的流程圖。 圖3是顯示圖2所示之晶圓的加工方法的保護構件貼附步驟的立體圖。 圖4是顯示圖2所示之晶圓的加工方法的保護構件貼附步驟後之晶圓的立體圖。 圖5是將圖2所示之晶圓的加工方法的磨削步驟以局部截面來顯示的側面圖。 圖6是圖2所示之晶圓的加工方法的磨削步驟後之晶圓的主要部分的截面圖。 圖7是顯示圖2所示之晶圓的加工方法的研磨步驟的側面圖。 圖8是圖2所示之晶圓的加工方法的研磨步驟後之晶圓的主要部分的側面圖。 圖9是圖2所示之晶圓的加工方法的研磨條件選定步驟前之晶圓的主要部分的截面圖。 圖10是顯示實施形態2之晶圓的加工方法之加工對象的晶圓的立體圖。 圖11是圖10中的沿XI-XI線的截面圖。 圖12是顯示實施形態2之晶圓的加工方法的加工後的晶圓的立體圖。 圖13是圖12中的沿XIII-XIII線的截面圖。 圖14是將圖13中的XIV放大而顯示的圖。FIG. 1 is a perspective view showing an example of a wafer to be processed in the wafer processing method according to the first embodiment. FIG. 2 is a flowchart showing the flow of the wafer processing method according to the first embodiment. FIG. 3 is a perspective view showing a step of attaching a protective member in the wafer processing method shown in FIG. 2 . FIG. 4 is a perspective view of the wafer after the step of attaching a protective member in the wafer processing method shown in FIG. 2 . FIG. 5 is a side view showing a partial cross-section of a grinding step of the wafer processing method shown in FIG. 2 . FIG. 6 is a cross-sectional view of a main part of the wafer after the grinding step of the wafer processing method shown in FIG. 2 . FIG. 7 is a side view showing a polishing step of the wafer processing method shown in FIG. 2 . FIG. 8 is a side view of a main part of the wafer after the polishing step of the wafer processing method shown in FIG. 2 . FIG. 9 is a cross-sectional view of a main part of the wafer before the step of selecting polishing conditions in the wafer processing method shown in FIG. 2 . FIG. 10 is a perspective view of a wafer to be processed in the wafer processing method according to Embodiment 2. FIG. FIG. 11 is a cross-sectional view along line XI-XI in FIG. 10 . 12 is a perspective view of a processed wafer showing the wafer processing method according to Embodiment 2. FIG. 13 is a cross-sectional view along line XIII-XIII in FIG. 12 . FIG. 14 is an enlarged view of XIV in FIG. 13 .

ST1:步驟 ST1: Step

ST2:保護構件貼附步驟 ST2: Steps to attach protective components

ST3:磨削步驟 ST3: Grinding step

ST4:研磨步驟 ST4: Grinding step

ST5:研磨條件選定步驟 ST5: Steps for selecting grinding conditions

Claims (3)

一種晶圓的加工方法，是薄化晶圓之晶圓的加工方法，並具備以下步驟：保護構件貼附步驟，在該晶圓的正面側貼附保護構件；磨削步驟，以工作夾台的保持面保持該晶圓的保護構件側，且以磨削磨石來磨削該晶圓的背面側而進行薄化，其中前述磨削磨石是以黏結材固定有磨粒之磨削磨石；以及研磨步驟，在該磨削步驟之後，一邊對該晶圓的背面側供給研磨漿料一邊按壓旋轉的研磨墊，以將該晶圓的背面側研磨到成為稍微殘留經磨削而形成之磨削應變層的狀態，來生成去疵層，該晶圓是將搭載於板狀之支撐基板的元件晶片以塑模樹脂覆蓋的封裝晶圓，在該磨削步驟中，是磨削塑模樹脂側直到該元件晶片露出為止，在該研磨步驟中，是將封裝晶圓的該塑模樹脂側之面研磨到成為以下狀態：於經磨削而露出之該元件晶片的正面稍微殘留該磨削應變層。 A wafer processing method is a wafer processing method for thinning the wafer, and has the following steps: a protective member attaching step, attaching a protective member to the front side of the wafer; a grinding step, using a work chuck The holding surface holds the protective member side of the wafer, and a grinding stone is used to grind the back side of the wafer to thin it, wherein the aforementioned grinding stone is a grinding grinding wheel with abrasive particles fixed by a bonding material. stone; and a polishing step, after the grinding step, pressing the rotating polishing pad while supplying polishing slurry to the back side of the wafer, so as to grind the back side of the wafer until a slight residue is formed by grinding The state of grinding the strained layer is used to generate the defect removal layer. The wafer is a package wafer in which a component chip mounted on a plate-shaped support substrate is covered with molding resin. In this grinding step, the plastic is ground. The mold resin side of the package wafer is polished until the component chip is exposed. In the polishing step, the surface of the mold resin side of the package wafer is polished until it becomes the following state: a slight amount of the component chip remains on the front surface of the component chip exposed after grinding. Grinding the strained layer. 如請求項1之晶圓的加工方法，其更具備研磨條件選定步驟，前述研磨條件選定步驟是為了決定該研磨步驟之研磨條件，而對該磨削步驟實施後的該晶圓進行研磨，並且按該研磨墊之按壓力或研磨時間來測定經研 磨後的該晶圓的該背面側的表面粗糙度，而選定在該研磨步驟中對應於完工的表面粗糙度的研磨條件。 For example, the wafer processing method of claim 1 further includes a grinding condition selection step. The aforementioned grinding condition selection step is to determine the grinding conditions for the grinding step and to grind the wafer after the grinding step is performed, and Measure the grinding force according to the pressing force or grinding time of the polishing pad. The surface roughness of the back side of the wafer after grinding is determined, and the grinding conditions corresponding to the finished surface roughness in the grinding step are selected. 如請求項1或2之晶圓的加工方法，其中在該研磨步驟中，是將該晶圓的背面側研磨成該磨削應變層的表面粗糙度成為超過1nm且在10nm以下。 The wafer processing method of claim 1 or 2, wherein in the grinding step, the back side of the wafer is ground until the surface roughness of the grinding strain layer exceeds 1 nm and is below 10 nm.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200817130A (en) * 2006-09-29 2008-04-16 Sumco Techxiv Corp Rough polishing method of semiconductor wafer and polishing apparatus of semiconductor wafer
TW200945431A (en) * 2008-03-26 2009-11-01 Tokyo Seimitsu Co Ltd Wafer processing method and wafer processing apparatus
TW201606897A (en) * 2014-06-27 2016-02-16 Disco Corp Evaluation method of device wafer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3006249B2 (en) * 1991-12-24 2000-02-07 信越半導体株式会社 Polishing equipment for semiconductor wafers
JP4871617B2 (en) 2006-03-09 2012-02-08 株式会社ディスコ Wafer processing method
JP2009259959A (en) * 2008-04-15 2009-11-05 Sumco Corp Thin silicon wafer and method of manufacturing the same
JP2015053468A (en) * 2013-08-07 2015-03-19 日東電工株式会社 Method for manufacturing semiconductor package
JP6192778B2 (en) 2016-07-07 2017-09-06 株式会社ディスコ Silicon wafer processing equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200817130A (en) * 2006-09-29 2008-04-16 Sumco Techxiv Corp Rough polishing method of semiconductor wafer and polishing apparatus of semiconductor wafer
TW200945431A (en) * 2008-03-26 2009-11-01 Tokyo Seimitsu Co Ltd Wafer processing method and wafer processing apparatus
TW201606897A (en) * 2014-06-27 2016-02-16 Disco Corp Evaluation method of device wafer

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