CN110993494A - Method for processing wafer - Google Patents
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- CN110993494A CN110993494A CN201910903129.6A CN201910903129A CN110993494A CN 110993494 A CN110993494 A CN 110993494A CN 201910903129 A CN201910903129 A CN 201910903129A CN 110993494 A CN110993494 A CN 110993494A
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
Abstract
Provided is a wafer processing method capable of providing defect removal capability while suppressing an increase in required man-hours. The wafer processing method is a processing method for thinning a wafer, wherein the wafer processing method comprises the following steps: a protective member attaching step (ST2) of attaching a protective member to the front surface side of the wafer; a grinding step (ST3) for holding the protective member side of the wafer by the holding surface of the chuck table, and grinding the back surface side of the wafer by a grinding tool obtained by fixing abrasive grains with a bonding material to thin the wafer; and a polishing step (ST4) for, after the grinding step (ST3), pressing a rotating polishing pad against the back surface side of the wafer while supplying slurry to the back surface side of the wafer, and polishing the back surface side of the wafer until a state in which a grinding strain layer formed by grinding is slightly left is obtained, thereby generating a defect removal layer.
Description
Technical Field
The present invention relates to a method of processing a wafer, and more particularly to thinning processing.
Background
With the trend toward thinner, lighter, and smaller electronic devices, semiconductor devices are often required to be thin and small. For example, a memory device stacks a large number of thin device chips to achieve high performance without increasing the size. In order to stack a large number of device chips, it is necessary to increase the bending strength of each device chip, and in order to increase the bending strength of a thin device chip, a processing technique has been developed in which a strained layer of a wafer after grinding is removed by polishing.
However, the processing technique of removing the strain layer due to grinding by lapping causes a new problem as follows: with the removal of the strain layer, the defect removal capability of the device chip disappears, and the device is poor in characteristics due to heavy metal contamination. Therefore, various processing techniques have been considered in which the surface from which the strained layer has been removed by polishing is processed to such an extent that the surface has defect removal performance (see, for example, patent documents 1 and 2).
Patent document 1: japanese patent No. 4871617
Patent document 2: japanese patent No. 6192778
However, the processing techniques disclosed in patent documents 1 and 2 have the following problems: the man-hours required for the processing for making the surface from which the strained layer has been removed by polishing have the ability to remove defects are increased.
Disclosure of Invention
The present invention has been made in view of the above problems, and an object of the present invention is to provide a wafer processing method capable of providing defect removal capability while suppressing an increase in required man-hours.
In order to achieve the object, a method for processing a wafer according to the present invention is a method for processing a wafer to thin the wafer, the method comprising the steps of: a protective member attaching step of attaching a protective member to the front surface side of the wafer; a grinding step of holding the protective member side of the wafer by a holding surface of a chuck table, and grinding and thinning the back surface side of the wafer by a grinding wheel in which abrasive grains are fixed by a bonding material; and a polishing step of, after the grinding step, pressing a rotating polishing pad against the back surface side of the wafer while supplying slurry to the back surface side of the wafer, and polishing the back surface side of the wafer until a state in which a grinding strain layer formed by grinding is slightly left is obtained, thereby generating a defect removal layer.
In the above method for processing a wafer, the method for processing a wafer may further include the step of selecting the polishing conditions as follows: in order to determine the polishing conditions of the polishing step, the wafer after the grinding step is polished, the surface roughness of the back surface side of the polished wafer is measured in accordance with the pressing force of the polishing pad or the polishing time, and the polishing conditions corresponding to the surface roughness to be finished by the polishing step are selected.
In the above-described wafer processing method, in the polishing step, the back surface side of the wafer may be polished so that the surface roughness of the grinding strain layer exceeds 1nm and is 10nm or less.
In the above wafer processing method, the wafer may be a package wafer in which the device chips mounted on the plate-like support substrate are covered with a mold resin, the mold resin side may be ground in the grinding step until the device chips are exposed, and the surface of the package wafer on the mold resin side may be ground in the grinding step until the grinding strain layer is slightly left on the front surfaces of the device chips exposed by the grinding.
The wafer processing method according to the present invention has the following effects: the defect removing capability can be provided while suppressing an increase in required man-hours.
Drawings
Fig. 1 is a perspective view showing an example of a wafer to be processed in a wafer processing method according to embodiment 1.
Fig. 2 is a flowchart showing a flow of a wafer processing method according to embodiment 1.
Fig. 3 is a perspective view illustrating a protective member attaching step of the wafer processing method shown in fig. 2.
Fig. 4 is a perspective view showing a wafer after a protective member attaching step in the wafer processing method shown in fig. 2.
Fig. 5 is a side view showing a grinding step of the processing method of the wafer shown in fig. 2 in a partial cross section.
Fig. 6 is a cross-sectional view of a principal part of a wafer after a grinding step in the method of processing a wafer shown in fig. 2.
Fig. 7 is a side view illustrating a grinding step of the wafer processing method shown in fig. 2.
Fig. 8 is a side view of a principal part of a wafer after a grinding step of the wafer processing method shown in fig. 2.
Fig. 9 is a cross-sectional view of a main portion of a wafer before a step of selecting polishing conditions in the method of processing a wafer shown in fig. 2.
Fig. 10 is a perspective view showing a wafer to be processed in the wafer processing method according to embodiment 2.
Fig. 11 is a sectional view taken along line XI-XI in fig. 10.
Fig. 12 is a perspective view of a processed wafer showing the wafer processing method according to embodiment 2.
Fig. 13 is a sectional view taken along line XIII-XIII in fig. 12.
Fig. 14 is an enlarged view of the XIV region in fig. 13.
Description of the reference symbols
1: a wafer; 1-2: a chip (package chip); 3. 11-1: a front side; 6: a back side; 7: grinding the strain layer; 7-1: removing a defect layer; 11: a support substrate; 12: a molding resin; 12-1: the surface of the molding resin (the back surface of the wafer); 21: a chuck table; 22: a holding surface; 23: grinding the grinding tool; 33: a polishing pad; 200: an adhesive tape (protective member); ST 2: a protective member attaching step; ST 3: grinding; ST 4: grinding; ST 5: and selecting grinding conditions.
Detailed Description
A mode (embodiment) for carrying out the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following embodiments. The components described below include those that can be easily conceived by those skilled in the art, and substantially the same ones. The following structures may be combined as appropriate. Various omissions, substitutions, and changes in the structure may be made without departing from the spirit of the invention.
[ embodiment 1]
A method for processing a wafer according to embodiment 1 of the present invention will be described with reference to the drawings. Fig. 1 is a perspective view showing an example of a wafer to be processed in a wafer processing method according to embodiment 1. Fig. 2 is a flowchart showing a flow of a wafer processing method according to embodiment 1.
The wafer processing method according to embodiment 1 is a processing method for thinning the wafer 1 shown in fig. 1. In embodiment 1, the wafer 1 is a disc-shaped semiconductor wafer or optical device wafer, and silicon, sapphire, gallium arsenide, or the like is used as the substrate 2. As shown in fig. 1 and 2, the wafer 1 has devices 5 formed on the front surface 3 of the substrate 2 in a plurality of regions defined by the grid-shaped lines to divide 4. The device 5 is, for example, an IC (Integrated Circuit) or an LSI (Large scale integration).
The method of processing a wafer according to embodiment 1 is a method of thinning the wafer 1 to a predetermined finished thickness 100. As shown in fig. 2, the wafer processing method according to embodiment 1 includes a holding member attaching step ST2, a grinding step ST3, a polishing step ST4, and a polishing condition selecting step ST 5. In the method of processing a wafer according to embodiment 1, the operator or the like determines whether or not the polishing conditions in the polishing step ST4 have been determined (step ST1), and proceeds to a protective member attaching step ST2 when it is determined that the polishing conditions have been determined (step ST 1: yes). In embodiment 1, the polishing conditions in the polishing step ST4 are determined when a new type of wafer 1 is manufactured.
(protective Member attaching step)
Fig. 3 is a perspective view illustrating a protective member attaching step of the wafer processing method shown in fig. 2. Fig. 4 is a perspective view showing a wafer after a protective member attaching step in the wafer processing method shown in fig. 2.
The protective member attaching step ST2 is a step of attaching the adhesive tape 200 as the protective member to the front surface 3 side of the substrate 2 of the wafer 1. In embodiment 1, as shown in fig. 3, in the protective member attaching step ST2, the adhesive layer of the adhesive tape 200 having the same diameter as that of the wafer 1 is opposed to the front surface 3 side of the substrate 2 of the wafer 1, and then, as shown in fig. 4, the adhesive layer of the adhesive tape 200 is attached to the front surface 3 of the substrate 2 of the wafer 1. In embodiment 1, the adhesive tape 200 having the same diameter as the wafer 1 is used as the protective member, but in the present invention, the protective member is not limited to the adhesive tape 200, and for example, a disk-shaped substrate having the same diameter as the wafer 1 and being hard may be used. When the adhesive tape 200 is attached to the front surface 3 side of the substrate 2 of the wafer 1, the wafer processing method proceeds to the grinding step ST 3.
(grinding step)
Fig. 5 is a side view showing a grinding step of the processing method of the wafer shown in fig. 2 in a partial cross section. Fig. 6 is a cross-sectional view of a principal part of a wafer after a grinding step in the method of processing a wafer shown in fig. 2. The grinding step ST3 is a step of holding the adhesive tape 200 side of the wafer 1 by the holding surface 22 of the chuck table 21 of the grinding apparatus 20 and grinding and thinning the back surface 6 side of the wafer 1 on the opposite side of the front surface 3 by the grinding wheel 23 in which abrasive grains are fixed by a binder.
In the grinding step ST3, the grinding device 20 suctions and holds the front surface 3 side of the wafer 1 on the holding surface 22 of the chuck table 21 via the adhesive tape 200. In the grinding step ST3, as shown in fig. 5, the grinding apparatus 20 supplies the grinding water 26 to the back surface 6 of the wafer 1 while rotating the grinding wheel 25 by the spindle 24 and rotating the chuck table 21 around the axis, and grinds the back surface 6 of the substrate 2 of the wafer 1 by the grinding wheel 23 by bringing the grinding wheel 23 of the grinding wheel 25 close to the chuck table 21 at a predetermined feed speed.
When the wafer 1 is thinned to a predetermined thickness 101 slightly thicker than the finished thickness 100 as shown in fig. 6, the wafer processing method proceeds to a polishing step ST 4. As shown in fig. 6, the wafer 1 after the grinding step ST3 has a grinding strain layer 7 formed on the entire back surface 6 by the grinding process of the grinding step ST 3. The grinding strain layer 7 is a layer in which crystal defects and strain are formed on the surface layer of the back surface 6 of the substrate 2 of the wafer 1, and exhibits a so-called gettering capability of capturing impurities mainly composed of metal such as copper (Cu) attached to the wafer 1 and suppressing metal contamination of the device 5 due to the impurities. The predetermined thickness 101 is preferably a thickness obtained by adding a dimension (hereinafter referred to as a removal amount) 102 in the thickness direction in which the grinding strain layer 7 is removed when the wafer 1 is polished under the polishing conditions determined in the polishing step ST4 to the finished thickness 100.
(grinding step)
Fig. 7 is a side view illustrating a grinding step of the wafer processing method shown in fig. 2. Fig. 8 is a side view of a principal part of a wafer after a grinding step of the wafer processing method shown in fig. 2. The grinding step ST4 is a step of: after the grinding step ST3, the rotating polishing pad 33 of the polishing apparatus 30 is pressed against the back surface 6 of the wafer 1 while supplying slurry to the back surface 6 side, and the back surface 6 side of the wafer 1 is polished until the grinding strain layer 7 formed by grinding is slightly left, thereby producing the defect removal layer 7-1.
In the polishing step ST4, the polishing apparatus 30 sucks and holds the front surface 3 side of the wafer 1 on the holding surface 32 of the chuck table 31 via the adhesive tape 200. In the polishing step ST4, as shown in fig. 7, while the grinding wheel 35 is rotated by the spindle 34 and the chuck table 31 is rotated around the axis, slurry as a polishing liquid is supplied from the slurry supply source 36 through the opening/closing valve 37 and the supply path 38 provided in the grinding wheel 35 or the like to a space between the polishing pad 33 of the grinding wheel 35 and the back surface 6 of the wafer 1, and the polishing pad 33 is brought close to the chuck table 31 at a predetermined feed rate to polish the back surface 6 of the wafer 1 by the polishing pad 33.
In embodiment 1, the polishing apparatus 30 polishes the back surface 6 of the wafer 1 while supplying slurry containing abrasive grains as a polishing liquid in the polishing step ST4, but in the present invention, the back surface 6 of the wafer 1 may be polished using a polishing pad 33 having fixed abrasive grains while supplying pure water as a polishing liquid, or Chemical Mechanical Polishing (CMP) may be performed using the polishing pad 33 while supplying a basic polishing liquid as a polishing liquid.
In the polishing step ST4, the back surface 6 of the wafer 1 is polished under predetermined polishing conditions. In embodiment 1, the polishing conditions are a pressing force for pressing the polishing pad 33 against the back surface 6 of the wafer 1 and a polishing time, and are conditions under which polishing is performed in such a manner that the surface layer of the grinding strain layer 7 is removed by polishing and the grinding strain layer 7 is slightly left and planarized in the polishing step ST4 so that the surface roughness Ra of the back surface 6 of the wafer 1, which is the surface of the grinding strain layer 7, exceeds 1nm and is 10nm or less. That is, in the present invention, "the back surface 6 of the wafer 1 is polished until the grinding strain layer 7 is slightly left" means that the back surface 6 of the wafer 1 is polished so that the surface roughness Ra of the grinding strain layer 7 left after polishing, that is, the surface roughness Ra of the back surface 6 of the wafer 1 exceeds 1nm and is 10nm or less. The surface roughness Ra is a so-called arithmetic average roughness. In this way, in the polishing step ST4, the polishing apparatus 30 thins the grinding strain layer 7, and as shown in fig. 8, polishes the surface of the grinding strain layer 7, that is, the back surface 6 of the substrate 2 of the wafer 1 to form the grinding strain layer 7 into a defect removal layer 7-1 having defect removal capability, and thins the wafer 1 to the finished thickness 100.
In the method of processing a wafer according to embodiment 1, the pressing force of the polishing pad 33 under the processing conditions of the polishing step ST4 is set to 15kPa, and the polishing time is set to 15sec, so that the surface roughness Ra of the back surface 6 of the substrate 2 of the wafer 1, which is the surface of the defect eliminating layer 7-1, is set to 7nm or more and 8nm or less, however, in the present invention, the surface roughness Ra of the back surface 6 of the substrate 2 of the wafer 1, which is the surface of the defect removal layer 7-1, may be set to 4nm or more and 6nm or less by setting the pressing force of the polishing pad 33 to 15kPa and the polishing time to 30sec under the processing conditions of the polishing step ST4, and the surface roughness Ra of the back surface 6 of the substrate 2 of the wafer 1, which is the surface of the defect removal layer 7-1, may be set to 2nm or more and 3nm or less by setting the pressing force of the polishing pad 33 to 15kPa and the polishing time to 60sec under the processing conditions of the polishing step ST 4.
In the method of processing a wafer according to embodiment 1, the polishing pad 33 used in the polishing step ST4 has a diameter of, for example, 450mm, and the polishing pad 33 has a thickness of, for example, 4 mm. In the wafer processing method according to embodiment 1, in the polishing step ST4, the rotation speed of the spindle 34 is, for example, 500rpm, the rotation speed of the chuck table 31 is 505rpm, and the supply amount of the slurry is 0.2L/min. When the back surface 6 of the wafer 1 is polished under the processing conditions in the polishing step ST4, the processing method of the wafer is ended.
When it is determined that the polishing conditions are not determined in the wafer processing method (no in step ST1), the process proceeds to a grinding condition selection step ST 5.
(grinding condition selecting step)
Fig. 9 is a cross-sectional view of a main portion of a wafer before a step of selecting polishing conditions in the method of processing a wafer shown in fig. 2. The polishing condition selection step ST5 is a step of: in order to determine the polishing conditions in the polishing step ST4, the wafer 1 after the grinding step ST3 is polished, the surface roughness Ra of the back surface 6 side of the wafer 1 after polishing is measured in accordance with the pressing force of the polishing pad 33 or the polishing time, and the polishing conditions corresponding to the surface roughness Ra to be finished in the polishing step ST4 are selected.
In the polishing condition selecting step ST5, a plurality of wafers 1 subjected to the polishing step ST3 are prepared, and the polishing conditions for each wafer 1 are made different, and the back surface 6 of the wafer 1 is polished by the polishing apparatus 30 in the same manner as in the polishing step ST4, so that the grinding strain layer 7 is thinned, and the front surface of the grinding strain layer 7, that is, the back surface 6 of the wafer 1 is planarized, and the defect removal layer 7-1 is formed. In the polishing condition selection step ST5, in the wafer after the polishing step ST3 shown in fig. 9, the removal amount 102 and the residual amount (amount obtained by subtracting the removal amount 102 from the thickness 103 of the grinding strain layer 7) 104 of the grinding strain layer 7 differ according to the pressing force of the polishing pad 33 or the polishing time, which are the processing conditions, and the surface roughness Ra of the front surface of the defect removal layer 7-1, that is, the back surface 6 of the wafer 1, after polishing differs. The residual amount 104 is the thickness of the defect-removed layer 7-1 after the polishing step ST 4.
In embodiment 1, the larger the removal amount 102 in the polishing condition selecting step ST5, the smaller the surface roughness Ra of the front surface of the defect removal layer 7-1, that is, the back surface 6 of the wafer 1. In embodiment 1, when the surface roughness Ra of the surface of the defect removal layer 7-1 is increased, the defect removal capability (capability of capturing impurities) of the devices 5 after the division of the wafer 1 is improved, but the flexural strength is lowered.
In the polishing condition selection step ST5, the surface roughness Ra of the back surface 6 of the wafer 1 after polishing is measured in accordance with the pressing force of the polishing pad 33 or the polishing time, and among the plurality of polishing conditions, the processing condition in which the surface roughness Ra of the back surface 6 is the surface roughness to be finished in the polishing step ST4, that is, in the range of more than 1nm and 10nm or less is selected as the processing condition in the polishing step ST 4. In the polishing condition selection step ST5, when there are a plurality of processing conditions in which the surface roughness Ra of the back surface 6 of the wafer 1 after polishing is in the range of more than 1nm and 10nm or less, the processing conditions are selected in consideration of the defect removal capability and the bending strength required for the devices 5 after the division of the wafer 1. When the processing conditions of the grinding step ST4 are selected, the processing method of the wafer proceeds to the protective member attaching step ST 2.
In the method of processing a wafer according to embodiment 1, in the polishing step ST4 after the grinding step ST3 of grinding the back surface 6 of the wafer 1, the removal amount 102 by polishing is set so that the grinding strain layer 7 is not completely removed but the grinding strain layer 7 slightly remains, and then the back surface 6 of the wafer 1 is polished in the polishing step ST 4. Therefore, in the wafer processing method, the wafer 1 is processed in a state where the bending strength is improved and the defect removal layer 7-1 having the defect removal capability is formed, and therefore, the wafer can be effectively thinned and polished. As a result, the wafer processing method has the following effects: it is not necessary to perform a step for imparting defect removing ability after the polishing step ST4, and it is possible to impart defect removing ability to the wafer 1 and the devices 5 singulated from the wafer 1 one by one while suppressing an increase in required man-hours.
In the method of processing a wafer according to embodiment 1, in the polishing condition selection step ST5, a plurality of wafers 1 after the grinding step ST3 are polished in the same manner as in the polishing step ST4 with different processing conditions, and thus appropriate polishing conditions are selected. As a result, in the wafer processing method, it is not necessary to perform a step for imparting defect removal capability after the polishing step ST4, and it is possible to impart defect removal capability and improve flexural strength to the devices 5 singulated from the wafer 1 one by one.
In the method of processing a wafer according to embodiment 1, since the back surface 6 of the wafer 1 is polished in the polishing step ST4 so that the surface roughness Ra of the back surface 6 of the wafer 1, which is the surface of the grinding strain layer 7, exceeds 1nm and is 10nm or less, it is possible to provide the devices 5 singulated from the wafer 1 one by one with the ability to remove defects and to improve the flexural strength without performing a step for providing the ability to remove defects after the polishing step ST 4.
[ embodiment 2]
A method for processing a wafer according to embodiment 1 of the present invention will be described with reference to the drawings. Fig. 10 is a perspective view showing a wafer to be processed in the wafer processing method according to embodiment 2. Fig. 11 is a sectional view taken along line XI-XI in fig. 10. Fig. 12 is a perspective view of a processed wafer showing the wafer processing method according to embodiment 2. Fig. 13 is a sectional view taken along line XIII-XIII in fig. 12. Fig. 14 is an enlarged view of the XIV region in fig. 13. In fig. 10, 11, 12, 13, and 14, the same portions as those in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.
The method of processing a wafer according to embodiment 2 is the same as embodiment 1 except that the target wafer 1-2 is different. As shown in fig. 10 and 11, a wafer 1-2 to be processed in the wafer processing method according to embodiment 2 includes: a plurality of device chips 10; a disc-shaped support substrate 11; and a molding resin 12.
The device chip 10 is manufactured by, for example, dividing the wafer 1 shown in embodiment 1 along the lines to divide 4. The device chip 10 is mounted on the support substrate 11 at equal intervals by overlapping the front surface 3 on which the device 5 is formed on the support substrate 11. In embodiment 2, the support substrate 11 has a wiring layer, not shown, connected to the electrodes of the device chip 10, but the present invention is not limited to this. The mold resin 12 is made of a synthetic resin and covers the plurality of device chips 10 on the support substrate 11. As described above, the wafer 1-2 to be processed in the wafer processing method according to embodiment 2 is a so-called package wafer in which the device chips 10 mounted on the support substrate 11 are covered with the mold resin 12.
The method of processing a wafer according to embodiment 2 includes the protective member sticking step ST2, the grinding step ST3, the polishing step ST4, and the polishing condition selecting step ST5, as in embodiment 1. In the wafer processing method according to embodiment 2, in the protective member attaching step ST2, as shown in fig. 12, an adhesive tape 200 serving as a protective member is attached to the front surface 11-1 side of the support substrate 11 of the wafer 1-2. In the method of processing a wafer according to embodiment 2, in a grinding step ST3, the adhesive tape 200 side of the wafer 1-2 is held by the chuck table 21 of the grinding apparatus 20, the front surface 12-1 of the mold resin 12, which is the back surface of the wafer 1-2, is ground by the grinding wheel 23, and the mold resin 12 is ground until the wafer 1-2 is in a state in which the device chips 10 are exposed on the front surface 12-1 side of the mold resin 12 as shown in fig. 12 and 13, and a grinding strain layer 7 is formed on the back surface 6 of the device chips 10 on the opposite side to the front surface 3.
In the method of processing a wafer according to embodiment 2, in the polishing step ST4, while slurry is supplied to the front surface 12-1 of the mold resin 12 of the wafer 1-2 and the back surface 6 of the device chip 10 exposed by grinding, the back surface 6 and the front surface 12-1 on the mold resin 12 side of the wafer 1-2 are polished in the same manner as in embodiment 1 until the grinding strained layer 7 is slightly left, and as shown in fig. 14, a desmear layer 7-1 having the same surface roughness Ra as that of embodiment 1 is formed on the back surface 6 of the device chip 10.
In the same manner as in embodiment 1, in the method for processing a wafer according to embodiment 2, the removal amount 102 by polishing is set so that the grinding strain layer 7 is not completely removed but the grinding strain layer 7 slightly remains in the polishing step ST4 after the polishing step ST3 of polishing the back surface 6 of each device chip 10 of the wafer 1-2, and then the back surface 6 of the wafer 1-2 is polished in the polishing step ST 4. As a result, the wafer processing method according to embodiment 2 achieves the following effects in the same manner as embodiment 1: the step of imparting defect removing ability after the polishing step ST4 is not required, and the defect removing ability can be imparted to the wafer 1-2 and the device chips 10 including the devices 5 obtained by singulating the wafer 1-2 one by one while suppressing an increase in required man-hours.
In the method of processing a wafer according to embodiment 2, since the grinding strain layer 7 is polished in the polishing step ST4 so that the grinding strain layer 7 is not completely removed but the grinding strain layer 7 is slightly left, and the remaining grinding strain layer 7 becomes the defect removal layer 7-1, the defect removal layer 7-1 can be formed on the device chip 10 while suppressing the man-hours required for processing the wafer 1-2, which is a packaged wafer in which the device chip 10 disposed on the support substrate 11 is coated with the mold resin 12 in particular.
Next, the inventors of the present invention confirmed the effect of the wafer processing method of the present invention. The results are shown in Table 1.
[ TABLE 1]
| Pressing force | Grinding time | Surface roughness Ra | Capacity of removing defects | Bending strength | |
| Comparative example 1 | 25kPa | 2min | 1nm or less | × | ○ |
| |
15kPa | 60sec | 2nm～3nm | ○ | ○ |
| |
15kPa | 30sec | 4nm～6nm | ○ | ○ |
| |
15kPa | 15sec | 7nm～8nm | ○ | ○ |
| Comparative example 2 | 15kPa | 5sec | Over 10nm | ○ | × |
In table 1, the inventors of the present invention polished a plurality of wafers 1 after the grinding step ST3 in the same manner as the polishing step ST4 with different grinding conditions to produce comparative example 1, comparative example 2, inventive product 1, inventive product 2, and inventive product 3. The inventors of the present invention confirmed the surface roughness Ra, defect removal ability, and bending strength after division of the surface of the defect removal layer 7-1, which is the residual grinding strain layer 7, in comparative example 1, comparative example 2, present invention product 1, present invention product 2, and present invention product 3, respectively. In comparative examples 1 and 2, invention products 1 and 2, and invention products 3 in table 1, the surface roughness Ra of the surface of the grinding strained layer 7 of the wafer 1 after the grinding step ST3 was about 10 nm.
In the polishing conditions of comparative example 1, the pressing force of the polishing pad 33 was set to 25kPa, and the polishing time was set to 2 min. In the polishing conditions of comparative example 2, the pressing force of the polishing pad 33 was set to 15kPa, and the polishing time was set to 5 sec. In the polishing conditions of the present invention product 1, the pressing force of the polishing pad 33 was set to 15kPa, and the polishing time was set to 60 sec. In the polishing conditions of the present invention product 2, the pressing force of the polishing pad 33 was set to 15kPa, and the polishing time was set to 30 sec. In the polishing conditions of the present invention product 3, the pressing force of the polishing pad 33 was set to 15kPa, and the polishing time was set to 15 sec.
The surface roughness Ra of the surface of the defect removal layer 7-1 of comparative example 1 was 1nm or less, and the surface roughness Ra of the surface of the defect removal layer 7-1 of comparative example 2 was more than 10 nm. The surface roughness Ra of the front surface of the defect removal layer 7-1 of the present invention product 1 was 2nm to 3nm, the surface roughness Ra of the front surface of the defect removal layer 7-1 of the present invention product 2 was 4nm to 6nm, and the surface roughness Ra of the front surface of the defect removal layer 7-1 of the present invention product 3 was 7nm to 8 nm.
In table 1, device chips that were singulated one by one and had the required defect removal capability are denoted by "○", and device chips that did not have the required defect removal capability are denoted by "x", and in table 1, device chips that were singulated one by one and had the required flexural strength are denoted by "○", and device chips that did not have the required flexural strength are denoted by "x".
From table 1, the defect removing ability of comparative example 1 is "x", whereas the defect removing ability of the present invention products 1, 2 and 3 is "○", from table 1, it is understood that the required defect removing ability can be imparted by polishing the wafers 1, 1-2 after the grinding step ST3 in the polishing step ST4 so that the surface roughness Ra of the surface of the defect removing layer 7-1 of the remaining grinding strain layer 7 exceeds 1nm and is 10nm or less.
Further, from table 1, the bending strength of comparative example 2 is "x", and on the other hand, the bending strength of invention products 1, 2 and 3 is "○", and thus, it is understood from table 1 that the wafers 1 and 1-2 after the grinding step ST3 are polished in the polishing step ST4 so that the surface roughness Ra of the surface of the defect removal layer 7-1 of the remaining grinding strain layer 7 exceeds 1nm and is 10nm or less, and thereby, it is understood from table 1 that both the required defect removal capability and the required bending strength can be imparted by polishing the wafers 1 and 1-2 after the grinding step ST3 in the polishing step ST4 so that the surface roughness Ra of the surface of the defect removal layer 7-1 exceeds 1nm and is 10nm or less, and it is possible to achieve both the defect removal capability and the improvement of the bending strength while the defect removal capability is imparted after the polishing step ST 4.
The present invention is not limited to the above embodiments. That is, various modifications can be made and implemented without departing from the scope of the present invention.
Claims (4)
1. A method for processing a wafer, thinning the wafer, wherein,
the processing method of the wafer comprises the following steps:
a protective member attaching step of attaching a protective member to the front surface side of the wafer;
a grinding step of holding the protective member side of the wafer by a holding surface of a chuck table, and grinding and thinning the back surface side of the wafer by a grinding wheel in which abrasive grains are fixed by a bonding material; and
and a polishing step of, after the grinding step, pressing a rotating polishing pad against the back surface side of the wafer while supplying slurry to the back surface side of the wafer, and polishing the back surface side of the wafer until a state in which a grinding strain layer formed by grinding is slightly left is obtained, thereby generating a defect removal layer.
2. The method of processing a wafer according to claim 1,
the wafer processing method also comprises the following steps of selecting grinding conditions: in order to determine the polishing conditions of the polishing step, the wafer after the grinding step is polished, the surface roughness of the back surface side of the polished wafer is measured in accordance with the pressing force of the polishing pad or the polishing time, and the polishing conditions corresponding to the surface roughness to be finished by the polishing step are selected.
3. The method of processing a wafer according to claim 1 or 2,
in the polishing step, the back surface side of the wafer is polished so that the surface roughness of the grinding strain layer exceeds 1nm and is 10nm or less.
4. The method of processing a wafer according to any one of claims 1 to 3,
the wafer is a packaged wafer obtained by covering a device chip mounted on a plate-like support substrate with a molding resin,
in the grinding step, the mold resin side is ground until the device chip is exposed,
in the polishing step, the surface of the package wafer on the mold resin side is polished until the grinding strain layer slightly remains on the front surface of the device chip exposed by the grinding.
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| JP2018-188268 | 2018-10-03 | ||
| JP2018188268A JP7175698B2 (en) | 2018-10-03 | 2018-10-03 | Wafer processing method |
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| CN110993494A true CN110993494A (en) | 2020-04-10 |
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| JP (1) | JP7175698B2 (en) |
| KR (1) | KR20200038424A (en) |
| CN (1) | CN110993494A (en) |
| TW (1) | TWI818091B (en) |
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| CN114161258A (en) * | 2021-12-10 | 2022-03-11 | 中国电子科技集团公司第四十六研究所 | Edge grinding method for preventing gallium oxide wafer from being cleaved |
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| CN114393497B (en) * | 2022-01-27 | 2023-12-19 | 江门市鸿华金属制品有限公司 | Polishing device for stainless steel products |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3006249B2 (en) * | 1991-12-24 | 2000-02-07 | 信越半導体株式会社 | Polishing equipment for semiconductor wafers |
| JP4871617B2 (en) | 2006-03-09 | 2012-02-08 | 株式会社ディスコ | Wafer processing method |
| JP5060755B2 (en) * | 2006-09-29 | 2012-10-31 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Semiconductor wafer rough polishing method and semiconductor wafer polishing apparatus |
| JP2009238853A (en) * | 2008-03-26 | 2009-10-15 | Tokyo Seimitsu Co Ltd | Wafer processing method and wafer processing apparatus |
| JP2009259959A (en) * | 2008-04-15 | 2009-11-05 | Sumco Corp | Thin silicon wafer and method of manufacturing the same |
| JP2015053468A (en) * | 2013-08-07 | 2015-03-19 | 日東電工株式会社 | Method for manufacturing semiconductor package |
| JP6410490B2 (en) * | 2014-06-27 | 2018-10-24 | 株式会社ディスコ | Device wafer evaluation method |
| JP6192778B2 (en) | 2016-07-07 | 2017-09-06 | 株式会社ディスコ | Silicon wafer processing equipment |
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- 2019-09-24 CN CN201910903129.6A patent/CN110993494A/en active Pending
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| CN114161258A (en) * | 2021-12-10 | 2022-03-11 | 中国电子科技集团公司第四十六研究所 | Edge grinding method for preventing gallium oxide wafer from being cleaved |
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| KR20200038424A (en) | 2020-04-13 |
| TWI818091B (en) | 2023-10-11 |
| JP2020057710A (en) | 2020-04-09 |
| JP7175698B2 (en) | 2022-11-21 |
| TW202015121A (en) | 2020-04-16 |
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