TWI812987B - 晶片之測試墊結構 - Google Patents

晶片之測試墊結構 Download PDF

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TWI812987B
TWI812987B TW110128415A TW110128415A TWI812987B TW I812987 B TWI812987 B TW I812987B TW 110128415 A TW110128415 A TW 110128415A TW 110128415 A TW110128415 A TW 110128415A TW I812987 B TWI812987 B TW I812987B
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Taiwan
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test
extended
test pads
pads
test pad
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TW110128415A
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TW202210843A (zh
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曾國瑋
陳柏琦
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矽創電子股份有限公司
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Publication of TW202210843A publication Critical patent/TW202210843A/zh
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Abstract

本發明提供一種晶片之測試墊結構，其包含複數個第一內測試墊、複數個第二內測試墊、複數個第一延伸測試墊與複數個第二延伸測試墊，該些個第一內測試墊與該些個第二內測試墊設置於一晶片，該些個第二內測試墊與該些個第一內測試墊之間具有一距離，該些個第一延伸測試墊連接該些個第一內測試墊，該些個第二延伸測試墊連接該些個第二內測試墊。該些個第一延伸測試墊與該些個第二延伸測試墊增加可被探針接觸的面積，探針透過該些個第一延伸測試墊與該些個第二延伸測試墊傳遞訊號或者電源至該些個第一內測試墊與該些個第二內測試墊，以測試晶片。

Description

晶片之測試墊結構
本發明是關於一種晶片之測試墊結構，尤其係指一種能確保探針接觸測試墊之結構。
隨著時代的發展，晶片設計公司依照客戶的需求及產品的功能，設計相關的電路與電路佈局，並提供給晶圓廠以生產晶片。晶片被製造而尚未從晶圓被切割下來前，為了確定晶圓上之晶片之電路的功能是否可以正常運作而進行預期的功能，晶圓須進行晶片針測（Chip Probing, CP）以確保每一晶片的品質。
接續上述，測試晶圓之檢測裝置具有探針卡（Probe Card），探針卡具有複數探針，該些探針會接觸晶片之測試墊，以傳遞訊號或者電源至晶片，以測試晶片是否可以正常運作。
請參閱第1圖，其為習知測試墊結構的剖視示意圖。如圖所示，一晶圓70包含有複數個晶片80，每一個晶片80包含複數個測試墊82與複數個開孔84，該些個測試墊82位於晶片80內，該些個開孔84對應於該些個測試墊82，並連通於該些個測試墊82與晶片80之表面。一檢測裝置40之兩探針42會進入該些個開孔84，而接觸該些個測試墊82，以傳遞訊號或者電源至晶片80，而測試晶片80。然而，基於製程誤差，例如蝕刻誤差、光罩對位誤差等，可能會導致開孔84之截面積接近等於探針42之截面積，如此探針42不易進入開孔84，而不易接觸測試墊82或者沒有確實接觸測試墊82，如此會降低測試品質。此外，甚至開孔84之截面積小於探針42之截面積，如此探針42無法進入開孔84，而無法接觸測試墊82，即無法測試晶片80。此外，若開孔84所在位置有所偏離，左右相鄰之兩開孔84間之距離會偏離一預定距離，如此兩探針42即無法同時對位到左右相鄰之兩開孔84，而無法進入開孔84，即無法測試晶片80。
基於上述可知，習知測試墊結構會影響檢測裝置之測試品質，甚至導致檢測裝置無法測試晶片。因此，產業界需要一種確保探針能確實接觸晶片之測試墊的結構，以提高測試品質。
本發明之一目的在於提供一種晶片之測試墊結構，其包含複數個內測試墊與複數個延伸測試墊，該些個延伸測試墊連接該些個內測試墊，以增加可被探針接觸的面積，如此探針可以確實接觸延伸測試墊，透過延伸測試墊傳輸訊號或者電源至內測試墊，以測試晶片，如此即可提高測試品質。
本發明之一目的在於提供一種晶片之測試墊結構，其可被探針接觸的面積增加，探針因磨損而截面積變大時，探針仍可接觸到測試墊結構，而不需要更換探針，如此可增加探針的使用壽命，可以降低測試成本。
本發明之一目的在於提供一種晶片之測試墊結構，其可被探針接觸的面積增加而具有較大的對位範圍，便於探針對位，可以改善探針不易對位情況。
本發明提供一種晶片之測試墊結構，其包含複數個第一內測試墊、複數個第二內測試墊、複數個第一延伸測試墊、複數個第二延伸測試墊。該些個第一內測試墊與該些個第二內測試墊設置於一晶片，且該些個第二內測試墊與該些個第一內測試墊之間具有一距離。該些個第一延伸測試墊與該些個第二延伸測試墊設置於晶片，該些個第一延伸測試墊連接該些個第一內測試墊，且位於該些個第一內測試墊上方，該些個第二延伸測試墊連接該些個第二內測試墊，且位於該些個第二內測試墊上方。該些個第一延伸測試墊與該些個第二延伸測試墊增加可被探針接觸的面積，探針可以確實接觸該些個第一延伸測試墊與該些個第二延伸測試墊，而透過該些個第一延伸測試墊與該些個第二延伸測試墊傳輸訊號或者電源至該些個第一內測試墊與該些個第二內測試墊，以測試晶片。
為使　貴審查委員對本發明之特徵及所達成之功效有更進一步之瞭解與認識，謹佐以實施例及配合說明，說明如後：
請參閱第2圖及第3圖，第2圖與第3圖分別為本發明之晶片之測試墊結構之第一實施例之俯視示意圖與剖視示意圖。如圖所示，一晶圓1包含複數個晶片10與複數條切割道50，該些條切割道50位於該些個晶片10之間。切割裝置可沿著切割道50切割晶圓1，以取得該些個晶片10。
再次參閱第2圖及第3圖，以及請參閱第4A圖，第4A圖為第3圖之局部放大示意圖。本發明之測試墊結構包含複數個第一內測試墊14、複數個第二內測試墊16、複數個第一延伸測試墊20以及複數個第二延伸測試墊30，其皆設置於晶片10。於一實施例中，該些個第一內測試墊14與該些個第二內測試墊16位於晶片10內，該些個第一內測試墊14位於晶片10之一第一側，該些個第二內測試墊16位於晶片10之一第二側。該些個第一內測試墊14具有一第一側面141與一第二側面143，該些個第二內測試墊16具有一第一側面161與一第二側面163，第二側面143與第二側面163相對，且兩者之間具有一距離D0，其表示該些個第一內測試墊14與該些個第二內測試墊16之間具有距離D0。該些個第一延伸測試墊20分別連接該些個第一內測試墊14，並位於該些個第一內測試墊14上方。該些個第二延伸測試墊30分別連接該些個第二內測試墊16，並位於該些個第二內測試墊16上方。
再次參閱第2圖及第4A圖。於本實施例中，晶片10包含複數個第一穿孔15與複數個第二穿孔17，該些個第一穿孔15對應該些個第一內測試墊14，且位於該些個第一內測試墊14之上方，該些個第二穿孔17對應該些個第二內測試墊16，且位於其上方。該些個第一延伸測試墊20各別包含一第一本體22以及一第一連接件24，第一本體22位於晶片10之表面，第一連接件24插設於第一穿孔15，且第一連接件24連接第一本體22與第一內測試墊14。該些個第二延伸測試墊30與該些個第一延伸測試墊20之間具有一距離，該些個第二延伸測試墊30各別包含一第二本體32以及一第二連接件34，第二本體32位於晶片10之表面，第二連接件34插設於第二穿孔17，且第二連接件34連接第二本體32與第二內測試墊16。
於本實施例中，第一本體22往靠近第二本體32之方向延伸，其表示第一延伸測試墊20往靠近第二延伸測試墊30之方向延伸。第二本體32往靠近第一本體22之方向延伸，其表示第二延伸測試墊30往靠近第一延伸測試墊20之方向延伸。如第4A圖所示，第一內測試墊14之第二側面143相較於第一內測試墊14之第一側面141較遠離晶片10之第一側面11。第一延伸測試墊20之第一本體22具有一第一側面221與一第二側面223，第二側面223相較於第一側面221較遠離晶片10之第一側面11。第一內測試墊14之第二側面143與晶片10之第一側面11之間具有一距離D4，第一延伸測試墊20之第二側面223與晶片10之第一側面11之間具有一距離D5，且距離D5大於距離D4。第二內測試墊16之第二側面163相較於第二內測試墊16之第一側面161較遠離晶片10之第二側面13。第二延伸測試墊30之第二本體32具有一第一側面321與一第二側面323，第二側面323相較於第一側面321較遠離晶片10之第二側面13，且第二側面323相對於第二側面223。第二內測試墊16之第二側面163與晶片10之第二側面13之間具有一距離D6，第二延伸測試墊30之第二側面323與晶片10之第二側面13之間具有一距離D7，且距離D7大於距離D6。
再次參閱第4A圖，第一內測試墊14之第一側面141與晶片10之第一側面11之間具有一距離D8，第一延伸測試墊20之第一側面221與晶片10之第一側面11之間具有一距離D9，且距離D9小於距離D8，其表示第一延伸測試墊20亦往遠離第二延伸測試墊30之方向延伸。第二內測試墊16之第一側面161與晶片10之第二側面13之間具有一距離D10，第二延伸測試墊30之第一側面321與晶片10之第二側面13之間具有一距離D11，且距離D11小於距離D10，其表示第二延伸測試墊30亦往遠離第一延伸測試墊20之方向延伸。
如第4A圖所示，第一穿孔15以及第二穿孔17各別具有一孔徑D1，代表第一穿孔15以及第二穿孔17之開口大小。第一內測試墊14與第二內測試墊16各別具有一長度D2，第一內測試墊14之長度與第二內測試墊16之長度亦可不同。第一本體22以及第二本體32各別具有一長度D3，且長度D3大於孔徑D1與長度D2，其表示第一本體22之上表面之面積，也就是第一延伸測試墊20之表面的面積，大於第一穿孔15之開口面積以及第一內測試墊14之表面之面積（如第3圖所示）；同樣地，第二本體32之上表面之面積，也就是第二延伸測試墊30之表面的面積，大於第二穿孔17之開口面積以及第二內測試墊16之表面之面積（如第3圖所示）。於一實施例中，第一本體22之長度與第二本體32之長度亦可不同。此外，如第2圖所示，第一內測試墊14與第二內測試墊16各別具有一寬度W1。第一內測試墊14之寬度與第二內測試墊16之寬度亦可不同。第一本體22以及第二本體32各別具有一寬度W2，且寬度W2大於寬度W1。於一實施例中，寬度W2可等於寬度W1，且第一本體22之寬度與第二本體32之寬度亦可不同。
再次參閱第2圖及參閱第4B圖，第4B圖同於第4A圖為第3圖之局部放大示意圖。如圖所示，一檢測裝置40用於檢測晶片10，檢測裝置40包含二探針42，二探針42可接觸第一延伸測試墊20之第一本體22及第二延伸測試墊30之第二本體32。第一穿孔15及第二穿孔17之間具有一距離D12，第一延伸測試墊20之第一側面221與第二延伸測試墊30之第一側面321之間具有一第一測試距離D13，第一延伸測試墊20之第二側面223與第二延伸測試墊30之第二側面323之間具有一第二測試距離D14，第一測試距離D13大於第二測試距離D14。二探針42之間具有一探針距離D15。本實施例中，距離D12及第二測試距離D14小於探針距離D15，第一測試距離D13大於探針距離D15。二探針42能接觸第一延伸測試墊20及第二延伸測試墊30之表面，而透過第一延伸測試墊20與第二延伸測試墊30傳輸訊號或者電源至第一內測試墊14與第二內測試墊16，以檢測晶片10。
由上述說明可知，探針42不需進入穿孔15、17，僅接觸第一延伸測試墊20與第二延伸測試墊30，即可測試晶片10，其相當於增加可被探針42接觸的面積。此外，第一延伸測試墊20與第二延伸測試墊30之面積可大於第一內測試墊14與第二內測試墊16之面積，如此更提高可被探針42接觸的面積。另外，第一延伸測試墊20與第二延伸測試墊30可被探針42接觸的面積大，相當於具有較大的對位範圍，如此便於探針42對位，縱使探針42長時間使用下，兩探針42間之探針距離D15變大或者變小仍可對位第一延伸測試墊20與第二延伸測試墊30，而可不需要更換探針42，又探針42因磨損而截面積變大時，探針42仍可確實接觸第一延伸測試墊20與第二延伸測試墊30，不需要更換探針42，如此可增加探針42的使用壽命，可以降低測試成本。
請參閱第5圖、第6圖及第7圖，第5圖與第6圖分別為本發明之晶片之測試墊結構之第二實施例之俯視示意圖與剖視示意圖；第7圖為第6圖的局部放大示意圖。如圖所示，第一延伸測試墊20之第一本體22往遠離第二延伸測試墊30之方向延伸，且可延伸出晶片10至切割道50，進一步增加第一本體22之面積，同理第二延伸測試墊30之第二本體32往遠離第一延伸測試墊20之方向延伸，且可延伸出晶片10至切割道50，增加第二本體32之面積。
請參閱第8圖，其為本發明之晶片之測試墊結構被移除部分延伸測試墊之一實施例之剖視示意圖。檢測裝置檢測完位於晶圓1之該些個晶片10後，可移除第一延伸測試墊20之第一本體22之一部分與第二延伸測試墊30之第二本體32之一部分。如此，從晶圓1被切割下來的該些個晶片10仍保留第一延伸測試墊20與第二延伸測試墊30，而可進行測試。於另一實施例中，可完全移除第一延伸測試墊20與第二延伸測試墊30，即完全移除第一本體22、第一連接件24、第二本體32及第二連接件34。於一實施例中，第一延伸測試墊20與第二延伸測試墊30之材料可不同於第一內測試墊14與第二內測試墊16之材料，如此可利用特定蝕刻劑移除第一延伸測試墊20與第二延伸測試墊30而不會移除第一內測試墊14與第二內測試墊16。
綜上所述，本發明提供一種晶片之測試墊結構，其包含延伸測試墊，而連接內測試墊，如此探針接觸延伸測試墊就可透過延伸測試墊傳輸訊號或電源至內測試墊，以測試晶片。
故本發明實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出發明專利申請，祈  鈞局早日賜准專利，至感為禱。
惟以上所述者，僅為本發明一實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
1:晶圓 10:晶片 11:第一側面 13:第二側面 14:第一內測試墊 141:第一側面 143:第二側面 15:第一穿孔 16:第二內測試墊 161:第一側面 163:第二側面 17:第二穿孔 20:第一延伸測試墊 22:第一本體 221:第一側面 223:第二側面 24:第一連接件 30:第二延伸測試墊 32:第二本體 321:第一側面 323:第二側面 34:第二連接件 40:檢測裝置 42:探針 50:切割道 70:晶圓 80:晶片 82:測試墊 84:開孔 D0:距離 D1:孔徑 D2:長度 D3:長度 D4:距離 D5:距離 D6:距離 D7:距離 D8:距離 D9:距離 D10:距離 D11:距離 D12:距離 D13:第一測試距離 D14:第二測試距離 D15:探針距離 W1:寬度 W2:寬度
第1圖：其為習知測試墊結構的剖視示意圖； 第2圖：其為本發明之晶片之測試墊結構之第一實施例之俯視示意圖； 第3圖：其為本發明之晶片之測試墊結構之第一實施例之剖視示意圖； 第4A圖及第4B圖：其為第3圖之局部放大示意圖； 第5圖：其為本發明之晶片之測試墊結構之第二實施例之俯視示意圖； 第6圖：其為本發明之晶片之測試墊結構之第二實施例之剖視示意圖； 第7圖：其為第6圖之局部放大示意圖；以及 第8圖：其為本發明之晶片之測試墊結構被移除部分延伸測試墊之一實施例之剖視示意圖。
10:晶片
11:第一側面
13:第二側面
14:第一內測試墊
141:第一側面
143:第二側面
15:第一穿孔
16:第二內測試墊
161:第一側面
163:第二側面
17:第二穿孔
20:第一延伸測試墊
22:第一本體
221:第一側面
223:第二側面
24:第一連接件
30:第二延伸測試墊
32:第二本體
321:第一側面
323:第二側面
34:第二連接件
40:檢測裝置
42:探針
D0:距離
D1:孔徑
D2:長度
D3:長度
D4:距離
D5:距離
D6:距離
D7:距離
D8:距離
D9:距離
D10:距離
D11:距離

Claims (17)

  1. 一種晶片之測試墊結構，其包含：複數個第一內測試墊，其設置於一晶片；複數個第二內測試墊，其設置於該晶片，並與該些個第一內測試墊之間具有一距離；複數個第一延伸測試墊，其設置於該晶片之表面，並連接該些個第一內測試墊，且位於該些個第一內測試墊上方；以及複數個第二延伸測試墊，其設置於該晶片之表面，並連接該些個第二內測試墊，且位於該些個第二內測試墊上方；其中，該些個第一延伸測試墊與該些個第二延伸測試墊傳遞一訊號或者一電源至該些個第一內測試墊與該些個第二內測試墊。
  2. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊之一表面之面積大於該些個第一內測試墊之一表面之面積。
  3. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊之一表面之面積大於該些個第二內測試墊之一表面之面積。
  4. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊之一長度大於該些個第一內測試墊之一長度。
  5. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊之一長度大於該些個第二內測試墊之一長度。
  6. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊之一寬度等於或大於該些個第一內測試墊之一寬度。
  7. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊之一寬度等於或大於該些個第二內測試墊之一寬度。
  8. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊往靠近該些個第二延伸測試墊之方向延伸。
  9. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊往靠近該些個第一延伸測試墊之方向延伸。
  10. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊往遠離該些個第二延伸測試墊之方向延伸。
  11. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊往遠離該些個第一延伸測試墊之方向延伸。
  12. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊之一側面與該晶片之一側面之間的一距離小於該些個第一內測試墊之一側面與該晶片之該側面之間的一距離。
  13. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊之一側面與該晶片之一側面之間的一距離小於該些個第二內測試墊之一側面與該晶片之該側面之間的一距離。
  14. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊或/及該些個第二延伸測試墊延伸出該晶片，該些個第一內測試墊及該些個第二內測試墊位於該晶片內。
  15. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊具有一第一側面與一第二側面，該些個第二延伸測試墊具有一第一側面與一第二側面，該些個第一延伸測試墊之 該第二側面相對於該些個第二延伸測試墊之該第二側面，該些個第一延伸測試墊之該第一側面與該些個第二延伸測試墊之該第一側面之間具有一第一測試距離，該些個第一延伸測試墊之該第二側面與該些個第二延伸測試墊之該第二側面之間具有一第二測試距離，該第一測試距離大於該第二測試距離，一檢測裝置包含二探針，該二探針之間具有一探針距離，該第一測試距離大於該探針距離，該第二測試距離小於該探針距離。
  16. 如請求項1所述之晶片之測試墊結構，其中該些個第一延伸測試墊各別包含：一第一本體；以及一第一連接件，其連接該第一本體與該第一內測試墊。
  17. 如請求項1所述之晶片之測試墊結構，其中該些個第二延伸測試墊各別包含：一第二本體；以及一第二連接件，其連接該第二本體與該第二內測試墊。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
JP2022160388A (ja) * 2021-04-06 2022-10-19 シトロニックス テクノロジー コーポレーション ウェハのバンプ構造

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0375531U (zh) * 1989-11-27 1991-07-29
US20010000013A1 (en) * 1999-03-01 2001-03-15 Mou-Shiung Lin High performance sub-system design and assembly
JP2005294626A (ja) * 2004-04-01 2005-10-20 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
TW200617398A (en) * 2004-11-23 2006-06-01 Taiwan Semiconductor Mfg Co Ltd Improved test pad and probe card for wafer acceptance testing and other applications
TW200622273A (en) * 2004-12-16 2006-07-01 Nanya Technology Corp Method for measuring the resistance of deep trench capacitor
JP2007501522A (ja) * 2003-08-05 2007-01-25 フリースケール セミコンダクター インコーポレイテッド 検査パッド構造を有する集積回路および検査方法
TW202004881A (zh) * 2018-03-08 2020-01-16 台灣積體電路製造股份有限公司 晶圓結構及封裝方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55141949U (zh) 1979-03-29 1980-10-11
TW479304B (en) * 2001-02-06 2002-03-11 Acer Display Tech Inc Semiconductor apparatus and its manufacturing method, and liquid crystal display using semiconductor apparatus
JP2003273490A (ja) * 2002-03-12 2003-09-26 Sharp Corp 基板接合構造及びそれを備えた電子装置
JP2005228871A (ja) * 2004-02-12 2005-08-25 Seiko Epson Corp 実装構造体、電気光学装置及び電子機器
TWI243386B (en) * 2004-02-26 2005-11-11 Au Optronics Corp Anisotropic conductive film pad
JP4067502B2 (ja) * 2004-03-11 2008-03-26 シャープ株式会社 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置
JP2008135468A (ja) * 2006-11-27 2008-06-12 Nec Lcd Technologies Ltd 半導体素子及び該半導体素子を備える表示装置
BRPI1012742A2 (pt) * 2009-06-16 2019-09-24 Sharp Kk "chip semicondutor módulo de cristal líquido e estrutura de montagem do chip semicondutor"
TW201117336A (en) * 2009-11-05 2011-05-16 Raydium Semiconductor Corp Electronic chip and substrate providing insulation protection between conducting nodes
US8405414B2 (en) * 2010-09-28 2013-03-26 Advanced Inquiry Systems, Inc. Wafer testing systems and associated methods of use and manufacture
US9224669B2 (en) * 2011-08-09 2015-12-29 Alpha And Omega Semiconductor Incorporated Method and structure for wafer level packaging with large contact area
JP2014053597A (ja) * 2012-08-09 2014-03-20 Hitachi Chemical Co Ltd チップ型電子部品及び接続構造体
KR20140128739A (ko) * 2013-04-29 2014-11-06 삼성디스플레이 주식회사 도전성 입자 및 이를 포함하는 표시 장치
JP5976055B2 (ja) * 2014-08-21 2016-08-23 力晶科技股▲ふん▼有限公司 半導体ウエハ、半導体チップ及び半導体装置とそれらの製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0375531U (zh) * 1989-11-27 1991-07-29
US20010000013A1 (en) * 1999-03-01 2001-03-15 Mou-Shiung Lin High performance sub-system design and assembly
JP2007501522A (ja) * 2003-08-05 2007-01-25 フリースケール セミコンダクター インコーポレイテッド 検査パッド構造を有する集積回路および検査方法
JP2005294626A (ja) * 2004-04-01 2005-10-20 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
TW200617398A (en) * 2004-11-23 2006-06-01 Taiwan Semiconductor Mfg Co Ltd Improved test pad and probe card for wafer acceptance testing and other applications
TW200622273A (en) * 2004-12-16 2006-07-01 Nanya Technology Corp Method for measuring the resistance of deep trench capacitor
TW202004881A (zh) * 2018-03-08 2020-01-16 台灣積體電路製造股份有限公司 晶圓結構及封裝方法

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