TWI804955B - 電晶體及其形成方法 - Google Patents
電晶體及其形成方法 Download PDFInfo
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- TWI804955B TWI804955B TW110130950A TW110130950A TWI804955B TW I804955 B TWI804955 B TW I804955B TW 110130950 A TW110130950 A TW 110130950A TW 110130950 A TW110130950 A TW 110130950A TW I804955 B TWI804955 B TW I804955B
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本揭露提供一種電晶體及其形成方法。在一個實施例中,此方法包括:在源極/汲極區及閘極遮罩上沉積保護層,閘極遮罩佈置在閘極結構上,閘極結構佈置在基板的通道區上,通道區鄰接源極/汲極區;蝕刻穿過保護層的開口,開口曝光源極/汲極區;在開口中及保護層上沉積金屬;對金屬進行退火以在源極/汲極區上形成金屬-半導體合金區;及用清洗製程移除開口中的金屬的殘留物,在清洗製程期間保護層覆蓋閘極遮罩。
Description
本揭露關於一種電晶體及其形成方法。
半導體裝置用於各種電子應用,諸如個人電腦、手機、數位相機、及其他電子設備。半導體裝置通常係藉由在半導體基板上順序沉積材料的絕緣或介電層、導電層、及半導體層,及使用微影術圖案化各種材料層以在其上形成電路組件及元件來製造的。
半導體行業藉由不斷減小最小特徵尺寸來不斷提高各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度,從而允許更多組件整合至給定面積中。然而,隨著最小特徵尺寸的減小,出現了需要解決的其他問題。
根據本揭露的一些實施例中,一種形成電晶體之方法,其包含以下步驟。在一源極/汲極區及一閘極遮罩上沉積一保護層,該閘極遮罩佈置在一閘極結構上,該閘極結構佈置在一基板的一通道區上,該通道區鄰接該源極/汲極
區;蝕刻穿過該保護層的一開口,該開口曝光該源極/汲極區;在該開口中及該保護層上沉積一金屬;對該金屬進行退火以在該源極/汲極區上形成一金屬-半導體合金區;及用一清洗製程自該開口移除該金屬的殘留物,在該清洗製程期間該保護層覆蓋該閘極遮罩。
根據本揭露的一些實施例中,一種形成電晶體之方法,其包含以下步驟。在一源極/汲極區上沉積一接觸蝕刻停止層(CESL);在該CESL上形成一層間介電質(ILD);形成穿過該ILD及該CESL的一接觸開口,該接觸開口曝光該源極/汲極區的一頂表面及該CESL的一側壁;在形成該接觸開口之後,藉由用一各向同性蝕刻製程蝕刻該ILD來擴展該接觸開口;及在該接觸開口中形成一源極/汲極觸點。
根據本揭露的一些實施例中,一種電晶體,其包含以下。一基板的一通道區上的一閘極結構;該閘極結構上的一閘極遮罩;鄰接該通道區的一源極/汲極區;一源極/汲極觸點,其連接至該源極/汲極區,該源極/汲極觸點具有有多個彎曲側壁的一上部部分及有多個直側壁的一下部部分;該源極/汲極觸點周圍的一接觸間隔物,該接觸間隔物接觸該閘極遮罩的一側壁。
A-A':橫截面
B-B':橫截面
50:基板
50N:n型區
50P:p型區
52:鰭片
56:隔離區/淺溝槽隔離區
58:通道區
62:虛設介電層
64:虛設閘極層
66:遮罩層
72:虛設介電質
74:虛設閘極
76:遮罩
80A:第一間隔物層
80B:第二間隔物層
82:閘極間隔物
84:鰭片間隔物
86:源極/汲極凹槽
88:磊晶源極/汲極區
88A:襯裡層
88B:主層
88C:結束層
92:接觸蝕刻停止層
94:第一層間介電質
96:凹槽
102:閘極介電層
104:閘電極層
112:閘極介電質
114:閘電極
116:閘極遮罩
122:接觸開口
122C:角落區
124:接觸遮罩
126:槽開口
132:保護層
134:金屬-半導體合金區
136:金屬
142:源極/汲極觸點
144:接觸間隔物
152:蝕刻停止層
154:第二層間介電質
162:源極/汲極觸點
164:閘極觸點
本揭露的態樣在與隨附圖式一起研讀時自以下詳細描述內容來最佳地理解。應注意,根據行業中的標準慣例,各種特徵未按比例繪製。實際上,各種特徵的尺寸可
為了論述清楚經任意地增大或減小。
第1圖圖示根據一些實施例的三維視圖中的鰭式場效電晶體(fin field-effect transistor,FinFET)的實例。
第2圖至第21B圖係根據一些實施例的製造FinFET的中間階段的視圖。
第22A圖至第22B圖係根據一些實施例的FinFET的視圖。
以下揭示內容提供用於實施本揭露的不同特徵的許多不同實施例、或實例。下文描述組件及配置的特定實例以簡化本揭露。當然,這些僅為實例且非意欲為限制性的。舉例而言,在以下描述中第一特徵於第二特徵上方或上的形成可包括第一及第二特徵直接接觸地形成的實施例,且亦可包括額外特徵可形成於第一特徵與第二特徵之間使得第一特徵及第二特徵可不直接接觸的實施例。此外,本揭露在各種實例中可重複參考數字及/或字母。此重複系出於簡單及清楚之目的,且本身且不指明所論述之各種實施例及/或組態之間的關係。
此外,為了方便用於描述如諸圖中圖示的一個元件或特徵與另一(多個)元件或(多個)特徵的關係的描述,在本文中可使用空間相對術語,諸如「在......下面」、「在......之下」、「下部」、「在......之上」、「上部」及類似者。空間相對術語意欲涵蓋除了諸圖中所描繪的定向以外的裝置在使用或操作時的不同定向。裝置可另外定向(旋轉90
度或處於其他定向),且本文中所使用的空間相對描述符可類似地加以相應解釋。
根據各種實施例,源極/汲極區的接觸開口初始形成為較小的寬度,接著在分開的蝕刻製程中擴展至較大的寬度。可更佳地控制接觸開口的寬度,從而可避免相鄰源極/汲極區的短路。另外,保護層形成在接觸開口中且用於在源極/汲極區上形成金屬-半導體合金區期間保護環境特徵。因此,可提高製造良率。
第1圖圖示根據一些實施例的鰭式場效電晶體(FinFET)的實例。第1圖係三維視圖,其中為了說明清楚省略了FinFET的一些特徵。FinFET包括自基板50(例如,半導體基板)延伸的鰭片52,其中鰭片52用作FinFET的通道區58。隔離區56,諸如淺溝槽隔離(shallow trench isolation,STI)區,佈置在相鄰鰭片52之間,鰭片52可突出於隔離區56之上且在相鄰隔離區56之間。儘管隔離區56被描述/圖示為與基板50分開,如本文所用,術語「基板」可指單獨的半導體基板或半導體基板與隔離區的組合。另外,儘管鰭片52的底部部分被圖示為具有基板50的單一連續材料,但鰭片52的底部部分及/或基板50可包括單一材料或複數種材料。在這種情況下,鰭片52係指自相鄰隔離區56之間延伸的部分。
閘極介電質112沿著鰭片52的側壁及其頂表面上方。閘電極114在閘極介電質112上方。磊晶源極/汲
極區88相對於閘極介電質112及閘電極114佈置在鰭片52的相對側。磊晶源極/汲極區88可在各個鰭片之間共高。舉例而言,相鄰磊晶源極/汲極區88可經電連接,諸如經由用磊晶生長聚結磊晶源極/汲極區88,或經由將磊晶源極/汲極區88與相同源極/汲極觸點耦合。
第1圖進一步圖示了後面諸圖中使用的參考橫截面。橫截面A-A'沿鰭片52的縱軸且在例如FinFET的磊晶源極/汲極區88之間的電流流動的方向上。橫截面B-B'垂直於橫截面A-A'且延伸穿過FinFET的磊晶源極/汲極區88。為了清楚起見,後續諸圖參考了這些參考橫截面。
本文討論的一些實施例在使用後閘極製程形成FinFET的上下文中討論。在其它實施例中,可使用先閘極製程。此外,一些實施例考慮在諸如平面FET的平面裝置中使用的態樣。
第2圖至第21B圖係根據一些實施例的製造FinFET的中間階段的視圖。第2圖、第3圖、及第4圖係三維視圖,示出了與第1圖相似的三維視圖。第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、第19A圖、第20A圖、及第21A圖圖示沿著類似於第1圖中的參考截面A-A'的橫截面的橫截面圖。第5B圖、第6B圖、第7B圖、第8B圖、第9B圖、第10B圖、第11B圖、第12B圖、第13B圖、第14B圖、第15B圖、第16B圖、第
17B圖、第18B圖、第19B圖、第20B圖、及第21B圖圖示沿著類似於第1圖中的參考橫截面B-B'的橫截面的橫截面圖。
在第2圖中,提供了基板50。基板50可係半導體基板,諸如體半導體、絕緣體上半導體(semiconductor-on-insulator,SOI)基板、或類似者,其可經摻雜(例如,用p型或n型雜質)或無摻雜。基板50可係晶圓,諸如矽晶圓。通常,SOI基板係在絕緣體層上形成的半導體材料層。絕緣體層可係例如埋入式氧化物(buried oxide,BOX)層、氧化矽層、或類似者。絕緣體層設定在基板上,通常係矽或玻璃基板。亦可使用其它基板,諸如多層或梯度基板。在一些實施例中,基板50的半導體材料可包括矽;鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦;合金半導體,包括矽鍺、磷砷化鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵、及/或磷砷化銦鎵;其組合;或類似者。
基板50具有n型區50N及p型區50P。n型區50N可用於形成n型裝置,諸如NMOS電晶體,例如,n型FinFET,且p型區50P可用於形成p型裝置,諸如PMOS電晶體,例如,p型FinFET。n型區50N可與p型區50P實體地分開(未單獨圖示),且可在n型區50N與p型區50P之間佈置任意數目的裝置特徵(例如,其它主動裝置、摻雜區、隔離結構等)。儘管圖示了一個n型
區50N及一個p型區50P,但可提供任意數目的n型區50N及p型區50P。
在基板50中形成鰭片52。鰭片52係半導體條。可藉由在基板50中蝕刻溝槽在基板50中形成鰭片52。蝕刻可係任何可接受的蝕刻製程,諸如活性離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)、類似者、或其組合。蝕刻製程可能係各向異性的。
鰭片52可藉由任何適合的方法經圖案化。舉例而言,可使用一或多個光學微影術製程(包括雙重圖案化或多重圖案化製程)來圖案化鰭片52。通常,雙重圖案化或多重圖案化製程將光學微影術及自對準製程相結合,允許待產生的圖案具有例如比使用單一、直接光學微影術製程獲得的節距更小的節距。舉例而言,在一個實施例中,犧牲層形成在基板上方且使用光學微影術製程經圖案化。使用自對準製程沿著經圖案化犧牲層形成間隔物。接著移除犧牲層,且剩餘的間隔物可接著用作遮罩以圖案化鰭片52。在一些實施例中,遮罩(或其它層)可保留在鰭片52上。
STI區56形成在基板50上方及相鄰鰭片52之間。STI區56佈置在鰭片52的下部部分周圍,使得鰭片52的上部部分突出於相鄰STI區56之間。換言之,鰭片52的上部部分在STI區56的頂表面之上延伸。STI區56分開相鄰裝置的特徵。
STI區56可藉由任何適合的方法形成。舉例而言,
絕緣材料可形成在基板50上方及相鄰鰭片52之間。絕緣材料可係諸如氧化矽的氧化物、諸如氮化矽的氮化物、類似者、或其組合,其可藉由化學氣相沉積(chemical vapor deposition,CVD)製程形成,諸如高密度電漿CVD(high density plasma CVD,HDP-CVD)、可流動化學氣相沉積(flowable chemical vapor deposition,FCVD)、類似者、或其組合。可使用藉由任何可接受製程形成的其他絕緣材料。在一些實施例中,絕緣材料係藉由FCVD形成的氧化矽。一旦形成絕緣材料,就可執行退火製程。儘管STI區56各者被圖示為單層,但一些實施例可利用多層。舉例而言,在一些實施例中,可首先沿著基板50及鰭片52的表面形成襯裡(未單獨圖示)。此後,可在襯裡上方形成填充材料諸如先前描述的絕緣材料的一層。在一個實施例中,形成絕緣材料使得多餘的絕緣材料覆蓋鰭片52。接著對絕緣材料應用移除製程以移除鰭片52上方的多餘的絕緣材料。在一些實施例中,可利用平坦化製程,諸如化學機械研磨(chemical mechanical polish,CMP)、回蝕製程、其組合、或類似者。在遮罩保留在鰭片52上的實施例中,平坦化製程可曝光遮罩或移除遮罩。在平坦化製程之後,絕緣材料及遮罩(若存在)或鰭片52的頂表面係共面的(在製程變化範圍內)。因此,遮罩(若存在)或鰭片52的頂表面經由絕緣材料曝光。在所圖示的實施例中,鰭片52上不保留遮罩。接著絕緣材料經凹陷以形成STI區56。凹陷絕緣材料使
得鰭片52的上部部分突出於絕緣材料的相鄰部分之間。此外,STI區56的頂表面可具有如所圖示的平面、凸面、凹面(諸如凹陷)、或其組合。STI區56的頂表面可藉由適當的蝕刻形成平的、凸的、及/或凹的。可使用諸如對絕緣材料的材料具有選擇性(例如,以比蝕刻鰭片52的材料更快的速率選擇性地蝕刻STI區56的絕緣材料)的任何可接受的蝕刻製程來凹陷絕緣材料。舉例而言,可使用稀氫氟(dilute hydrofluoric,dHF)酸來執行氧化物移除。
前面描述的製程係如何形成鰭片52及STI區56的僅一個實例。在一些實施例中,可使用遮罩及磊晶生長製程來形成鰭片52。舉例而言,介電層可形成在基板50的頂表面上方,且溝槽可經蝕刻穿過介電層以曝光下伏基板50。磊晶結構可在溝槽中磊晶生長,且介電層可經凹陷使得磊晶結構突出於介電層以形成鰭片52。在磊晶結構經磊晶生長的一些實施例中,磊晶生長的材料可在生長期間經原位摻雜,這可避免先前及/或後續植入,雖然原位摻雜及植入摻雜可一起使用。
此外,在n型區50N中磊晶生長不同於p型區50P中的材料的材料可係有利的。在各種實施例中,鰭片52的上部部分可由矽鍺(SixGe1-x,其中x可在0至1的範圍內)、碳化矽、純或基本純鍺、III-V化合物半導體、II-VI化合物半導體、或類似者形成。舉例而言,用於形成III-V化合物半導體的可用材料包括但不限於砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化鎵銦、砷化
鋁銦、銻化鎵、銻化鋁、磷化鋁、磷化鎵、及類似者。
此外,可在鰭片52及/或基板50中形成適當的井(未單獨圖示)。這些井可具有與後續待在n型區50N及p型區50P中的各者中形成的源極/汲極區的導電類型相反的導電類型。在一些實施例中,在n型區50N中形成p型井,且在p型區50P中形成n型井。在一些實施例中,在n型區50N及p型區50P兩者中形成p型井或n型井。
在具有不同井類型的實施例中,可使用諸如光阻劑的遮罩(未單獨圖示)來達成用於n型區50N及p型區50P的不同植入步驟。舉例而言,可在n型區50N中的鰭片52及STI區56上方形成光阻劑。光阻劑經圖案化以曝光p型區50P。光阻劑可藉由使用旋裝技術形成,且可使用可接受的光學微影術技術來圖案化。一旦光阻劑經圖案化,則在p型區50P中執行n型雜質植入,且光阻劑可充當遮罩以基本防止n型雜質被植入n型區50N中。n型雜質可係植入區中的磷、砷、銻、或類似者,達到1013cm-3至1014cm-3範圍內的濃度。在植入之後,諸如藉由任何可接受的灰化製程來移除光阻劑。
在p型區50P的植入之後或之前,在p型區50P中的鰭片52及STI區56上方形成諸如光阻劑的遮罩(未單獨圖示)。光阻劑經圖案化以曝光n型區50N。光阻劑可藉由使用旋裝技術形成,且可使用可接受的光學微影術技術來圖案化。一旦光阻劑經圖案化,可在n型區50N中執行p型雜質植入,且光阻劑可充當遮罩以基本防止p型
雜質被植入p型區50P中。p型雜質可係植入區中的硼、氟化硼、銦、或類似者,達到1013cm-3至1014cm-3範圍內的濃度。在植入之後,諸如藉由任何可接受的灰化製程來移除光阻劑。
在n型區50N及p型區50P的植入之後,可執行退火以修復植入損傷且活化植入的p型及/或n型雜質。在磊晶結構為鰭片52磊晶生長的一些實施例中,在生長期間生長的材料可經原位摻雜,這可避免植入,儘管原位摻雜及植入摻雜可一起使用。
在第3圖中,虛設介電層62形成在鰭片52上。虛設介電層62可由介電材料(諸如氧化矽、氮化矽、其組合、或類似者)形成,其可根據可接受的技術經沉積或熱生長。虛設閘極層64形成在虛設介電層62上方,且遮罩層66形成在虛設閘極層64上方。虛設閘極層64可沉積在虛設介電層62上方且接著諸如藉由CMP經平坦化。遮罩層66可沉積在虛設閘極層64上方。虛設閘極層64可由導電或非導電材料(諸如非晶矽、多晶矽(聚合矽)、多晶矽鍺(poly-crystalline silicon-germanium,poly-SiGe)、金屬、金屬氮化物、金屬矽化物、金屬氧化物、或類似者)形成,其可藉由物理氣相沉積(physical vapor deposition,PVD)、CVD、或類似者沉積。虛設閘極層64可由對絕緣材料(例如,STI區56及/或虛設介電層62)的蝕刻具有高蝕刻選擇性的材料(多種)形成。遮罩層66可由諸如氮化矽、氧氮化矽、或類似者的介
電材料形成。在這個實例中,跨n型區50N及p型區50P形成單個虛設閘極層64及單個遮罩層66。在所圖示實施例中,虛設介電層62覆蓋鰭片52及STI區56,使得虛設介電層62在STI區56上方及虛設閘極層64與STI區56之間延伸。在另一實施例中,虛設介電層62僅覆蓋鰭片52。
在第4圖中,使用可接受的光學微影術及蝕刻技術圖案化遮罩層66以形成遮罩76。接著藉由任何可接受的蝕刻技術將遮罩76的圖案轉移至虛設閘極層64以形成虛設閘極74。遮罩76的圖案可藉由任何可接受的蝕刻技術可選地進一步轉移至虛設介電層62,以形成虛設介電質72。虛設閘極74覆蓋鰭片52的各自的通道區58。遮罩76的圖案可用於實體地分開相鄰虛設閘極74。虛設閘極74亦可具有基本垂直(在製程變化範圍內)於鰭片52的縱向方向的縱向方向。遮罩76可在虛設閘極74的圖案化期間經移除,或可在後續處理期間經移除。
第5A圖至第21B圖圖示製造實施例裝置的各種額外步驟。第5A圖至第21B圖圖示n型區50N及p型區50P中任一者的特徵。舉例而言,所圖示的結構可適用於n型區50N及p型區50P兩者。n型區50N及p型區50P的結構中的差別(若有)在各個圖所附的文本中描述。
在第5A圖至第5B圖中,閘極間隔物82形成在鰭片52上方、遮罩76(若存在)、虛設閘極74、及虛設介電質72的經曝光側壁上。閘極間隔物82可藉由共形沉
積一或多個介電材料(多種)及後續蝕刻介電材料(多種)而形成。可接受的介電材料可包括氧化矽、氮化矽、氧氮化矽、氧碳氮化矽、或類似者,其可藉由共形沉積製程形成,諸如化學氣相沉積(CVD)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、原子層沉積(atomic layer deposition,ALD)、電漿增強原子層沉積(plasma-enhanced atomic layer deposition,PEALD)、或類似者。可使用藉由任何可接受製程形成的其他絕緣材料。在所圖示的實施例中,閘極間隔物82各者包括多個層,例如,第一間隔物層80A及第二間隔物層80B。在一些實施例中,第一間隔物層80A及第二間隔物層80B由氧碳氮化矽(例如,SiOxNyC1-x-y,其中x及y在0至1的範圍內)形成,第一間隔物層80A由與第二間隔物層80B相似或不同的氧碳氮化矽組成。可執行任何可接受的蝕刻製程(諸如乾式蝕刻、濕式蝕刻、類似者、或其組合)以圖案化介電材料(多種)。蝕刻可係各向異性的。當經蝕刻時,介電材料(多種)在虛設閘極74的側壁上留下部分(從而形成閘極間隔物82)。在一些實施例中,調整用於形成閘極間隔物82的蝕刻,使得當經蝕刻時,介電材料(多種)亦具有留在鰭片52的側壁上的部分(從而形成鰭片間隔物84)。在蝕刻之後,鰭片間隔物84(若存在)及閘極間隔物82可具有直側壁(如所圖示)或可具有彎曲側壁(未單獨圖示)。
此外,可執行植入以形成輕摻雜源極/汲極(lightly doped source/drain,LDD)區(未單獨圖示)。在具有不同裝置類型的實施例中,類似於用於先前描述的井的植入,可在n型區50N上方形成諸如光阻劑的遮罩(未單獨圖示),同時曝光p型區50P,且適當類型(例如,p型)的雜質可植入曝光於p型區50P中的鰭片52中。接著可移除遮罩。隨後,可在曝光n型區50N的同時在p型區50P上方形成諸如光阻劑的遮罩(未單獨圖示),且可將適當類型的雜質(例如,n型)植入曝光於n型區50N中的鰭片52中。接著可移除遮罩。n型雜質可係先前描述的任何n型雜質,且p型雜質可係先前描述的任何p型雜質。在植入期間,通道區58保持由虛設閘極74覆蓋,使得通道區58保持基本無雜質植入以形成LDD區。LDD區可具有在1015cm-3至1019cm-3範圍內的雜質濃度。退火可用於修復植入損傷及活化植入的雜質。
注意,先前的揭示內容通常描述形成間隔物及LDD區的製程。可使用其他製程及順序。舉例而言,可利用較少或額外的間隔物、可利用不同順序的步驟、可形成及移除額外的間隔物、及/或類似者。此外,可使用不同的結構及步驟來形成n型裝置及p型裝置。
在第6A圖至第6B圖中,源極/汲極凹槽86形成在鰭片52中。在所圖示實施例中,源極/汲極凹槽86延伸至鰭片52中。源極/汲極凹槽86亦可延伸至基板50中。在各種實施例中,源極/汲極凹槽86可延伸至基板50的
頂表面而不蝕刻基板50;鰭片52可經蝕刻使得源極/汲極凹槽86的底表面佈置在STI區56的頂表面之下;或類似者。源極/汲極凹槽86可藉由使用各向異性蝕刻製程(諸如RIE、NBE、或類似者)蝕刻鰭片52來形成。在用於形成源極/汲極凹槽86的蝕刻製程期間,閘極間隔物82及虛設閘極74共同遮蔽鰭片52的部分。在源極/汲極凹槽86達至所需深度之後,可使用定時蝕刻製程以停止源極/汲極凹槽86的蝕刻。在源極/汲極凹槽86的蝕刻期間或之後,可蝕刻鰭片間隔物84(若存在),使得鰭片間隔物84的高度減小,且鰭片間隔物84覆蓋鰭片52的側壁的一部分。後續待在源極/汲極凹槽86中形成的源極/汲極區的大小及尺寸可藉由調整鰭片間隔物84的高度來控制。
在第7A圖至第7B圖中,磊晶源極/汲極區88形成在源極/汲極凹槽86中。因此磊晶源極/汲極區88被佈置在鰭片52中,使得各個虛設閘極74(及相應通道區58)在磊晶源極/汲極區88的各自的相鄰對之間。磊晶源極/汲極區88因此鄰接通道區58。在一些實施例中,閘極間隔物82用於藉由適當的側向距離將磊晶源極/汲極區88自虛設閘極74分開,使得磊晶源極/汲極區88不與所得FinFET的後續形成的閘極短路。磊晶源極/汲極區88的材料可經選擇,以在各自的通道區58中施加應力,從而提高效能。
n型區50N中的磊晶源極/汲極區88可藉由遮蔽p型區50P而形成。接著,n型區50N中的磊晶源極/汲
極區88在n型區50N中的源極/汲極凹槽86中磊晶生長。磊晶源極/汲極區88可包括適合於n型裝置的任何可接受的材料。舉例而言,若鰭片52係矽,則n型區50N中的磊晶源極/汲極區88可包括在通道區58上施加拉伸應變的材料,諸如矽、碳化矽、磷摻雜碳化矽、磷化矽、或類似者。n型區50N中的磊晶源極/汲極區88可稱為「n型源極/汲極區」。n型區50N中的磊晶源極/汲極區88可具有自鰭片52的各自的表面升起的表面,且可具有小平面。
p型區50P中的磊晶源極/汲極區88可藉由遮蔽n型區50N形成。接著,p型區50P中的磊晶源極/汲極區88在p型區50P中的源極/汲極凹槽86中磊晶生長。磊晶源極/汲極區88可包括適合於p型裝置的任何可接受的材料。舉例而言,若鰭片52係矽,p型區50P中的磊晶源極/汲極區88可包括在通道區58上施加壓縮應變的材料,諸如矽鍺、硼摻雜矽鍺、鍺、鍺錫、或類似者。p型區50P中的磊晶源極/汲極區88可稱為「p型源極/汲極區」。p型區50P中的磊晶源極/汲極區88可具有自鰭片52的各自的表面升起的表面,且可具有小平面。
磊晶源極/汲極區88及/或鰭片52可植入雜質,以形成源極/汲極區,類似於先前描述的形成LDD區的製程,然後進行退火。源極/汲極區可具有在1019cm-3至1021cm-3範圍內的雜質濃度。用於源極/汲極區的n型及/或p型雜質可係先前描述的任何雜質。在一些實施例中,
磊晶源極/汲極區88可在生長期間經原位摻雜。
作為用於形成磊晶源極/汲極區88的磊晶製程的結果,磊晶源極/汲極區的上表面具有小平面,小平面超出鰭片52的側壁而側向向外擴展。在一些實施例中,這些小平面使得相鄰磊晶源極/汲極區88合併,如第7B圖所圖示。在一些實施例中,相鄰磊晶源極/汲極區88在磊晶製程完成之後保持分開(未單獨圖示)。在所圖式實施例中,形成鰭片間隔物84以覆蓋在STI區56之上延伸的鰭片52的側壁的一部分,從而阻擋了磊晶生長。在另一實施例中,用於形成閘極間隔物82的間隔物蝕刻經調整以不形成鰭片間隔物84,從而允許磊晶源極/汲極區88延伸至STI區56的表面。
磊晶源極/汲極區88可包括一或多個半導體材料層。舉例而言,磊晶源極/汲極區88可各包括襯裡層88A、主層88B、及結束層88C(或更一般地,第一半導體材料層、第二半導體材料層、及第三半導體材料層)。任何數目的半導體材料層可用於磊晶源極/汲極區88。襯裡層88A、主層88B、及結束層88C可由不同的半導體材料形成,且可摻雜至不同的雜質濃度。在一些實施例中,主層88B具有比結束層88C更高的雜質濃度,且結束層88C具有比襯裡層88A更高的雜質濃度。在磊晶源極/汲極區88包括三個半導體材料層的實施例中,襯裡層88A可在源極/汲極凹槽86中生長,主層88B可在襯裡層88A上生長,且結束層88C可在主層88B上生長。形成具有比
主層88B更低的雜質濃度的襯裡層88A可增大源極/汲極凹槽86中的附著力,且形成具有比主層88B更低的雜質濃度的結束層88C可減少後續處理期間摻雜劑自主層88B向外擴散。
在第8A圖至第8B圖中,第一層間介電質(inter-layer dielectric,ILD)94沉積在磊晶源極/汲極區88、閘極間隔物82、及遮罩76(若存在)或虛設閘極74上方。第一ILD 94可由介電材料形成,其可藉由任何適合的方法沉積,諸如CVD、電漿增強CVD(PECVD)、FCVD、或類似者。可接受的介電材料可包括磷矽玻璃(phospho-silicate glass,PSG)、硼矽玻璃(boro-silicate glass,BSG)、硼磷矽玻璃(boron-doped phospho-silicate glass,BPSG)、無摻雜矽玻璃(undoped silicate glass,USG)、或類似者。可使用藉由任何可接受的製程形成的其他絕緣材料。
在一些實施例中,在第一ILD 94與磊晶源極/汲極區88、閘極間隔物82、及遮罩76(若存在)或虛設閘極74之間形成接觸蝕刻停止層(contact etch stop layer,CESL)92。CESL 92可由介電材料形成,諸如氮化矽、氧化矽、氧氮化矽、或類似者,具有對第一ILD 94的蝕刻的高蝕刻選擇性。CESL 92可藉由任何適合的方法形成,諸如CVD、ALD、或類似者。
在第9A圖至第9B圖中,執行移除製程以使第一
ILD 94的頂表面與遮罩76(若存在)或虛設閘極74的頂表面齊平。在一些實施例中,可利用諸如化學機械研磨(CMP)、回蝕製程、其組合、或類似者的平坦化製程。平坦化製程亦可移除虛設閘極74上的遮罩76,及沿著遮罩76的側壁的閘極間隔物82的部分。在平坦化製程之後,第一ILD 94、CESL 92、閘極間隔物82、及遮罩76(若存在)或虛設閘極74的頂表面共面(在製程變化範圍內)。因此,遮罩76(若存在)或虛設閘極74的頂表面經由第一ILD 94曝光。在所圖示實施例中,遮罩76保留,且平坦化製程將第一ILD 94的頂表面與遮罩76的頂表面齊平。
在第10A圖至第10B圖中,在蝕刻製程中移除遮罩76(若存在)及虛設閘極74,從而形成凹槽96。凹槽96中的虛設介電質72的部分亦可經移除。在一些實施例中,僅移除虛設閘極74,且虛設介電質72保留並藉由凹槽96曝光。在一些實施例中,虛設介電質72自晶片的第一區(例如,核心邏輯區)中的凹槽96移除且保留在晶片的第二區(例如,輸入/輸出區)中的凹槽96中。在一些實施例中,藉由各向異性乾式蝕刻製程移除虛設閘極74。舉例而言,蝕刻製程可包括使用活性氣體(多種)的乾式蝕刻製程,以比蝕刻第一ILD 94或閘極間隔物82更快的速率選擇性地蝕刻虛設閘極74。在移除期間,當蝕刻虛設閘極74時,虛設介電質72可用作蝕刻停止層。在移除虛設閘極74之後,可接著可選地移除虛設介電質72。各
個凹槽96曝光及/或上覆各自的鰭片52的通道區58。
在第11A圖至第11B圖中,閘極介電層102形成在凹槽96中。閘電極層104形成在閘極介電層102上。閘極介電層102及閘電極層104係用於替換閘極的層,且各沿著通道區58的側壁及其頂表面上方延伸。
閘極介電層102佈置在鰭片52的側壁及/或頂表面上以及閘極間隔物82的側壁上。閘極介電層102亦可形成在第一ILD 94及閘極間隔物82的頂表面上。閘極介電層102可包括氧化物(諸如氧化矽或金屬氧化物)、矽酸鹽(諸如金屬矽酸鹽)、其組合、其多層、或類似者。閘極介電層102可包括高k介電材料(例如,具有大於約7.0的k值的介電材料),諸如鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛的金屬氧化物或矽酸鹽、及其組合。閘極介電層102的形成方法可包括分子束沉積(molecular-beam deposition,MBD)、ALD、PECVD、及類似者。在虛設介電質72的部分保留在凹槽96中的實施例中,閘極介電層102包括虛設介電質72的材料(例如,氧化矽)。儘管圖示了單層閘極介電層102,但閘極介電層102可包括任何數目的介面層及任何數目的主層。舉例而言,閘極介電層102可包括介面層及上覆高k介電層。
閘電極層104可包括含金屬材料,諸如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鎢、鈷、釕、鋁、其組合、其多層、或類似者。儘管圖示了單層閘電極層104,但閘電極層104可包括任何數目的功函數調諧層、任何數目的阻
障層、任何數目的黏合層、及填充材料。
n型區50N及p型區50P中的閘極介電層102的形成可同時發生,使得各個區中的閘極介電層102由相同的材料(多種)形成,且閘電極層104的形成可同時發生,使得各個區中的閘電極層104由相同的材料(多種)形成。在一些實施例中,各個區中的閘極介電層102可藉由不同的製程形成,使得閘極介電層102可係不同的材料及/或具有不同數目的層;及/或各個區中的閘電極層104可藉由不同的製程形成,使得閘電極層104可係不同的材料及/或具有不同數目的層。當使用不同的製程時,可使用各種遮蔽步驟來遮蔽及曝光適當的區。
在第12A圖至第12B圖中,執行移除製程,以移除閘極介電層102及閘電極層104的材料的多餘部分,這些材料的多餘部分在第一ILD 94、CESL 92、及閘極間隔物82的頂表面上方,從而形成閘極介電質112及閘電極114。在一些實施例中,可利用平坦化製程,諸如化學機械研磨(CMP)、回蝕製程、其組合、或類似者。當進行平坦化時,閘極介電層102具有留在凹槽96中的部分(從而形成閘極介電質112)。當進行平坦化時,閘電極層104具有留在凹槽96中的部分(從而形成閘電極114)。閘極間隔物82、CESL 92、第一ILD 94、閘極介電質112、及閘電極114的頂表面係共面的(在製程變化範圍內)。閘極介電質112及閘電極114形成所得FinFET的替換閘極。閘極介電質112及閘電極114的各個相應對可統稱
為「閘極結構」。閘極結構各沿著鰭片52的通道區58的頂表面、側壁、及底表面延伸。
第13A圖至第13B圖中,閘極遮罩116形成在閘極結構(包括閘極介電質112及閘電極114)及閘極間隔物82(可選地)上方。閘極遮罩116由一或多個介電材料(多種)形成,介電材料對第一ILD 94的蝕刻具有高蝕刻選擇性。可接受的介電材料可包括氮化矽、碳氮化矽、氧氮化矽、氧碳氮化矽、或類似者,這些可藉由共形沉積製程(諸如化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、電漿增強原子層沉積(PELD)、或類似者)形成。可使用藉由任何可接受製程形成的其他絕緣材料。
作為形成閘極遮罩116的實例,閘極結構(包括閘極介電質112及閘電極114)及閘極間隔物82(可選地)可使用任何可接受的蝕刻製程來凹陷。在所圖示實施例中,閘極間隔物82及閘極結構凹陷相同的深度。在另一實施例中,閘極結構比閘極間隔物82凹陷更大的深度。在又另一實施例中,閘極結構經凹陷,但閘極間隔物82未經凹陷。接著,介電材料(多種)共形地沉積在凹槽中,且亦可形成在第一ILD 94的頂表面上。執行移除製程以移除介電材料(多種)的多餘部分,這些多餘部分在第一ILD 94的頂表面上方,由此形成閘極遮罩116。在一些實施例中,可利用諸如化學機械研磨(CMP)、回蝕製程、其組合、或類似者的平坦化製程。當經平坦化時,介電材料(多種)
具有留在凹槽中的部分(從而形成閘極遮罩116)。隨後將形成閘極觸點以穿透閘極遮罩116而接觸閘電極114的頂表面。
第14A圖至第14B圖中,接觸開口122穿過第一ILD 94及CESL 92形成。接觸開口122係藉由自對準接觸(self-aligned contact,SAC)製程形成的源極/汲極接觸開口,使得基本沒有第一ILD 94的殘留物保留在接觸開口122的角落區122C中。接觸開口122的角落區122C係在第14A圖的橫截面中藉由CESL 92的側壁及磊晶源極/汲極區88的頂表面界定的角落。
作為形成接觸開口122的實例,可在第一ILD 94及閘極遮罩116上方形成接觸遮罩124。接觸遮罩124經圖案化為具有接觸開口122的圖案的槽開口126。接觸遮罩124可係例如光阻劑,諸如單層光阻劑、雙層光阻劑、三層光阻劑、或類似者,其可使用可接受的光學微影術技術經圖案化以形成槽開口126。可使用藉由任何可接受的製程形成的其它類型的遮罩。槽開口126係平行於鰭片52的縱向運行的條帶,與第一ILD 94及閘極遮罩116重疊。接著可使用接觸遮罩124作為蝕刻遮罩且使用CESL 92作為蝕刻停止層來蝕刻第一ILD 94。蝕刻可係任何可接受的蝕刻製程,諸如對第一ILD 94的材料具有選擇性(例如,以比蝕刻CESL 92及閘極遮罩116的材料更快的速率選擇性地蝕刻第一ILD 94的材料)的蝕刻製程。蝕刻製程可係各向異性的。因此,蝕刻未被接觸遮罩124覆蓋
的第一ILD 94的部分(例如,藉由槽開口126曝光)以形成接觸開口122。接著接觸開口122藉由任何可接受的蝕刻製程延伸穿過CESL 92以曝光磊晶源極/汲極區88。在蝕刻製程之後,諸如藉由任何可接受的灰化製程來移除接觸遮罩124。
根據用於形成接觸開口122的蝕刻製程的選擇性,可發生CESL 92及/或閘極遮罩116的一些損失。參考第14A圖的橫截面,接觸開口122可具有漏斗形狀,其中接觸開口122的上部部分具有彎曲的側壁(例如,錐形側壁),且接觸開口122的下部部分具有基本直的側壁(例如,非錐形側壁)。可減小CESL 92及/或閘極遮罩116的尺寸。具體地,閘極遮罩116及CESL 92的上部部分可具有減小的寬度,使得閘極遮罩116及CESL 92的上部部分具有彎曲的側壁,且閘極遮罩116及CESL 92的下部部分具有基本直的側壁。此外,閘極遮罩116及CESL 92可具有減小的高度,且事實上,CESL 92的頂表面可凹陷在閘極遮罩116的頂表面之下,從而曝光閘極遮罩116的彎曲側壁。
在第15A圖至第15B圖中,接觸開口122經擴展以擴大源極/汲極觸點的著陸窗口,窗口隨後將形成在接觸開口122中。舉例而言,在擴展之前,接觸開口122可具有在10nm至100nm範圍內的初始寬度,且在擴展之後,接觸開口122可具有在11nm至105nm範圍內的最終寬度,其中最終寬度比初始寬度大1%至5%。可使
用任何可接受的蝕刻製程來擴展接觸開口122,諸如對第一ILD 94的材料具有選擇性(例如,以比蝕刻閘極遮罩116的材料更快的速率選擇性地蝕刻第一ILD 94的材料)的蝕刻製程。蝕刻製程可係各向同性的,使得第一ILD 94的高度減小,且藉由蝕刻使第一ILD 94的角落變圓。舉例而言,在蝕刻之前,第一ILD 94可具有在40nm至80nm範圍內的初始高度,且在蝕刻之後,第一ILD 94可具有在20nm至60nm範圍內的最終高度,其中最終高度比初始高度小25%至50%。接觸開口122亦可擴展穿過CESL 92。
在一些實施例中,蝕刻處理係無需電漿而執行的乾式蝕刻。舉例而言,當第一ILD 94由氧化矽形成時,可用包括氟化氫(hydrogen fluoride,HF)及氨(ammonia,NH3)(可選地)的蝕刻氣體溶液來執行乾式蝕刻。蝕刻氣體溶液可在第一ILD 94上方及在接觸開口122中流動,而不產生電漿。在蝕刻氣體溶液中包括氨(NH3)係任選的,且包括其降低了蝕刻氣體溶液與第一ILD 94的材料之間的反應的活化能,從而允許在低溫下執行蝕刻。在一些實施例中,在不低於室溫的低溫下執行乾式蝕刻。舉例而言,當蝕刻氣體溶液不包括氨(NH3)時,可在20℃至40℃範圍內的溫度下執行乾式蝕刻,且當蝕刻氣體溶液包括氨(NH3)時,可在室溫下執行乾式蝕刻,諸如在20℃至40℃範圍內的溫度。蝕刻氣體溶液與第一ILD 94的材料之間的反應係放熱的,且因此在低溫下執
行它可提高反應效率。在蝕刻氣體溶液包括氟化氫(HF)及氨(NH3)的實施例中,蝕刻氣體溶液與第一ILD 94的材料之間的反應包括兩種擴散(例如,氣相擴散及表面擴散)及兩種吸附(例如,物理吸附及化學吸附),且因此反應可具有潛伏期,這增大了乾式蝕刻的持續時間。舉例而言,乾式蝕刻可執行3秒至20秒範圍內的持續時間。乾式蝕刻將第一ILD 94的材料轉化為一或多個副產品(多種)。副產品可包括氣相副產品(例如,四氟化矽)(多種)及/或固相副產品(例如,氟矽酸銨)(多種)。在乾式蝕刻之後,可在足夠高的溫度及持續時間下進行熱處理,以昇華固相副產品(多種)且產生額外的氣相副產品(多種)。舉例而言,可在100℃至180℃範圍內的溫度下執行60秒至240秒之間的持續時間的熱處理。熱處理可在比乾式蝕刻更高的溫度下執行,特別地在蝕刻氣體溶液包括氨(NH3)的實施例中。一旦固相副產品昇華為氣相副產品,它們就可藉由真空自接觸開口122中排出。在一些實施例中,蝕刻處理包括乾式蝕刻及熱處理的多個循環。可執行循環直至接觸開口122擴展為期望的量。舉例而言,可執行1至10個乾式蝕刻及熱處理的循環。
如上所述,接觸開口122的最終寬度大於接觸開口122的初始寬度。用於擴展接觸開口122(如第15A圖至第15B圖所述)的各向同性蝕刻製程可比用於初始形成接觸開口122(如第14A圖至第14B圖所述)的各向異性蝕刻製程更為最終控制的。與初始形成接觸開口122
為較大寬度相比,初始形成接觸開口122為較小寬度且接著用高度可控蝕刻製程將它們擴展至更大的寬度,可避免相鄰磊晶源極/汲極區88的短路。此外,用於擴展接觸開口122的各向同性蝕刻製程對第一ILD 94具有選擇性,使得閘極遮罩116基本不被蝕刻製程所蝕刻。因此,第14B圖的橫截面中的接觸開口122的寬度增大,但第14A圖的橫截面中的接觸開口122的寬度保持基本不變。因此,可避免隨後形成的觸點短接至例如閘電極114。
在第16A圖至第16B圖中,保護層132共形地沉積在接觸開口122中及閘極遮罩116上。保護層132佈置在磊晶源極/汲極區88、CESL 92、第一ILD 94、及閘極遮罩116的側壁及/或頂表面上。值得注意,保護層132與藉由用於初始形成接觸開口122的蝕刻製程曝光的閘極遮罩116及CESL 92的彎曲側壁接觸地形成(如第14A圖至第14B圖所述)。保護層132由一或多個介電材料(多種)形成,介電材料具有對磊晶源極/汲極區88的蝕刻的高蝕刻選擇性。可接受的介電材料可包括氮化矽、碳氮化矽、氧氮化矽、氧碳氮化矽、或類似者,其可由共形沉積製程形成,諸如化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、電漿增強原子層沉積(PELD)、或類似者。可使用藉由任何可接受的製程形成的其他絕緣材料。在一些實施例中,保護層132由氮化矽藉由ALD來形成。保護層132可形成為1nm至3nm範圍內的厚度。這種厚度在後續處理中為下伏特
征提供了充分的保護。
值得注意,在擴展接觸開口122之後,保護層132沉積在接觸開口122中。如上所述,擴展接觸開口122允許隨後形成的源極/汲極觸點的著陸窗口經放大。在形成保護層132之前擴展接觸開口122確保擴展製程不會被保護層132阻擋。此外,且如隨後所述,形成保護層132有助於避免在後續處理期間接觸開口122的進一步擴展。
在第17A圖至第17B圖中,接觸開口122延伸穿過保護層132以曝光磊晶源極/汲極區88。可使用任何可接受的蝕刻製程,諸如對保護層132的材料具有選擇性(例如,以比蝕刻磊晶源極/汲極區88的材料(多種)更快的速率選擇性地蝕刻保護層132的材料)的蝕刻製程。蝕刻製程可係各向異性的。
在一些實施例中,藉由使用羰基硫化物(carbonyl sulfide,COS)的乾式蝕刻,接觸開口122延伸穿過保護層132。COS在保護層132(例如,氮化矽)的絕緣材料與高雜質濃度的半導體材料之間提供了高蝕刻選擇性。如上所述,磊晶源極/汲極區88可包括主層88B及結束層88C,其中主層88B具有比結束層88C更大的雜質濃度。用COS執行乾式蝕刻允許接觸開口122延伸穿過保護層132及結束層88C,使得接觸開口122曝光主層88B,而基本不刻蝕主層88B。隨後將形成在接觸開口122中的源極/汲極觸點可因此接觸磊晶源極/汲極區88的主層88B(例如,高摻雜區)。形成源極/汲極觸點
至磊晶源極/汲極區88的高摻雜區降低了裝置的接觸電阻。此外,避免蝕刻主層88B增大了磊晶源極/汲極區88中可用的多數載子的數目。因此,可改善裝置效能。
在一些實施例中,藉由類似於描述為用以初始形成接觸開口122的自對準製程的自對準製程,接觸開口122延伸穿過保護層132。舉例而言,具有槽開口圖案的遮罩可形成在保護層132上方,且用作蝕刻遮罩以將接觸開口122延伸穿過保護層132。因此,磊晶源極/汲極區88經由保護層132曝光,但閘極遮罩116、第一ILD 94、及CESL 92的多數保持由保護層132覆蓋。
在第18A圖至第18B圖中,金屬-半導體合金區134形成在接觸開口122中及由接觸開口122曝光的磊晶源極/汲極區88的部分上。舉例而言,當磊晶源極/汲極區88的主層88B經曝光時,金屬-半導體合金區134形成,使得它們在主層88B上且延伸穿過結束層88C(參見第17A圖至第17B圖)。金屬-半導體合金區134可係由金屬矽化物(例如,矽化鈦、矽化鈷、矽化鎳等)形成的矽化物區、由金屬鍺化物(例如,鍺化鈦、鍺化鈷、鎳化鍺等)形成的鍺化物區、由金屬矽化物及金屬鍺化物形成的矽鍺化物區、或類似者。金屬-半導體合金區134可藉由在保護層132上及接觸開口122中(例如,在磊晶源極/汲極區88上)沉積金屬136,且接著執行熱退火製程來形成。金屬136可係能夠與磊晶源極/汲極區88的半導體材料(例如,矽、矽鍺、鍺等)反應以形成低電阻金屬-半
導體合金的任何金屬,諸如鎳、鈷、鈦、鉭、鉑、鎢、其他貴金屬、其他難熔金屬、稀土金屬或其合金。金屬136可藉由諸如ALD、CVD、PVD、或類似者的沉積製程沉積。在熱退火製程之後,執行清洗製程,以移除金屬136的任何殘留物,諸如自金屬-半導體合金區134及保護層132的表面。清洗製程可係用稀氫氟(dHF)酸執行的濕式蝕刻。
如上所述,保護層132經圖案化使得閘極遮罩116、第一ILD 94、及CESL 92的多數保持由保護層132覆蓋。因此,在用於移除金屬136的殘留物的清洗製程期間,可避免閘極遮罩116、第一ILD 94、及CESL 92的蝕刻,使得不會發生閘極遮罩116、第一ILD 94、或CESL 92的蝕刻。在自接觸開口122移除金屬136的殘留物期間,用保護層132保護閘極遮罩116、第一ILD 94、及CESL 92可避免接觸開口122的不期望的擴展。因此,可避免隨後形成的觸點與例如閘電極114的短路。
在第19A圖至第19B圖中,在接觸開口122中形成源極/汲極觸點142。源極/汲極觸點142連接至磊晶源極/汲極區88,且實體地接觸金屬-半導體合金區134。作為形成源極/汲極觸點142的實例,諸如擴散阻障層、附著層、或類似者的襯裡(未單獨圖示)及導電材料可形成在接觸開口122中(例如,在金屬-半導體合金區134上)。襯裡可包括鈦、氮化鈦、鉭、氮化鉭、或類似者。導電材料可係銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或類似者。
執行移除製程以自閘極遮罩116的頂表面移除多餘材料。在一些實施例中,可利用諸如化學機械研磨(CMP)、回蝕製程、其組合、或類似者的平坦化製程。剩餘襯裡及導電材料在接觸開口122中形成源極/汲極觸點142。
由於保護層132在接觸開口122的清洗期間保護閘極遮罩116及CESL 92(如第18A圖至第18B圖所述),因此可避免CESL 92及/或閘極遮罩116的損失。參考第19A圖的橫截面,源極/汲極觸點142因此可具有與接觸開口122類似的漏斗形狀(如第14A圖所述),其中源極/汲極觸點142的上部部分具有彎曲的側壁(例如,錐形側壁),且源極/汲極觸點142的下部部分具有基本直的側壁(例如,非錐形側壁)。
為了移除源極/汲極觸點142的多餘材料而執行的移除製程亦自閘極遮罩116的頂表面移除保護層132的部分。剩餘的保護層132在接觸開口122中、在源極/汲極觸點142的周圍形成接觸間隔物144。沿著源極/汲極觸點142的上部部分的接觸間隔物144的部分係彎曲的,且沿著源極/汲極觸點142的下部部分的接觸間隔物144的部分係直的。取決於移除製程的選擇性,閘極遮罩116可發生一些損失,使得閘極遮罩116具有減小的高度。在所圖示的實施例中,接觸間隔物144沿著閘極遮罩116的剩餘部分的彎曲側壁、及CESL 92的彎曲側壁延伸且與這些側壁實體地接觸。在另一實施例中(更多細節在下文描述),降低閘極遮罩116的高度,直至閘極遮罩116及
CESL 92的頂表面共面(在製程變化範圍內),使得接觸間隔物144藉由CESL 92與閘極遮罩116的側壁實體地分開。
在第20A圖至第20B圖中,第二ILD 154沉積在第一ILD 94、閘極遮罩116、源極/汲極觸點142、及接觸間隔物144上方。在一些實施例中,第二ILD 154係藉由可流動CVD方法形成的可流動膜。在一些實施例中,第二ILD 154由諸如PSG、BSG、BPSG、USG、或類似者的介電材料形成,其可藉由諸如CVD、PECVD、或類似者的任何適合的方法沉積。
在一些實施例中,在第二ILD 154與第一ILD 94、閘極遮罩116、源極/汲極觸點142、及接觸間隔物144之間形成蝕刻停止層(etch stop layer,ESL)152。ESL 152可包括介電材料,諸如氮化矽、氧化矽、氧氮化矽、或類似者,具有對第二ILD 154的蝕刻的高蝕刻選擇性。
在第21A圖至第21B圖中,源極/汲極觸點162及閘極觸點164分別形成為接觸源極/汲極觸點142及閘電極114。源極/汲極觸點162實體耦合且電耦合至源極/汲極觸點142。閘極觸點164實體耦合且電耦合至閘電極114。
作為形成源極/汲極觸點162及閘極觸點164的實例,形成穿過第二ILD 154及ESL 152的開口。可使用可接受的光學微影術及蝕刻技術形成開口。在開口中形
成諸如擴散阻障層、附著層、或類似者的襯裡(未單獨圖標)及導電材料。襯裡可包括鈦、氮化鈦、鉭、氮化鉭、或類似者。導電材料可係銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或類似者。可執行諸如CMP的平坦化製程以自第二ILD 154的頂表面移除多餘的材料。剩餘的襯裡及導電材料形成開口中的源極/汲極觸點162及閘極觸點164。源極/汲極觸點162及閘極觸點164可在不同的製程中形成,或可在相同的製程中形成。儘管示出為形成在相同的橫截面中,但應理解,源極/汲極觸點162及閘極觸點164中的各者可形成在不同的橫截面中,這可避免觸點短路。
第22A圖至第22B圖係根據一些實施例的FinFET的視圖。除了接觸間隔物144藉由CESL 92與閘極遮罩116的側壁實體地分開之外,這個實施例類似於第21A圖至第21B圖的實施例。具體地,在執行以移除源極/汲極觸點142的多餘材料的移除製程期間,減小閘極遮罩116的高度,直至閘極遮罩116及CESL 92的頂表面共面(在製程變化範圍內),使得接觸間隔物144藉由CESL 92與閘極遮罩116的側壁實體地分開。
實施例可達成優點。與初始形成接觸開口122為較大寬度相比,初始形成接觸開口122為較小寬度且接著將它們擴展至較大寬度可避免相鄰磊晶源極/汲極區88的短路。此外,形成保護層132有助於保護閘極遮罩116、第一ILD 94、及CESL 92,以便在形成金屬-半導體合金區134期間可避免接觸開口122的不期望的擴展。因此
可避免源極/汲極觸點142與相鄰導電特徵的短路。具體地,在第18A圖的橫截面中避免接觸開口122的擴展可降低源極/汲極觸點142與閘電極114或閘極觸點164之間短路的風險。類似地,在第18B圖的橫截面中避免接觸開口122的擴展可降低相鄰源極/汲極觸點142之間短路的風險。因此可提高製造良率。最後,用諸如羰基硫化物(COS)的蝕刻劑蝕刻保護層132允許源極/汲極觸點142形成至磊晶源極/汲極區88的主層88B(例如,高摻雜區),同時避免蝕刻主層88B。因此可提高裝置效能。
所揭示的FinFET實施例亦可應用於奈米結構裝置,諸如奈米結構(例如,奈米片、奈米導線、全環繞閘極、或類似者)場效電晶體(nanostructure field-effect transistor,NSFET)。在NSFET實施例中,鰭片由藉由圖案化通道層及犧牲層的交替層的堆疊而形成的奈米結構替換。虛設閘極結構及源極/汲極區以類似於上述實施例的方式形成。在移除虛設閘極結構之後,可部分或完全移除通道區中的犧牲層。替換閘極結構以類似於上述實施例的方式形成,替換閘極結構可部分或完全填充藉由移除犧牲層留下的開口,且替換閘極結構可部分或完全包圍NSFET裝置的通道區中的通道層。至替換閘極結構及源極/汲極區的ILD及觸點可以類似於上述實施例的方式形成。可形成如美國專利申請公開號第2016/0365414號中揭示的奈米結構裝置,其全文以引用的方式併入本文中。
在一個實施例中,一種形成電晶體之方法包括:在源極/汲極區及閘極遮罩上沉積保護層,閘極遮罩佈置在閘極結構上,閘極結構佈置在基板的通道區上,通道區鄰接源極/汲極區;蝕刻穿過保護層的開口,開口曝光源極/汲極區;在開口中及保護層上沉積一金屬;對金屬進行退火以在源極/汲極區上形成金屬-半導體合金區;及用清洗製程自開口移除金屬的殘留物,在清洗製程期間保護層覆蓋閘極遮罩。在方法的一些實施例中,清洗製程包括使用稀氫氟酸執行濕式蝕刻,且在濕式蝕刻期間不發生閘極遮罩的蝕刻。在方法的一些實施例中,源極/汲極區包括主層及結束層,且方法進一步包括:蝕刻穿過源極/汲極區的結束層的開口,開口曝光源極/汲極區的主層。在方法的一些實施例中,保護層包括氮化矽,且蝕刻開口包括使用羰基硫化物執行乾式蝕刻。在方法的一些實施例中,在乾式蝕刻期間不發生源極/汲極區的主層的蝕刻。在方法的一些實施例中,保護層具有在1nm至3nm範圍內的厚度。在一些實施例中,方法進一步包括:在源極/汲極區上沉積接觸蝕刻停止層(CESL);在CESL上形成層間介電質(ILD);形成穿過ILD及CESL的接觸開口;及在形成接觸開口之後,擴展接觸開口,在擴展接觸開口之後,保護層沉積在接觸開口中。在方法的一些實施例中,擴展接觸開口包括在室溫下用氟化氫及氨蝕刻ILD。
在一個實施例中,一種形成電晶體之方法包括:在源極/汲極區上沉積接觸蝕刻停止層(CESL);在CESL上
形成層間介電質(ILD);形成穿過ILD及CESL的接觸開口,接觸開口曝光源極/汲極區的頂表面及CESL的側壁;在形成接觸開口之後,藉由用各向同性蝕刻製程蝕刻ILD來擴展接觸開口;及在接觸開口中形成源極/汲極觸點。在方法的一些實施例中,各向同性蝕刻製程包括:在接觸開口中用蝕刻氣體溶液執行乾式蝕刻,在沒有電漿的情況下執行乾式蝕刻,蝕刻氣體溶液將ILD轉化為固相副產品;執行熱處理以將固相副產品昇華為氣相副產品;及將該氣相副產品自該接觸開口排出。在方法的一些實施例中,蝕刻氣體溶液包括氟化氫及氨,且在室溫下執行乾式蝕刻。在方法的一些實施例中,蝕刻氣體溶液包括氟化氫,且在20℃至40℃範圍內的溫度下執行乾式蝕刻。在方法的一些實施例中,在第一溫度下執行乾式蝕刻,且在第二溫度下執行熱處理,第二溫度大於第一溫度。在方法的一些實施例中,ILD包括氧化矽,且固相副產品包括氟矽酸銨。在一些實施例中,方法進一步包括:在基板的通道區上形成閘極結構,通道區鄰接源極/汲極區;在閘極結構上形成閘極遮罩;在擴展接觸開口之後,在閘極遮罩上及接觸開口中沉積保護層;接觸開口延伸穿過保護層;及在接觸開口中形成金屬-半導體合金區,同時保護層覆蓋閘極遮罩。在方法的一些實施例中,形成金屬-半導體合金區包括執行清洗製程,且在清洗製程期間不發生閘極遮罩的蝕刻。在方法的一些實施例中,接觸開口延伸穿過保護層包括用羰基硫化物蝕刻接觸開口。
在一個實施例中,一種電晶體包括:基板的通道區上的閘極結構;閘極結構上的閘極遮罩;鄰接通道區的源極/汲極區;連接至源極/汲極區的源極/汲極觸點,源極/汲極觸點具有有彎曲側壁的上部部分及有直側壁的下部部分;及源極/汲極觸點周圍的接觸間隔物,接觸間隔物接觸閘極遮罩的側壁。在一些實施例中,電晶體進一步包括:閘極結構與源極/汲極區之間的閘極間隔物;及閘極間隔物與接觸間隔物之間的接觸蝕刻停止層(CESL),CESL接觸閘極遮罩的側壁。在一些實施例中,電晶體進一步包括:源極/汲極區與源極/汲極觸點之間的金屬-半導體合金區,接觸間隔物接觸金屬-半導體合金區的側壁。
前述內容概述若干實施例的特徵,使得熟習此項技術者可更佳地理解本揭露的態樣。熟習此項技術者應瞭解,其可易於使用本揭露作為用於設計或修改用於實施本文中引入之實施例之相同目的及/或達成相同優勢之其他製程及結構的基礎。熟習此項技術者亦應認識到,此類等效構造並不偏離本揭露的精神及範疇,且此類等效構造可在本文中進行各種改變、取代、及替代而不偏離本揭露的精神及範疇。
A-A':橫截面
B-B':橫截面
50:基板
52:鰭片
56:隔離區/淺溝槽隔離區
58:通道區
88:磊晶源極/汲極區
112:閘極介電質
114:閘電極
Claims (10)
- 一種形成電晶體之方法,其包含以下步驟:在一源極/汲極區及一閘極遮罩上沉積一保護層,該閘極遮罩佈置在一閘極結構上,該閘極結構佈置在一基板的一通道區上,該通道區鄰接該源極/汲極區;蝕刻穿過該保護層的一開口,該開口曝光該源極/汲極區;在該開口中及該保護層上沉積一金屬;對該金屬進行退火以在該源極/汲極區上形成一金屬-半導體合金區;及用一清洗製程自該開口移除該金屬的殘留物,在該清洗製程期間該保護層覆蓋該閘極遮罩,其中該清洗製程包含使用稀氫氟酸執行一濕式蝕刻,且在該濕式蝕刻期間不發生該閘極遮罩的蝕刻。
- 如請求項1所述之方法,其中該保護層具有在1nm至3nm範圍內的一厚度。
- 如請求項1所述之方法,其中該源極/汲極區包含一主層及一結束層,該方法進一步包含以下步驟:蝕刻穿過該源極/汲極區的該結束層的該開口,該開口曝光該源極/汲極區的該主層。
- 如請求項3所述之方法,其中該保護層包含 氮化矽,且蝕刻該開口包含使用羰基硫化物執行一乾式蝕刻之步驟。
- 如請求項4所述之方法,其中在該乾式蝕刻期間不發生該源極/汲極區的該主層的蝕刻。
- 如請求項1所述之方法,其進一步包含以下步驟:在該源極/汲極區上沉積一接觸蝕刻停止層(CESL);在該CESL上形成一層間介電質(ILD);形成穿過該ILD及該CESL的一接觸開口;及在形成該接觸開口之後,擴展該接觸開口,在擴展該接觸開口之後,該保護層沉積在該接觸開口中。
- 一種形成電晶體之方法,其包含以下步驟:在一源極/汲極區上沉積一接觸蝕刻停止層(CESL);在該CESL上形成一層間介電質(ILD);形成穿過該ILD及該CESL的一接觸開口,該接觸開口曝光該源極/汲極區的一頂表面及該CESL的一側壁;在形成該接觸開口之後,藉由用一各向同性蝕刻製程蝕刻該ILD來擴展該接觸開口;及在該接觸開口中形成一源極/汲極觸點。
- 如請求項7所述之方法,其中該各向同性蝕 刻製程包含以下步驟:在該接觸開口中用一蝕刻氣體溶液執行一乾式蝕刻,該乾式蝕刻在沒有電漿的情況下執行,該蝕刻氣體溶液將該ILD轉化為一固相副產品;執行一熱處理以將該固相副產品昇華為一氣相副產品;及將該氣相副產品自該接觸開口排出。
- 如請求項7所述之方法,其進一步包含以下步驟:在一基板的一通道區上形成一閘極結構,該通道區鄰接該源極/汲極區;在該閘極結構上形成一閘極遮罩;在擴展該接觸開口之後,在該閘極遮罩上及該接觸開口中沉積一保護層;該接觸開口延伸穿過該保護層;及在該接觸開口中形成一金屬-半導體合金區,同時該保護層覆蓋該閘極遮罩。
- 一種電晶體,其包含:一基板的一通道區上的一閘極結構;該閘極結構上的一閘極遮罩;鄰接該通道區的一源極/汲極區;一源極/汲極觸點,其連接至該源極/汲極區,該源極/汲 極觸點具有有多個彎曲側壁的一上部部分及有多個直側壁的一下部部分;及該源極/汲極觸點周圍的一接觸間隔物,該接觸間隔物接觸該閘極遮罩的一側壁。
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CN114975611A (zh) | 2022-08-30 |
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