TWI801628B - 微電子工件中矽鍺奈米線形成期間保護氮化物層的方法 - Google Patents

微電子工件中矽鍺奈米線形成期間保護氮化物層的方法 Download PDF

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TWI801628B
TWI801628B TW108125035A TW108125035A TWI801628B TW I801628 B TWI801628 B TW I801628B TW 108125035 A TW108125035 A TW 108125035A TW 108125035 A TW108125035 A TW 108125035A TW I801628 B TWI801628 B TW I801628B
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silicon
nitride
etch
layers
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TW202020965A (zh
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吉田祐介
克里斯多佛 卡塔諾
克里斯多佛 塔洛内
尼可拉斯 喬伊
謝爾蓋 沃羅寧
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日商東京威力科創股份有限公司
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
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Abstract

在此說明形成矽鍺奈米線並且同時減少或消除氮化物層(例如遮罩與間隔件)之侵蝕的實施例，於矽鍺奈米線形成期間，該侵蝕係在矽相對於矽鍺之選擇性蝕刻期間所引起。氧化物層用以在矽鍺(SiGe)奈米線形成期間保護氮化物層。尤其，形成包含氧化物/氮化物/氧化物層的多層間隔件，以在用以形成例如用於場效電晶體(FET，field effect transistors)之矽鍺奈米線的選擇性矽蝕刻製程期間保護氮化物層。多層間隔件允許達到對於氮化物層的目標侵蝕位準。

Description

微電子工件中矽鍺奈米線形成期間保護氮化物層的方法
[相關申請案]
本申請案係主張下列共同申請中之臨時申請案的優先權：美國臨時專利申請案第62/698,430號，申請於2018年7月16日，發明名稱為「METHODS TO PROTECT NITRIDE LAYERS DURING FORMATION OF SILICON GERMANIUM NANO-WIRES IN MICROELECTRONIC WORKPIECES」；以及美國臨時專利申請案第62/729,047號，申請於2018年9月10日，發明名稱為「METHODS TO PROTECT NITRIDE LAYERS DURING FORMATION OF SILICON GERMANIUM NANO-WIRES IN MICROELECTRONIC WORKPIECES」，其整體內容乃藉由參考文獻方式合併於此。
本揭露內容係與用於微電子工件製造的方法相關，該方法包含在微電子工件上形成圖案化結構。
在微電子工件內的裝置形成一般係涉及與基板上之若干材料層之形成、圖案化、以及移除有關的一系列製造技術。對於形成在微電子工件上 的某些半導體裝置而言，係形成矽奈米線以生產半導體裝置。對於矽奈米線形成而言，通常係使用矽與矽鍺的多層堆疊體。首先藉由垂直蝕刻製程來形成這些多層堆疊體，然後以對矽具有選擇性的方式橫向蝕刻犧牲矽鍺層，以形成懸空的矽奈米線。
對於矽鍺奈米線形成而言，以對矽鍺具有選擇性的方式橫向蝕刻堆疊之鰭層內的矽。然而，對矽鍺之選擇性矽蝕刻的其中一關鍵性挑戰為對通常被使用作為硬遮罩與作為間隔件之氮化物層的選擇性。例如，氮化物硬遮罩及/或間隔件經常被使用作為奈米線場效電晶體(FET，field effect transistors)之閘極與源極-汲極區域之間的保護層。此外，如上所指出，吾人瞭解氮化物遮罩與間隔件亦可含有附加的元素，例如硼、碳、及/或氧。由於在標準製程中對氮化物的不佳選擇性，所以在橫向矽蝕刻期間，包含凹部與針孔的顯著侵蝕通常發生在氮化物遮罩與間隔件內。這些凹部與針孔可能會引起嚴重的缺陷，例如源極/汲極材料的不規則磊晶成長以及閘極與源極/汲極之間的電氣短路。然而，對於習知的製程流程而言，因為在對矽鍺具有選擇性之矽蝕刻期間的氮化物侵蝕，所以不存在被證實用於矽鍺奈米線形成的方法。
圖1A-B(先前技術)提供基於習知製程流程的示範實施例，其中對氮化物遮罩及/或間隔件的侵蝕係發生在選擇性矽蝕刻期間。例如，氮氧化物(NO)一般被認為係矽(Si)對矽鍺(SiGe)之選擇性蝕刻的關鍵性成分，但NO也會增強氮化物(SiN)蝕刻。此種增強之氮化物蝕刻會引起氮化物遮罩與間隔件結構的不期望侵蝕。
首先觀看圖1A(先前技術)，顯示基於習知製程的示範製程流程圖，於此處，用於矽鍺奈米線形成的矽選擇性蝕刻係在例如氮化物硬遮罩與間 隔件結構之氮化物層內引起侵蝕。尤其，氮化物間隔件侵蝕與氮化物遮罩侵蝕係發生在透過相對於SiGe層之Si層橫向選擇性蝕刻的Si凹陷期間。視圖100係描繪在選擇性矽蝕刻之前的多層結構，以及視圖110係描繪在如箭頭105所標示的選擇性矽蝕刻之後的多層結構。
如視圖100所示，Si層112與SiGe層114被堆疊成鰭層的部分，其作為可用以形成奈米線場效電晶體(FET)的多層結構。該多層結構包含形成在基板116上的Si與SiGe層112/114、虛擬閘極122、氮化物間隔件125、以及氮化物硬遮罩120。吾人注意到，例如，該虛擬閘極可由矽所製成，然而其他的虛擬閘極材料亦可被使用。其他的變化亦可在該多層結構內被加以實施。
如視圖110所示，如箭頭105所標示的選擇性Si相對於SiGe蝕刻，係在如就氮化物硬遮罩120與氮化物間隔件125所顯示的氮化物遮罩/間隔件層內引起侵蝕。就其本身而言，已透過Si層112的選擇性橫向蝕刻而由SiGe層114形成SiGe奈米線。然而，由於氮化物對一般Si對SiGe選擇性蝕刻化學品(例如，使用NO來提供選擇性矽蝕刻者)的敏感性，所以不期望的侵蝕已在氮化物硬遮罩120與氮化物間隔件125內發生。
圖1B(先前技術)提供基於習知製程的示範製程流程圖，於此處，在SiGe奈米線FET形成期間接著執行SiGe奈米線(NW，nano-wire)釋出製程。此種釋出(release)製程係移除Si層112並且留下SiGe層114以作為露出之奈米線。然而，此種NW釋出製程會導致在圖1A(先前技術)所示之虛擬閘極122取出後之露出區域之邊緣上的氮化物間隔件125的侵蝕。視圖150係描繪在用以移除Si層112之選擇性矽蝕刻之前的多層結構，以及視圖160係描繪在如箭頭155所標示的選擇性矽蝕刻之後的多層結構。
如視圖150所示，氮化物間隔件174也已加入在SiGe層114之間，以填充在Si層112的橫向蝕刻區域內。此外，也已加入源極與汲極區域172，以及可例如使用經摻雜之SiGe及/或另一導電材料來形成這些源極與汲極區域172。也已形成氧化物層168。此外，如視圖150所示，在如箭頭155所標示的SiGe奈米線釋出製程之前，在如圖1A(先前技術)之視圖110所示於氮化物間隔件125內發生侵蝕之處，可使用氮化物間隔件125的再沉積來重組氮化物間隔件125。
如視圖160所示，如箭頭155所標示的選擇性Si相對於SiGe蝕刻，係在如就氮化物間隔件125所顯示的氮化物間隔件層內引起侵蝕。就其本身而言，已透過Si層112的選擇性蝕刻而在SiGe層114中釋出SiGe奈米線。然而，由於氮化物對一般Si對SiGe選擇性蝕刻化學品(例如，使用NO來提供選擇性矽蝕刻者)的敏感性，所以不期望的侵蝕已在氮化物間隔件125內發生。
在此說明形成矽鍺奈米線並且同時減少或消除氮化物層(例如遮罩與間隔件)之侵蝕的實施例，於矽鍺奈米線形成期間，該侵蝕係在矽相對於矽鍺之選擇性蝕刻期間所引起。如在此所述，氧化物層(例如SiO2)用以在矽鍺(SiGe)奈米線形成期間保護氮化物層(例如SiN)。尤其，形成包含氧化物/氮化物/氧化物層的多層間隔件，以在用以形成矽鍺奈米線的矽回蝕(etch back)製程期間保護氮化物層。就其本身而言，達到對於氮化物層的目標侵蝕位準。不同或附加的特徵、變化、以及實施例亦可被實現，且相關的系統與方法亦可被利用。
作為一實施例，揭露一種用以處理微電子工件的方法，其包含提供具有一虛擬閘極與一下伏層的一基板，該下伏層包含鰭層，該等鰭層包含矽 層與矽鍺層；形成多層間隔件以保護該虛擬閘極；以及執行該等鰭層內之該等矽層的橫向凹陷蝕刻，於此處，該橫向凹陷蝕刻為矽相對於矽鍺的選擇性蝕刻，且該等多層間隔件包含一內氧化物層、一氮化物層、以及一外氧化物層。
在附加的實施例中，該內氧化物層與該外氧化物層包含二氧化矽(SiO2)，以及該氮化物層包含矽氮化物(SiN)。作為進一步之實施例，該內氧化物層、該外氧化物層、或該氮化物層之至少一者包含一或多種附加的元素。作為又進一步之實施例，該附加的元素包含硼、碳、或氧之至少一者。
在附加的實施例中，由於該外氧化物層所提供的保護作用，所以在該橫向凹陷蝕刻期間達到對於該氮化物層的目標侵蝕位準。
在附加的實施例中，該方法更包含在形成該等多層間隔件之前，形成一多層帽蓋結構以保護該虛擬閘極，而該多層帽蓋結構包含一氮化物硬遮罩以及一氧化物帽蓋。在進一步之實施例中，該多層帽蓋結構在執行該橫向凹陷蝕刻之前係被露出。
在附加的實施例中，該方法亦包含在執行該橫向凹陷蝕刻之前，執行該等多層間隔件的回蝕。在附加的實施例中，用於該橫向凹陷蝕刻的一蝕刻化學品包含氮氧化物。
在附加的實施例中，該方法亦包含在該橫向凹陷蝕刻之後形成一氧化物間隔件層，並且執行該氧化物間隔件層的回蝕，以露出該等矽鍺層，且在該等矽鍺層之間留下氧化物間隔件。在進一步之實施例中，該方法亦包含形成一氮化物間隔件層並且執行該氮化物間隔件層的回蝕，以在該等矽鍺層之間留下氮化物間隔件。在又進一步之實施例中，該等矽鍺層係形成作為一場效電晶體(FET，field effect transistors)的部分。在進一步之實施例中，該方法包含形 成用於該FET的源極與汲極區域。在又進一步之實施例中，該等源極與汲極區域係形成作為磊晶成長區域。
在附加的實施例中，該方法亦包含取出該虛擬閘極，以露出包含該等矽層與該等矽鍺層的該等鰭層。在進一步之實施例中，該虛擬閘極為一矽虛擬閘極。在進一步之實施例中，該方法亦包含在取出該虛擬閘極之前，執行一平坦化製程。
在附加的實施例中，該方法包含執行露出之該等鰭層內之該等矽層的層移除蝕刻，以留下露出之矽鍺奈米線，於此處，該層移除蝕刻為矽相對於矽鍺的選擇性蝕刻。在進一步之實施例中，由於該內氧化物層所提供的保護作用，所以在該層移除蝕刻期間達到對於該氮化物層的目標侵蝕位準。在進一步之實施例中，用於該層移除蝕刻的一蝕刻化學品包含氮氧化物。作為進一步之實施例，該方法包含執行氧化物蝕刻，以移除該內氧化物層。
作為進一步之實施例，該方法包含在露出之該等矽鍺奈米線之上形成一或多個附加的層。作為又進一步之實施例，該一或多個附加的層包含一介電層或一金屬層之至少一者。
100:視圖
105:箭頭
110:視圖
112:Si層
114:SiGe層
116:基板
120:氮化物硬遮罩
122:虛擬閘極
125:氮化物間隔件
150:視圖
155:箭頭
160:視圖
168:氧化物層
172:源極/汲極區域
174:氮化物間隔件
200:實施例
202:氧化物帽蓋
204:氧化物層
205:氮化物層
206:氧化物層
207:多層間隔件
208:示範實施例
210:示範實施例
215:示範實施例
220:示範實施例
225:示範實施例
230:示範實施例
235:示範實施例
240:示範實施例
242:氧化物層
244:氧化物間隔件
245:示範實施例
250:示範實施例
252:氮化物間隔件層
254:氮化物間隔件
255:示範實施例
260:示範實施例
272:介電層
274:介電層
276:金屬層
300:示範實施例
302:方塊
304:方塊
306:方塊
藉著參考下列說明內容並結合隨附圖式便可獲得對本發明及其優點之更完整瞭解，其中相似的參考符號係指相似的特徵。然而，吾人應注意到，隨附圖式僅說明所揭露之概念的示範實施例，並因此不應被視為範圍之限制，因所揭露之概念可容許其他等效實施例。
圖1A-1B說明習知製程流程，其中對氮化物遮罩及/或間隔件的侵蝕係在選擇性矽蝕刻期間發生。
圖2A-2O說明由本發明之製程步驟所產生的結構。
圖3說明本發明之製程的流程圖。
如在此所述，揭露在微電子工件生產中矽鍺奈米線形成期間保護氮化物層的方法。如在此所述，堆疊之矽鍺奈米線係由矽與矽鍺的鰭層所形成，該等鰭層係形成在作為微電子工件的基板上。這些矽鍺奈米線可被形成作為例如奈米線場效電晶體(FET)的部分，且尤其係作為p通道奈米線FET的部分，於此處，使用此種結構可實現較高的性能。如進一步在此所述，氧化物層(例如SiO2)係用以形成氧化物/氮化物/氧化物的多層結構，其在堆疊之矽(Si)與矽鍺(SiGe)鰭層的選擇性矽蝕刻期間保護氮化物層(例如SiN)。亦注意到，除了矽氮化物(SiN)以外，氮化物層通常包含附加的元素(例如碳(C)、硼(B)、氧(O))、及/或其他添加物。同樣地，注意到，除了二氧化矽(SiO2)以外，氧化物層通常包含附加的元素。當利用在此所述的製程技術時仍亦可實現其他的優點與實施例。
如以上就習知製程所述，由於氮化物對一般Si對SiGe選擇性蝕刻化學品(例如，使用NO來提供選擇性矽蝕刻者)的敏感性，所以不期望的侵蝕會在氮化物遮罩與間隔件層內發生。在此所揭露之實施例係提供在因為選擇性矽蝕刻而形成SiGe奈米線期間減少或防止氮化物層(例如氮化物遮罩與氮化物間隔件層)之侵蝕的技術。就其本身而言，所揭露之實施例可在不遭遇到使用習知製 程所會發生之氮化物侵蝕問題的情況下，以類似於形成矽奈米線的方式進行微電子工件中矽鍺奈米線的大量生產。
在一實施例中，在此所揭露之方法包含虛擬閘極結構(例如，矽虛擬閘極)上之多層間隔件的形成。這些多層間隔件包含內氧化物層、氮化物層、以及外氧化物層。外氧化物層在矽鍺層之間的犧牲矽層部分橫向凹陷期間保護矽氮化物間隔件。如進一步於下文中所述，為了在露出之奈米線區域上形成矽氮化物間隔件，在矽鍺層之間的犧牲矽層部分凹陷之後，沉積矽氮化物並且將其部分回蝕。例如，在取出(pull)製程已移除矽虛擬閘極之後，內矽氧化物層在犧牲矽層移除期間保護矽氮化物間隔件。吾人注意到，可例如藉由矽氧化物的沉積或下伏含矽材料的表面氧化來形成內氧化物層。其他形成技術亦可被使用。
作為一實施例，在矽氮化物間隔件形成之前，該方法包含附加的矽氧化物間隔件形成步驟。對於本實施例而言，在矽犧牲層部分凹陷之後，沉積矽氧化物並且將其部分回蝕。之後以矽氮化物重複此種沉積與回蝕步驟，以在Si-Ge層之間形成外氮化物間隔件。於虛擬閘極取出之情況下，在使矽鍺奈米線露出的奈米線釋出製程期間，附加的矽氧化物層在犧牲矽層完全移除期間保護Si-Ge層之間的這些外矽氮化物間隔件。
藉著所揭露的實施例以實現若干優點。如在此所述，在矽選擇性蝕刻期間減少或防止矽氮化物侵蝕。矽選擇性蝕刻一般係相對於矽鍺而對矽具有選擇性，但一般不會同樣對矽氮化物具有選擇性並且傾向侵蝕氮化物。又，所揭露之實施例允許以類似於矽奈米線形成的方式來進行矽鍺奈米線之形成，即：(1)使用包含矽與矽鍺之多層堆疊體的鰭層；(2)使用矽氮化物作為間隔件/遮罩材料，即使其在對矽鍺具有選擇性的矽蝕刻期間亦會被蝕刻或侵蝕；以及(3) 加入矽氧化物間隔件形成與移除之步驟，其用以形成氧化物/氮化物/氧化物的多層結構，以在選擇性矽蝕刻期間保護矽氮化物遮罩/間隔件。當利用在此所述的製程技術時仍亦可實現其他的優點與實施例。
現在觀看圖2A-O，進一步說明一製程流程的一示範實施例，其係使用氧化物/氮化物/氧化物層之多層間隔件結構，以在矽相對於矽鍺的選擇性蝕刻期間保護矽氮化物層。使用此種氧化物/氮化物/氧化物層的多層結構，因為內矽氧化物層及/或外矽氧化物層所提供的保護作用，所以在矽相對於矽鍺之選擇性蝕刻製程期間達到對於矽氮化物層的目標侵蝕位準。又，附加的氧化物層亦可用以保護形成在矽鍺層之間的附加之氮化物間隔件。進一步注意到，如在先前解決方案中所見，被減少或防止的侵蝕係包含會以其他方式形成在矽氮化物層內的針孔與凹部。
圖2A係實施例200的一製程圖，於此處，包含氧化物/氮化物/氧化物層的多層間隔件結構係形成在虛擬閘極122以及包含Si層112與SiGe層114之堆疊體的鰭層之上。虛擬閘極122已事先形成在多層Si與SiGe結構的頂部上，該多層Si與SiGe結構已事先形成在基板116上。氧化物帽蓋202也已形成在氮化物硬遮罩120之上，以提供多層帽蓋結構。氮化物硬遮罩120係事先形成在虛擬閘極122之上。如圖所示，氧化物/氮化物/氧化物層204/205/206的多層間隔件結構係形成在其他結構之上。對於此種多層間隔件結構而言，內氧化物層204首先形成在位於基板上之包含虛擬閘極122以及鰭層(其包含Si/SiGe層112/114之堆疊體)的結構之上。氮化物層205接著形成在內氧化物層204之上。外氧化物層206之後形成在氮化物層205之上。吾人注意到，可例如藉由矽氧化物的沉積或下伏含矽材料的表面氧化來形成內氧化物層204。其他的形成技術亦可被使用。亦注意 到，除了矽氮化物(SiN)以外，氮化物層通常包含附加的元素(例如碳(C)、硼(B)、氧(O))、及/或其他添加物。同樣地，注意到，除了二氧化矽(SiO2)以外，氧化物層通常包含附加的元素。其他的變化亦可被實現。
圖2B係示範實施例208的一製程圖，於此處，已執行間隔件回蝕製程而留下氧化物/氮化物/氧化物層204/205/206以作為鄰接於虛擬閘極122的多層間隔件207。例如，可執行一或多個蝕刻製程而在包含Si層112與SiGe層114的鰭層之上留下堆疊的結構，該堆疊的結構包含虛擬閘極122與多層間隔件207。
圖2C係示範實施例210的一製程圖，於此處，已執行鰭凹陷製程步驟而露出包含Si層112與SiGe層114之鰭層的側邊。就其本身而言，係形成一鰭結構，於此處，Si-SiGe鰭層112/114係位於虛擬閘極122下方的多層結構。
圖2D係示範實施例215的一製程圖，於此處，已執行相對於矽鍺而對矽具有選擇性的橫向凹陷蝕刻製程。雖然此種橫向選擇性矽蝕刻對SiN具有不佳的選擇性(此可能引起對SiN的侵蝕，其為習知製程中的情況)，但氮化物層205與氮化物硬遮罩120係受到包含氧化物/氮化物/氧化物層204/205/206的多層間隔件207與氧化物帽蓋202所保護。尤其，多層間隔件207的外氧化物層206係保護位於內/外氧化物層204/206之間的氮化物層205。作為一範例，矽層112的橫向選擇性蝕刻包含具有傾向侵蝕氮化物之氮氧化物(NO)的蝕刻化學品，然而，相對於矽鍺而對矽具有選擇性的其他蝕刻化學品亦可被使用。
圖2E係示範實施例220的一製程圖，於此處，已執行氧化物間隔件沉積製程，以在多層間隔件207、虛擬閘極122、以及Si-SiGe層112/114之上形成附加的氧化物層242。注意到，在此種氧化物間隔件沉積之後，外氧化物層206實際上係變為附加之氧化物層242的部分。
圖2F係示範實施例225的一製程圖，於此處，已執行氧化物間隔件回蝕，以移除附加之氧化物層242的一部分並且在SiGe層114之間留下氧化物間隔件244。此種回蝕製程可為等向性蝕刻。又，此種回蝕製程可從多層間隔件結構將外氧化物層移除。
圖2G係示範實施例230的一製程圖，於此處，已執行氮化物間隔件沉積，以在剩餘之氧化物/氮化物層204/205、虛擬閘極122、以及包含Si/SiGe層112/114之鰭層之上形成氮化物間隔件層252。注意到，在此種氮化物間隔件沉積之後，氮化物層205實際上係變為氮化物間隔件層252的部分。
圖2H係示範實施例235的一製程圖，於此處，已執行氮化物間隔件回蝕，以移除氮化物間隔件層252的一部分並且在SiGe層114之間留下氮化物間隔件254。
圖2I係示範實施例240的一製程圖，於此處，已執行磊晶成長製程以形成磊晶層(例如矽磊晶層)，並且一同執行圖案化及/或蝕刻製程以形成源極與汲極區域172。如圖所示，這些源極/汲極區域172係形成鄰接於包含Si/SiGe層112/114的鰭層。此外，源極/汲極區域172的一部分係形成在SiGe層114之間而鄰接於氮化物間隔件254。
圖2J係示範實施例245的一製程圖，於此處，已執行氧化物沉積製程，以在剩餘之氧化物/氮化物層204/205、虛擬閘極122、源極/汲極區域172、以及包含Si/SiGe層112/114的鰭層之上形成氧化物層168。
圖2K係示範實施例250的一製程圖，於此處，已執行例如化學機械平坦化(CMP，chemical mechanical planarization)的平坦化製程，以使實施例245 中之結構的頂部平坦化。如圖所示，可在此種平坦化製程期間移除氮化物硬遮罩120與氧化物帽蓋202。
圖2L係示範實施例255的一製程圖，於此處，已從該結構取出圖2K所示之虛擬閘極122而露出包含Si層112與SiGe層114的鰭層。如上所述，虛擬閘極122可為矽虛擬閘極，其係在例如取出製程的矽蝕刻中被移除。
圖2M係示範實施例260的一製程圖，於此處，已執行相對於SiGe而對Si具有選擇性的蝕刻製程。此種矽選擇性蝕刻製程係移除作為Si-SiGe多層結構之鰭層中的Si層112而留下SiGe層114以作為露出之奈米線。雖然此種Si選擇性蝕刻對SiN具有不佳的選擇性(此可能引起對氮化物的侵蝕，其為習知製程中的情況)，但氮化物層205與氮化物間隔件254係受到保護。尤其，氮化物層205係受到仍繼續存在而作為多層間隔件207(其起初係以如圖2B所示之氧化物/氮化物/氧化物層204/205/206所形成)之部分的內氧化物層204所保護。氮化物間隔件254係受到氧化物間隔件244所保護。作為一範例，矽層112的選擇性層移除蝕刻可包含具有傾向侵蝕氮化物之氮氧化物(NO)的蝕刻化學品，然而，相對於矽鍺而對矽具有選擇性的其他蝕刻化學品亦可被使用。
圖2N係一製程圖，於此處，已使用氧化物蝕刻來執行氧化物間隔件移除製程而移除氧化物間隔件244。
圖2O係一製程圖，於此處，已執行附加的沉積製程，以在由SiGe層114所形成之露出的SiGe奈米線之上形成一或多個附加的層。例如，該一或多個附加的層可為介電層272/274(例如高介電常數(高k)層)、金屬層276(例如金屬閘極插栓)、及/或其他期望材料層。
圖3係示範實施例300的一製程流程圖，於此處，形成包含氧化物/氮化物/氧化物層的多層間隔件，以在用於微電子工件製造之SiGe奈米線形成期間保護氮化物層。在方塊302中，提供具有虛擬閘極與下伏層的基板，該下伏層包含矽與矽鍺的鰭層。在方塊304中，形成多層間隔件以保護虛擬閘極，而該多層間隔件結構包含內氧化物(SiO2)層、氮化物(SiN)層、以及外氧化物(SiO2)層。在方塊306中，執行鰭層內之矽層的橫向凹陷蝕刻，而該橫向凹陷蝕刻為矽相對於矽鍺的選擇性蝕刻。進一步注意到，由於外氧化物層所提供的保護作用，所以可在該橫向凹陷蝕刻期間達到對於氮化物層的目標侵蝕位準。又，在一或多個附加之製程步驟期間，內氧化物層係用以在選擇性矽蝕刻期間保護氮化物層。又進一步，亦可在提供矽相對於矽鍺之選擇性蝕刻的蝕刻製程期間，沉積附加的氧化物層，以保護氮化物間隔件、遮罩、及/或結構。當利用在此所述的技術時仍亦可使用附加及/或不同的製程步驟。
吾人注意到，一或多個沉積製程可用以形成在此所述的材料層。例如，一或多個沉積可使用下者加以實現：化學氣相沉積(CVD，chemical vapor deposition)、電漿增強CVD(PECVD，plasma enhanced CVD)、物理氣相沉積(PVD，physical vapor deposition)、原子層沉積(ALD，atomic layer deposition)、及/或其他沉積製程。對於電漿沉積製程而言，可使用前驅物氣體混合物，其包含但不限於在種種壓力、功率、流量以及溫度條件下，與一或多種稀釋氣體(例如氬、氮等等)結合的碳氫化合物、碳氟化合物、或含氮之碳氫化合物。可使用光微影、極紫外線(EUV，extreme ultra-violet)微影、及/或其他微影製程來實現關於光阻(PR，photo resist)層的微影製程。可使用電漿蝕刻製程、放電蝕刻製程、及/或其他期望蝕刻製程來實現蝕刻製程。例如，可使用含有碳氟化合物、氧、 氮、氫、氬、及/或其他氣體的電漿來實現電漿蝕刻製程。此外，可控制製程步驟的操作變數，以確保在穿孔(via)形成期間達到穿孔的臨界尺寸(CD，critical dimension)目標參數。這些操作變數可包含例如腔室溫度、腔室壓力、氣體的流率、在電漿產生時施加至電極組件的頻率及/或功率、及/或處理步驟的其他操作變數。當利用在此所述的技術時仍亦可進行變化。
吾人注意到，整份說明書中所提及的「一個實施例」或「一實施例」意味著關於該實施例所描述之特定的特徵、結構、材料、或特性係包含於本發明的至少一個實施例中，但不表示上述特徵、結構、材料、或特性係存在於每個實施例中。因此，在整份說明書中各處出現的「在一個實施例中」或「在一實施例中」之用語，係不必然關於本發明的相同實施例。再者，在一或多個實施例中，特定的特徵、結構、材料、或特性可以任何適當的方式加以組合。各種附加的層及/或結構可被包含及/或所描述的特徵可在其他實施例中被省略。
根據本發明，如在此所使用之「微電子工件」一般係指受到處理的物件。微電子工件可包括裝置(尤其係半導體或其他電子裝置)的任何材料部份或結構，並且例如可為基底基板結構，如半導體基板、或在基底基板結構上或覆蓋於其上的層(例如薄膜)。因此，工件並非意欲限制於圖案化或未圖案化的任何特定基底結構、下伏層或覆蓋層，而係考量包括任何此種層或基底結構、以及層及/或基底結構的任何組合。本說明在下文中或許參照特定種類的基板，但這僅是為了說明之目的而非限制。
如在此所使用之用語「基板」係意指並包含於其上形成材料的基底材料或結構。吾人將明白基板可包含單一材料、複數層不同材料、其中具有不同材料或不同結構之區域的一層或複數層等等。這些材料可包含半導體、絕 緣體、導體、或其組合。舉例來說，基板可為半導體基板、支撐結構上的基底半導體層、具有形成於其上之一或多個層、結構或區域的金屬電極或半導體基板。基板可為習知矽基板或包含半導電性材料層之其他主體基板。如在此所使用之用語「主體基板」不僅意指且包含矽晶圓，還有矽覆絕緣體(SOI，silicon-on-insulator)基板(例如矽覆藍寶石(SOS，silicon-on-sapphire)基板及矽覆玻璃(SOG，silicon-on-glass)基板)、基底半導體基部上之矽磊晶層、以及其他半導體或光電材料(例如矽鍺、鍺、砷化鎵、氮化鎵、以及磷化銦)。基板可經摻雜或未摻雜。
用以處理微電子工件的系統與方法係說明於各種實施例中。相關領域中具有通常知識者將察知該等不同實施例可在不具有一或多個具體細節或在具有其他替代及/或附加的方法、材料、或構件的情況下實施。在其他情況下，廣為人知的結構、材料或操作係未詳細顯示或描述，以免混淆本發明之不同實施例的實施態樣。同樣地，為了解釋之目的而提出具體的數量、材料、以及結構，以提供對本發明的全面瞭解。然而，本發明可在不具有具體細節的情況下被加以實施。再者，吾人瞭解到，圖式所示的各種實施例僅為例示代表，未必按照比例繪製。
鑑於此說明內容，所述系統與方法的進一步修改及替代實施例對於熟悉本技術領域者將顯而易見。因此，吾人將察知，所述系統與方法不受限於這些示範的配置。吾人應理解此處顯示及敘述之系統與方法的形式應視為示範的實施例。各種改變可在實施例中做成。因此，雖然本發明於此處係參照具體實施例而敘述，但各種修改及變更仍可在不離開本發明之範圍的情況下做成。因此，應將說明書及圖式視為例示性而非限制性，且欲將此種修改包含在 本發明的範圍內。又，此處所述關於具體實施例之任何益處、優點、或對於問題的解決方案皆不意圖被解讀為任何或所有請求項的關鍵、所需、或必要的特徵或元件。
300:示範實施例
302:方塊
304:方塊
306:方塊

Claims (24)

  1. 一種用以處理微電子工件的方法，包含下列步驟：提供具有一虛擬閘極與一下伏層的一基板，該下伏層包含鰭層，該等鰭層包含矽層與矽鍺層；形成多層間隔件以保護該虛擬閘極，該等多層間隔件包含一內氧化物層、一氮化物層、以及一外氧化物層；以及執行該等鰭層內之該等矽層的橫向凹陷蝕刻，而該橫向凹陷蝕刻為矽相對於矽鍺的選擇性蝕刻，其中由於該外氧化物層所提供的保護作用，所以在該橫向凹陷蝕刻期間達到對於該氮化物層的目標侵蝕位準。
  2. 一種用以處理微電子工件的方法，包含下列步驟：提供具有一虛擬閘極與一下伏層的一基板，該下伏層包含鰭層，該等鰭層包含矽層與矽鍺層；形成多層間隔件以保護該虛擬閘極，該等多層間隔件包含一內氧化物層、一氮化物層、以及一外氧化物層；執行該等鰭層內之該等矽層的橫向凹陷蝕刻，而該橫向凹陷蝕刻為矽相對於矽鍺的選擇性蝕刻；以及該方法更包含在該橫向凹陷蝕刻之後形成一氧化物間隔件層，並且執行該氧化物間隔件層的回蝕，以露出該等矽鍺層，且在該等矽鍺層之間留下氧化物間隔件。
  3. 如申請專利範圍第2項之用以處理微電子工件的方法，更包含形成一氮化物間隔件層，並執行該氮化物間隔件層的回蝕，以在該等矽鍺層之間留下氮化物間隔件。
  4. 如申請專利範圍第3項之用以處理微電子工件的方法，其中該等矽鍺層係形成作為一場效電晶體(FET，field effect transistors)的部分。
  5. 一種用以處理微電子工件的方法，包含下列步驟：提供具有一虛擬閘極與一下伏層的一基板，該下伏層包含鰭層，該等鰭層包含矽層與矽鍺層；形成多層間隔件以保護該虛擬閘極，該等多層間隔件包含一內氧化物層、一氮化物層、以及一外氧化物層，其中在該等多層間隔件的形成期間，該等多層間隔件係形成在該虛擬閘極之上及該下伏層之上的位置，且該等多層間隔件亦沿該虛擬閘極之側邊而形成；執行該等多層間隔件的回蝕，以移除該虛擬閘極之上及該下伏層之上的該等多層間隔件之部分，但留下沿著該虛擬閘極之側邊的該等多層間隔件之部分；以及執行該等鰭層內之該等矽層的橫向凹陷蝕刻，而該橫向凹陷蝕刻為矽相對於矽鍺的選擇性蝕刻。
  6. 如申請專利範圍第5項之用以處理微電子工件的方法，更包含在形成該等多層間隔件之前，在該虛擬閘極之上形成一帽蓋，該帽蓋包含一氧化物帽蓋或一氮化物硬遮罩之至少一者。
  7. 如申請專利範圍第6項之用以處理微電子工件的方法，其中該帽蓋為一多層帽蓋結構，該多層帽蓋結構包含該氮化物硬遮罩及該氧化物帽蓋兩者，該方法更包含在該多層帽蓋結構之上的位置執行該等多層間隔件的回蝕，使得該多層帽蓋結構在執行該橫向凹陷蝕刻之前係被露出。
  8. 如申請專利範圍第5項之用以處理微電子工件的方法，更包含在執行該回蝕之後且在執行該橫向凹陷蝕刻之前，執行鰭凹陷製程步驟，以露出該等鰭層的側邊。
  9. 如申請專利範圍第8項之用以處理微電子工件的方法，更包含在執行該橫向凹陷蝕刻之後，形成氧化物間隔件或氮化物間隔件之至少一者，以在該等矽鍺層之間提供氧化物間隔件或氮化物間隔件之至少一者。
  10. 如申請專利範圍第5項之用以處理微電子工件的方法，其中該內氧化物層及該外氧化物層包含二氧化矽(SiO2)，且該氮化物層包含矽氮化物(SiN)。
  11. 如申請專利範圍第10項之用以處理微電子工件的方法，其中該內氧化物層、該外氧化物層、或該氮化物層之至少一者包含一或更多附加的元素。
  12. 如申請專利範圍第11項之用以處理微電子工件的方法，其中該附加的元素包含硼、碳、或氧之至少一者。
  13. 如申請專利範圍第5項之用以處理微電子工件的方法，其中用於該橫向凹陷蝕刻的一蝕刻化學品包含氮氧化物。
  14. 如申請專利範圍第13項之用以處理微電子工件的方法，更包含形成用於FET的源極與汲極區域。
  15. 如申請專利範圍第14項之用以處理微電子工件的方法，其中該等源極與汲極區域係形成作為磊晶成長區域。
  16. 如申請專利範圍第5項之用以處理微電子工件的方法，更包含取出該虛擬閘極，以露出包含該等矽層與該等矽鍺層的該等鰭層。
  17. 如申請專利範圍第16項之用以處理微電子工件的方法，其中該虛擬閘極為一矽虛擬閘極。
  18. 如申請專利範圍第16項之用以處理微電子工件的方法，更包含在取出該虛擬閘極之前，執行一平坦化製程。
  19. 如申請專利範圍第5項之用以處理微電子工件的方法，更包含執行露出之該等鰭層內之該等矽層的層移除蝕刻，以留下露出之矽鍺奈米線，該層移除蝕刻為矽相對於矽鍺的選擇性蝕刻。
  20. 如申請專利範圍第19項之用以處理微電子工件的方法，其中由於該內氧化物層所提供的保護作用，所以在該層移除蝕刻期間達到對於該氮化物層的目標侵蝕位準。
  21. 如申請專利範圍第19項之用以處理微電子工件的方法，其中用於該層移除蝕刻的一蝕刻化學品包含氮氧化物。
  22. 如申請專利範圍第19項之用以處理微電子工件的方法，更包含執行氧化物蝕刻，以移除該內氧化物層。
  23. 如申請專利範圍第19項之用以處理微電子工件的方法，更包含在露出之該等矽鍺奈米線之上形成一或多個附加的層。
  24. 如申請專利範圍第23項之用以處理微電子工件的方法，其中該一或多個附加的層包含一介電層或一金屬層之至少一者。
TW108125035A 2018-07-16 2019-07-16 微電子工件中矽鍺奈米線形成期間保護氮化物層的方法 TWI801628B (zh)

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