TWI801352B - 超低介電常數金屬間介電層的形成方法、積體電路的製造方法及半導體裝置 - Google Patents

超低介電常數金屬間介電層的形成方法、積體電路的製造方法及半導體裝置 Download PDF

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TWI801352B
TWI801352B TW106131396A TW106131396A TWI801352B TW I801352 B TWI801352 B TW I801352B TW 106131396 A TW106131396 A TW 106131396A TW 106131396 A TW106131396 A TW 106131396A TW I801352 B TWI801352 B TW I801352B
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dielectric
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ultra
dielectric layer
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TW201839903A (zh
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施伯錚
周家政
李俊德
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台灣積體電路製造股份有限公司
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Abstract

超低介電常數金屬間介電層的形成方法包含形成第一金屬間介電層於基底上，第一金屬間介電層包含複數個介電料材層，形成黏著層於第一金屬間介電層上，形成超低介電常數介電層於黏著層上，形成保護層於超低介電常數介電層上，形成硬遮罩於保護層上且將硬遮罩圖案化以產生窗口，移除窗口下的層以產生開口，被移除的層包含保護層、超低介電常數介電層、黏著層和第一金屬間介電層。在開口中形成金屬層。

Description

超低介電常數金屬間介電層的形成方法、積體電 路的製造方法及半導體裝置
本發明實施例係有關於半導體積體電路製造，特別有關於超低介電常數金屬間介電層的形成方法。
隨著電晶體製程技術的進步，電晶體的尺寸已經縮小，且積體電路的每單位面積的電晶體數量也因此增加。增加的裝置密度需要更進步的互連技術，且此互連技術能達成以期望的速度在裝置之間傳遞訊號並滿足低電阻和低電容(例如，低電阻電容(RC)時間常數)的需求。隨著積體電路變得更複雜且部件(feature)尺寸變小，也使得互連RC時間常數對訊號延遲的影響加劇。在半導體後段(back-end-of line，BEOL)製程中，用金屬間介電層製造金屬互連結構，其導致金屬互連結構產生電容。電容的產生造成不希望發生的半導體電路的訊號傳遞速度的降低。
使用低介電常數(low-k)介電材料形成金屬間介電層，在某種程度上已降低電容的產生且改善訊號傳遞速度。然而，低介電常數介電材料有不利的特性和性質，例如高孔隙 率，使其在某些半導體製造過程中容易受損，例如蝕刻、沉積和濕製程，而損害其介電常數(亦即，增加其介電常數)。
特別在先進技術中，例如5奈米節點(5-nanometer node，N5)或更先進的技術，亟需能達到期望的電容、良率和可靠度的解決方法。
根據一些實施例，提供超低介電常數(extra low-k，ELK)金屬間介電層(inter-layer metal dielectric layer，IMD)的形成方法。此方法包含形成第一金屬間介電層於基底上，第一金屬間介電層包含複數個介電材料層，形成黏著層於第一金屬間介電層上，形成超低介電常數介電層於黏著層上，形成保護層於超低介電常數介電層上，形成硬遮罩於保護層上，且將硬遮罩圖案化以產生窗口，移除窗口下方的層以產生開口，移除的層包含保護層、超低介電常數介電層、黏著層和第一金屬間介電層，以及在開口中形成金屬層。
根據另一些實施例，提供積體電路的製造方法。此方法包含形成複數個裝置於基底上，以產生製程中的基底；以及藉由產生後段製程(BEOL)金屬和介電層，對前述裝置實施傳導電力和訊號佈線(routing)互連，其中產生後段製程金屬和介電層包含形成金屬間介電層於製程中的基底上；形成超低介電常數介電層於金屬間介電層上；形成介電蓋於超低介電常數介電層上；形成包含氮化鈦(TiN)的硬遮罩於該介電蓋上，且將硬遮罩圖案化以產生窗口；移除窗口下的層以產生溝槽，被移除的層包含介電蓋、超低介電常數介電層和金屬間介電層； 以及形成包含銅(Cu)的金屬層於溝槽內。
根據又一些實施例，提供半導體裝置，其包含第一金屬間介電層形成於製程中的基底上；黏著層形成於第一金屬間介電層上，黏著層包含氧化矽或碳氧化矽；超低介電常數介電層形成於黏著層上，超低介電常數介電層包含摻雜碳且富含氧的氧化矽材料；保護層形成於超低介電常數介電層上；以及金屬層，從超低介電常數介電層延伸至第一金屬間介電層。
10:超低介電常數介電層的製造方法
S11、S12、S13、S14、S15、S16、S17:步驟
20、30、40、50、60、70、80:X-Z剖面視圖
22:基底
23:第一金屬間介電層
24:氮化鋁層
25:第一摻雜氧的碳化物層
26:氧化鋁層
27:第二摻雜氧的碳化物層
32:黏著層
42:超低介電常數介電層
52:保護層
54:硬遮罩
56:窗口
62:開口
72:金屬層
t1:厚度
為了讓本發明實施例的各個觀點能更明顯易懂，以下配合所附圖式作詳細說明。應該注意，根據工業中的標準範例，各個部件(features)未必按比例繪製。實際上，為了清楚的討論，各種部件的尺寸可以被任意增大或減小。
第1圖係根據本發明的一或更多實施例，描繪超低介電常數(extra low-k，ELK)介電層的製造方法之示範製程流程圖。
第2圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第3圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第4圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第5圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第6圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第7圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
第8圖係根據本發明的一或更多實施例，描繪超低介電常數介電層的製造方法中的一個階段。
以下揭露內容提供了許多用於實現在此所提供之本發明實施例的不同部件的不同實施例或範例。以下描述各部件及其排列方式的具體範例以簡化本發明實施例。當然，這些僅僅是範例，而不在於限制本發明實施例之保護範圍。例如，在以下描述中，在第二部件上方或其上形成第一部件，可以包含第一部件和第二部件以直接接觸的方式形成的實施例，並且也可以包含在第一部件和第二部件之間形成額外的部件，使得第一部件和第二部件可以不直接接觸的實施例。此外，本發明實施例可在各個範例中重複參考標號及/或字母。此重複是為了簡單和清楚的目的，其本身並非用於指定所討論的各個實施例及/或配置之間的關係。
再者，為了容易描述，在此可以使用例如“在...底下”、“在...下方”、“下”、“在...上方”、“上”等空間相關用語，以描述如圖所示的一個元件或部件與另一個(或另一些)元件或部件之間的關係。除了圖中所示的方位外，空間相關用語可涵蓋裝置在使用或操作中的不同方位。裝置可以採用其他方式定向(旋轉90度或在其他方位上)，並且在此使用的空間相關描述可以同樣地作出相應的解釋。
第1圖係根據本發明的一或更多實施例，描繪超低 介電常數介電層的製造方法10的示範製程流程圖。方法10說明整個製造製程的相關部分。可理解的是，可在第1圖所示的操作之前、期間和之後提供額外的操作，且可取代或移除下文所述的一些操作用於此方法的額外實施例。操作/製程的順序可互換。
在第1圖的步驟S11中，形成第一金屬間介電層23於基底22上，如第2圖的X-Z剖面視圖20所示。基底22可例如為晶圓，或者矽或鍺晶圓，或者是製程中的基底，其包含許多半導體裝置，如場效電晶體(field-effect transistor，FET)，場效電晶體包含形成於基礎基底上的金屬氧化物半導體場效電晶體(metal oxide semiconductor FET)或鰭式場效電晶體(Fin FET)。在一些實施例中，可藉由如本文中將更詳細討論的產生後段製程(back-end-of-line，BEOL)金屬和介電層，實施各種佈線(routing)互連，例如用於半導體裝置的傳導電力和訊號佈線互連。在一些實施例中，基礎基底可為P型矽基底，其雜質濃度的範圍從約1×1015cm-3到約3×1015cm-3。在另一些實施例中，基礎基底可為N型矽基底，其雜質濃度的範圍從約1×1015cm-3到約3×1015cm-3。在一些實施例中，矽基底的晶格方位為(100)。
另外，基礎基底可包含另一元素半導體，例如鍺；化合物半導體，其包含第四-四族(Group IV-IV)化合物半導體，例如碳化矽(SiC)和矽鍺(SiGe)，以及第三-五族(Group III-V)化合物半導體，例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或前述之組合。在一或更多實施例中，基礎基底為絕緣體上的矽 (silicon-on-insulator，SOI)基底之矽層。非晶形基底(amorphous substrate)，例如非晶形矽或非晶形碳化矽(SiC)，或者絕緣材料，例如氧化矽，也可用來作為基礎基底。基礎基底可包含各種已經以雜質進行適合摻雜(例：P型或N型導電性)的區域。
在一些實施例中，第一金屬間介電層23包含複數個層，例如：氮化鋁層24、第一摻雜氧的碳化物(oxygen doped carbide，ODC)層25(例：摻雜氧的碳化矽)、氧化鋁(Al2O3)層26以及第二摻雜氧的碳化物層27，如第2圖的X-Z剖面視圖20所示。在一些實施例中，可使用電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)或物理氣相沉積(physical vapor deposition，PVD)製程，形成厚度在約3nm至約5nm的範圍內的氮化鋁層24。為人所熟知的是，氮化鋁具有許多優點，其包含均勻的微結構、高導熱性、高電阻和直到約980℃的化學安定性。在一些實施例中，可使用電漿增強化學氣相沉積或物理氣相沉積製程，沉積第一摻雜氧的碳化物層25和第二摻雜氧的碳化物層27。第一摻雜氧的碳化物層25的厚度和第二摻雜氧的碳化物層27的厚度可在約3nm至約5nm的範圍內。在一些實施例中，氧化鋁(Al2O3)層26的厚度可在約3nm至約5nm的範圍內，且可使用電漿增強化學氣相沉積或物理氣相沉積製程沉積。在一些實施例中，可使用其它沉積製程，且第一金屬間介電層23的各層可為具有不同厚度的不同介電材料。第一金屬間介電層23的堆疊結構不限於上述的配置。第一金屬間介電層23可為單層介電層，或者可為分別由任何合適的介電材料組成的多層介電層。
在第1圖的步驟S12中，藉由使用電漿增強化學氣相沉積或物理氣相沉積製程，在第一金屬間介電層23上形成黏著層32，如第3圖的X-Z剖面視圖30所示。在一些實施例中，黏著層為氧化物層或碳化物層，但不限於這些化合物，且黏著層可增強下一層對第一金屬間介電層23的黏著力。雖然也可使用其它材料或化合物，但在一些實施例中，氧化物層可為氧化矽(SiO2)，且碳化物層可為碳氧化矽(SiOC)。
在第1圖的步驟S13中，在黏著層32上形成超低介電常數介電層42，如第4圖的X-Z剖面視圖40所示。在一些實施例中，超低介電常數介電層42為摻雜碳且富含氧的氧化矽材料緻密層。在一些實施例中，可在電漿增強化學氣相沉積或物理氣相沉積製程中使用低流速的前驅物來沉積超低介電常數介電層42。在一些實施例中，前驅物可為甲基二乙氧基甲基矽烷(methyl-diethoxymethylsilane，mDEOS)。在一些實施例中，低流速是小於約900標準立方公分每分鐘(standard cubic centimeters per minute，sccm)的流速。
在一些實施例中，藉由在電漿增強化學氣相沉積或物理氣相沉積製程中，使用低的前驅物與載體氣體的流速比值，形成超低介電常數介電層42。在一些實施例中，載體氣體可為氦(He)，且低的前驅物與載體氣體的流速比值小於約0.4。在其它實施例中，可使用其它載體氣體和不同的前驅物與載體氣體的流速比值。在一些實施例中，超低介電常數介電層42具有小於約3.4的介電常數。在一些實施例中，超低介電常數介電層42的厚度t1可在約20nm至約100nm的範圍內。在一些實施 例中，超低介電常數介電層42的摻雜碳且富含氧的氧化矽材料緻密層的碳含量在約5至約30原子百分比的範圍內，其氧含量在約40至約55原子百分比的範圍內，且其矽含量在約30至約40原子百分比的範圍內。超低介電常數介電層42比傳統低介電常數材料更緻密，且可具有約3至約10GPa範圍內的硬度。
相較於傳統低介電常數材料，本發明實施例的超低介電常數介電層具有許多優點。例如，本發明實施例的超低介電常數介電層可以改善金屬互連線的耦合電容(例如改善超過1至1.5%)，這樣可以相應地使得半導體裝置的速度更快。再者，超低介電常數介電層42比傳統低介電常數材料更可靠，且較不易受到損傷。
在第1圖的步驟S14中，在超低介電常數介電層42上形成保護層52，如第5圖的X-Z剖面視圖50所示。在一些實施例中，保護層52係由無氮抗反射層(nitrogen-free antireflection layer，NFARL)製成的介電蓋。無氮抗反射層係用來將來自光阻層底下的層之光的總反射最小化，且用來形成光阻層和其下方層之間的界面。在化學氣相沉積(選擇性地為電漿增強)製程中，使用碳、矽和氧來源的氣體混合物，可以製造出無氮抗反射層。在一些實施例中，可調整製程參數以獲得可接受的折射率n和消光係數k之數值。無氮抗反射層可消除在許多抗反射層中發現的迅速增長(mushrooming)和基腳(footing)問題。
在一些實施例中，保護層52包含以四乙氧基矽烷(tetraethoxysilane，TEOS)為基礎的層，在矽烷氧聚合物(silicone polymer)中，這樣的層已知常作為交聯劑，且在半導 體產業中，這樣的層已知常作為二氧化矽的前驅物。雖然可使用其他沉積法，但在一些實施例中，藉由旋塗式玻璃(spin-on-glass)沉積法可沉積以四乙氧基矽烷為基礎的層。在一些實施例中，保護層52包含介電材料，例如：摻雜氧的碳化物、氮化矽、氮氧化矽、碳化矽、其它合適的材料和/或前述之組合。在一些實施例中，保護層52包含無氮抗反射層，其包含一氧化矽(SiO)。在另一些實施例中，保護層52包含碳氧化矽(SiOC)。在保護層包含碳氧化矽的那些實施例中，保護層具有重量百分比為約20至約45%的碳、重量百分比為約0至約20%的氧和/或重量百分比為約30%至約50%的矽。在一些實施例中，保護層52包含BC、BN、SiBN、SiBC、SiBCN和/或其它包含硼的材料。在那些實施例中，保護層具有重量百分比為約5%至約100%的硼。
在第1圖的步驟S15中，在保護層52上形成硬遮罩54，且將硬遮罩54圖案化，如第5圖的X-Z剖面視圖50所示。雖然可使用其它硬遮罩材料，在一些實施例中，硬遮罩包含氮化鈦(TiN)。在一些實施例中，可使用化學氣相沉積或物理氣相沉積法，沉積氮化鈦的硬遮罩54。可將硬遮罩54圖案化，為接下來的蝕刻製程打開窗口56。
在第1圖的步驟S16中，移除窗口56下方的層，以產生開口62，如第6圖的X-Z剖面視圖60所示。窗口56下方的層為保護層52、超低介電常數介電層42、黏著層32和第一金屬間介電層23。
雖然可使用其它蝕刻製程，在一些實施例中，可 使用一或更多蝕刻操作，包含例如電漿蝕刻製程，以產生開口(或稱溝槽)62。
在第1圖的步驟S17中，在開口62中形成金屬層72，如第7圖的X-Z剖面視圖70所示。金屬層72可為鋁(Al)或銅(Cu)。在一些實施例中，金屬層72可為後段製程(back-end-of-line，BEOL)的金屬互連。在一些實施例中，金屬層72為耦接兩個或更多金屬層的導孔(via)結構(為了簡潔，未繪示於第7圖中)。在一些實施例中，可使用氣相沉積(vapor phase deposition,VPD)製程，例如電子束氣相沉積(electron beam VPD，EBVPD)製程、物理氣相沉積、化學氣相沉積或電鍍，以沉積金屬層72。在另一些實施例中，可使用其它沉積方法形成金屬層72。
在一些實施例中，在沉積金屬層72之後，可使用平坦化製程，例如化學機械平坦化(chemical mechanical planarization，CMP)，以移除保護層52和硬遮罩層54，如第8圖的X-Z剖面視圖80所示。
可以理解的是，並非全部的優點都必需在本文中討論，沒有一個特定的優點是全部的實施例或示範例都必要的，並且其它實施例或示範例可提供不同的優點。
根據本發明實施例的一方面，超低介電常數金屬間介電層的製造方法包含形成第一金屬間介電層於基底上，第一金屬間介電層包含複數個介電材料層，形成黏著層於第一金屬間介電層上，形成超低介電常數介電層於黏著層上，形成保護層於超低介電常數介電層上，形成硬遮罩於保護層上，且將硬遮罩圖案化以產生窗口，移除窗口下方的層以產生開口，移 除的層包含保護層、超低介電常數介電層、黏著層和第一金屬間介電層，在開口中形成金屬層。此方法可更包含實施平坦化製程，例如使用化學機械平坦化。
在一些實施例中，上述那些介電材料層包含氮化鋁(AlN)層、第一摻雜氧的碳化物(ODC)層、氧化鋁(Al2O3)層和第二摻雜氧的碳化物(ODC)層。在一些實施例中，超低介電常數介電層為摻雜碳且富含氧的氧化矽材料。在一些實施例中，在電漿增強化學氣相沉積或物理氣相沉積製程中，使用低流速的前驅物形成超低介電常數介電層。在一些實施例中，前驅物可包含甲基二乙氧基甲基矽烷(methyl-diethoxymethylsilane，mDEOS)，且低流速是小於約900標準立方公分每分鐘(standard cubic centimeters per minute，sccm)的流速。在另一些實施例中，低流速是小於約600標準立方公分每分鐘的流速。
在一些實施例中，在電漿增強化學氣相沉積或物理氣相沉積製程中，可藉由使用低的前驅物與載體氣體的流速比值，形成超低介電常數介電層。在一些實施例中，載體氣體可為氦(He)，且低的前驅物與載體氣體的流速比值小於約0.4。在另一些實施例中，載體氣體可為氦(He)，且低的前驅物與載體氣體的流速比值小於約0.2。在一些實施例中，黏著層為氧化物層或碳化物層。在一些實施例中，氧化物層為氧化矽(SiO2)。在一些實施例中，碳化物層為碳氧化矽(SiOC)。
在一些實施例中，保護層為包含無氮抗反射層(nitrogen-free antireflection layer，NFARL)的介電蓋材料。在另一些實施例中，保護層可為包含四乙氧基矽烷 (tetraethoxysilane，TEOS)的介電蓋材料。在一些實施例中，硬遮罩可為氮化鈦(TiN)。
在一些實施例中，金屬層為後段製程(back-end-of-line，BEOL)的金屬互連線。在一些實施例中，金屬層可為銅(Cu)。在一些實施例中，基底為晶圓，此晶圓包含矽晶圓，且此晶圓可包含電子電路。
根據本發明實施例的另一方面，積體電路的製造方法包含形成複數個裝置於基底上，以產生製程中的基底，可藉由產生後段製程金屬和介電層，對前述裝置實施傳導電力和訊號佈線互連，後段製程金屬和介電層的產生包含形成金屬間介電層於製程中的基底上，及形成超低介電常數介電層於金屬間介電層上，形成介電蓋於超低介電常數介電層上，形成包含氮化鈦(TiN)的硬遮罩於介電蓋上，及將硬遮罩圖案化以產生窗口，移除窗口下的層以產生溝槽，移除的層包含介電蓋、超低介電常數介電層和金屬間介電層，在溝槽中形成包含銅(Cu)的金屬層。
在一些實施例中，金屬間介電層包含複數個介電材料層，這些介電材料層包含氮化鋁(AlN)層、第一摻雜氧的碳化物(ODC)層、氧化鋁(Al2O3)層和第二摻雜氧的碳化物(ODC)層。在一些實施例中，超低介電常數介電層包含摻雜碳且富含氧的氧化矽材料，藉由使用電漿增強化學氣相沉積或物理氣相沉積製程，形成摻雜碳且富含氧的氧化矽材料。在一些實施例中，使用低流速的前驅物形成超低介電常數介電層，前驅物包含甲基二乙氧基甲基矽烷(mDEOS)。在一些實施例中，低流速 是小於約900標準立方公分每分鐘的流速。
在一些實施例中，在電漿增強化學氣相沉積或物理氣相沉積製程中，使用低的前驅物與氦(He)載體氣體的流速比值來形成超低介電常數介電層。在一些實施例中，低的前驅物與載體氣體的流速比值小於約0.4。在另一些實施例中，低的前驅物與載體氣體的流速比值小於約0.2。
在一些實施例中，在形成超低介電常數介電層之前，此方法更包含在金屬間介電層上形成黏著層。在一些實施例中，黏著層包含氧化矽(SiO2)或碳氧化矽(SiOC)。在一些實施例中，介電蓋包含無氮抗反射層。在另一些實施例中，介電蓋包含四乙氧基矽烷(tetraethoxysilane，TEOS)。
根據本發明實施例的又另一方面，積體電路包含在基底上實施複數個裝置，以產生製程中的基底，配置後段製程金屬和介電層以提供用於前述這些裝置的傳導電力和訊號佈線互連，後段製程金屬和介電層包含形成於製程中的基底上的第一金屬間介電層，第一金屬間介電層包含複數個介電材料層，包含氧化矽(SiO2)或碳氧化矽(SiOC)的黏著層形成在第一金屬間介電層上，包含摻雜碳且富含氧的氧化矽材料的超低介電常數介電層形成在黏著層上，保護層形成在超低介電常數介電層上。金屬層形成在保護層、超低介電常數介電層、黏著層和第一金屬間介電層的開口中，且金屬層從超低介電常數介電層延伸至第一金屬間介電層。
以上概述了數個實施例的部件，使得在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的 各方面。在本發明所屬技術領域中具有通常知識者應該理解，他們可以容易地使用本發明實施例作為基礎，來設計或修改用於實施與在此所介紹實施例具有相同的目的及/或達到相同優點的其他製程和結構。在本發明所屬技術領域中具有通常知識者也應該理解，這些等效的構造並不背離本發明的精神和範圍，並且在不背離本發明的精神和範圍的情況下，在此可以做出各種改變、取代或其他選擇。
10:超低介電常數介電層的製造方法
S11、S12、S13、S14、S15、S16、S17:步驟

Claims (9)

  1. 一種超低介電常數金屬間介電層的形成方法，包括：形成一第一金屬間介電層於一基底上，該第一金屬間介電層包括於該基底上的氮化鋁層、於該氮化鋁層上的一第一摻雜氧的碳化物層、於該第一摻雜氧的碳化物層上的氧化鋁層及於該氧化鋁層上的一第二摻雜氧的碳化物層；形成一黏著層於該第一金屬間介電層上；形成一超低介電常數介電層於該黏著層上；形成一保護層於該超低介電常數介電層上；形成一硬遮罩於該保護層上，且將該硬遮罩圖案化以產生一窗口；移除該窗口下的層以產生一開口，其中該被移除的層包含該保護層、該超低介電常數介電層、該黏著層及該第一金屬間介電層；以及形成一金屬層於該開口內。
  2. 如請求項1的超低介電常數金屬間介電層的形成方法，其中該超低介電常數介電層的形成，包括在一電漿增強化學氣相沉積或一物理氣相沉積製程中，使用低流速的一前驅物，其中該前驅物包括甲基二乙氧基甲基矽烷，且該低流速是小於約900標準立方公分每分鐘的流速。
  3. 如請求項1或2的超低介電常數金屬間介電層的形成方法，其中該保護層包括一介電蓋材料，該介電蓋材料包括無氮抗反射層或四乙氧基矽烷，該介電蓋材料包括四乙氧基矽烷時，該硬遮罩包括氮化鈦。
  4. 一種積體電路的製造方法，包括：形成複數個裝置於一基底上，以產生一製程中的基底；以及藉由產生後段製程金屬和複數個介電層，對上述複數個裝置實施傳導電力和訊號佈線互連，該後段製程金屬和該些介電層的產生是藉由：形成一金屬間介電層於該製程中的基底上，該金屬間介電層包括於該製程中的基底上的氮化鋁層、於該氮化鋁層上的一第一摻雜氧的碳化物層、於該第一摻雜氧的碳化物層上的氧化鋁層及於該氧化鋁層上的一第二摻雜氧的碳化物層；形成一超低介電常數介電層於該金屬間介電層上；形成一介電蓋於該超低介電常數介電層上；形成一硬遮罩於該介電蓋上，及將該硬遮罩圖案化以產生一窗口，該該硬遮罩包含氮化鈦；移除該窗口下的複數個層以產生一溝槽，上述移除的層包含該介電蓋、該超低介電常數介電層和該金屬間介電層；以及在該溝槽中形成包含銅的一金屬層。
  5. 如請求項4的積體電路的製造方法，其中該超低介電常數介電層包含摻雜碳且富含氧的氧化矽材料，藉由使用一電漿增強化學氣相沉積或一物理氣相沉積製程，形成該摻雜碳且富含氧的氧化矽材料。
  6. 如請求項5的積體電路的製造方法，其中形成該超低介電常 數介電層包括使用一低流速的前驅物，該低流速的前驅物包含甲基二乙氧基甲基矽烷，其中該低流速小於約900標準立方公分每分鐘。
  7. 如請求項4的積體電路的製造方法，其中形成該超低介電常數介電層包括在一電漿增強化學氣相沉積或一物理氣相沉積製程中，使用一低的前驅物與氦氣的流速比值，其中該低的前驅物與氦氣的流速比值小於約0.2。
  8. 如請求項4的積體電路的製造方法，更包括在形成該超低介電常數介電層之前，在該金屬間介電層上形成一黏著層，其中該黏著層包括氧化矽或碳氧化矽。
  9. 一種半導體裝置，包括：一第一金屬間介電層，形成在一製程中的基底上，該第一金屬間介電層包括於該製程中的基底上的氮化鋁層、於該氮化鋁層上的一第一摻雜氧的碳化物層、於該第一摻雜氧的碳化物層上的氧化鋁層及於該氧化鋁層上的一第二摻雜氧的碳化物層；一黏著層，形成在該第一金屬間介電層上，該黏著層包含氧化矽或碳氧化矽；一超低介電常數介電層，形成在黏著層上，該超低介電常數介電層包含摻雜碳且富含氧的氧化矽材料；一保護層，形成在該超低介電常數介電層上；以及一金屬層，從該超低介電常數介電層延伸至該第一金屬間介電層。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
US10707165B2 (en) * 2017-04-20 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having an extra low-k dielectric layer and method of forming the same
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050042889A1 (en) * 2001-12-14 2005-02-24 Albert Lee Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US20080254641A1 (en) * 2004-01-13 2008-10-16 Tokyo Electron Limited Manufacturing Method Of Semiconductor Device And Film Deposition System
TW201230192A (en) * 2010-11-12 2012-07-16 Applied Materials Inc Process for lowering adhesion layer thickness and improving damage resistance for thin ultra low-k dielectric film
TW201616568A (zh) * 2014-10-17 2016-05-01 台灣積體電路製造股份有限公司 積體電路中的蝕刻停止層
TW201705364A (zh) * 2015-07-17 2017-02-01 台灣積體電路製造股份有限公司 形成半導體裝置結構的方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759740B2 (en) * 2001-03-30 2004-07-06 Kyocera Corporation Composite ceramic board, method of producing the same, optical/electronic-mounted circuit substrate using said board, and mounted board equipped with said circuit substrate
US20030134499A1 (en) 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
JP2004281535A (ja) 2003-03-13 2004-10-07 Fujitsu Ltd 被膜形成材料、絶縁膜の製造方法及び半導体装置
US20070063188A1 (en) 2003-04-11 2007-03-22 Rantala Juha T Low-k dielectric material
WO2004105123A1 (ja) * 2003-05-21 2004-12-02 Fujitsu Limited 半導体装置
US6841466B1 (en) * 2003-09-26 2005-01-11 Taiwan Semiconductor Manufacturing Company Method of selectively making copper using plating technology
US7015133B2 (en) * 2004-04-14 2006-03-21 Taiwan Semiconductor Manufacturing Company Dual damascene structure formed of low-k dielectric materials
CN100403495C (zh) * 2004-08-30 2008-07-16 联华电子股份有限公司 半导体制造方法及其结构
US8043959B2 (en) 2006-04-21 2011-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity
WO2011106218A2 (en) 2010-02-25 2011-09-01 Applied Materials, Inc. Ultra low dielectric materials using hybrid precursors containing silicon with organic functional groups by plasma-enhanced chemical vapor deposition
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US8987139B2 (en) 2013-01-29 2015-03-24 Applied Materials, Inc. Method of patterning a low-k dielectric film
CN104347476B (zh) * 2013-07-23 2018-06-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US10170396B2 (en) 2014-02-14 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure extending to metallization layer
KR101665784B1 (ko) 2014-05-23 2016-10-12 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 금속의 접촉 저항을 감소시키기 위한 장치 및 방법
US9536964B2 (en) 2015-05-29 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming via profile of interconnect structure of semiconductor device structure
US9768061B1 (en) * 2016-05-31 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k dielectric interconnect systems
US10181420B2 (en) * 2017-02-06 2019-01-15 Globalfoundries Inc. Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias
US10707165B2 (en) * 2017-04-20 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having an extra low-k dielectric layer and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050042889A1 (en) * 2001-12-14 2005-02-24 Albert Lee Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US20080254641A1 (en) * 2004-01-13 2008-10-16 Tokyo Electron Limited Manufacturing Method Of Semiconductor Device And Film Deposition System
TW201230192A (en) * 2010-11-12 2012-07-16 Applied Materials Inc Process for lowering adhesion layer thickness and improving damage resistance for thin ultra low-k dielectric film
TW201616568A (zh) * 2014-10-17 2016-05-01 台灣積體電路製造股份有限公司 積體電路中的蝕刻停止層
TW201705364A (zh) * 2015-07-17 2017-02-01 台灣積體電路製造股份有限公司 形成半導體裝置結構的方法

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