TWI799102B - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer and an insulating material layer. The build-up circuit structure is disposed on the substrate and includes at least one inner circuit, at least one dielectric layer, outer circuit and a plurality of conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The plurality of conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at intervals. The graphene oxide layer is disposed corresponding to the dielectric layer, and the graphene layer is disposed corresponding to the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, and the opening exposes the graphene layer.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and its manufacturing method, and in particular to a circuit board and its manufacturing method which can improve the problem of heterogeneous adhesion.

Most of the existing surface binders are used to enhance the binding force between organic and metal interfaces, but there is no surface binder that can be used both between organic and metal interfaces and between organic and organic interfaces. For example, due to the insufficient bonding force between the solder resist dielectric material (such as solder resist ink) and the outer circuit interface, when using electroless plating for surface treatment processes (such as electroless nickel palladium immersion gold (ENEPIG)) , It is often found that there is plating and discoloration on the bottom sidewall of the opening of the solder mask dielectric material.

In addition, although the surface roughness of the outer layer circuit can be increased by roughening the surface of the outer layer circuit to increase the bonding force between the solder resist dielectric material and the interface of the outer layer circuit, however, the outer layer circuit after surface roughening It will affect signal transmission and even cause signal loss.

The invention provides a circuit board and a manufacturing method thereof, which can improve the problem of poor bonding of heterogeneous materials, or improve reliability and yield.

The circuit board of the present invention includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer and an insulating material layer. The build-up circuit structure is disposed on the substrate. The build-up wiring structure includes at least one inner wiring, at least one dielectric layer, outer wiring and a plurality of conductive holes. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive hole penetrates the dielectric layer and electrically connects the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are spaced apart on the build-up circuit structure. The graphene oxide layer is arranged corresponding to the dielectric layer, and the graphene layer is arranged corresponding to the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, and the opening exposes the graphene layer.

In an embodiment of the present invention, the material of the above-mentioned dielectric layer is different from that of the insulating material layer.

In an embodiment of the present invention, the insulating material layer is another dielectric layer or a solder resist layer.

In an embodiment of the present invention, in the normal direction of the above-mentioned build-up wiring structure, the graphene oxide layer overlaps the dielectric layer, and the graphene layer overlaps the outer wiring.

In an embodiment of the present invention, the above-mentioned graphene oxide layer is in contact with the dielectric layer, and the graphene layer is in contact with the outer circuit.

In an embodiment of the present invention, the above-mentioned circuit board further includes a conductive material layer. The conductive material layer is disposed in the opening. The conductive material layer is electrically connected to the build-up circuit structure through the graphene layer.

In an embodiment of the present invention, the graphene oxide layer is located at the interface between the insulating material layer and the dielectric layer, and is located at the interface between the insulating material layer and the outer circuit.

The manufacturing method of the circuit board of the present invention includes the following steps. First, a substrate is provided. Next, a build-up circuit structure is formed on the substrate. Wherein, the build-up circuit structure includes at least one inner layer circuit, at least one dielectric layer, outer layer circuit and a plurality of conductive holes. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. A plurality of conductive holes penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. Next, a graphene oxide layer is formed on the build-up circuit structure. Next, an insulating material layer is formed on the graphene oxide layer. Wherein, the insulating material layer has an opening, and the opening exposes a part of the graphene oxide layer. Then, part of the graphene oxide layer is reduced to a graphene layer. Wherein, the graphene layer is arranged corresponding to the outer circuit, and another part of the graphene oxide layer is arranged corresponding to the dielectric layer.

In an embodiment of the present invention, the above manufacturing method further includes the following step: forming a conductive material layer in the opening. Wherein, the conductive material layer can be electrically connected to the build-up circuit structure through the graphene layer.

In an embodiment of the present invention, the method for reducing a portion of the graphene oxide layer to a graphene layer includes: treating the portion of the graphene oxide layer with a plasma or steam method.

Based on the above, in the circuit board and its manufacturing method according to an embodiment of the present invention, by disposing the graphene oxide layer between the insulating material layer and the build-up circuit structure, it can be used to improve the insulating material layer and the build-up circuit structure There is a problem of poor bonding between heterogeneous materials (that is, improving the bonding force between the insulating material layer and the build-up circuit structure), thereby improving the reliability and yield of the circuit board. In addition, with the arrangement of graphene, the conductive material layer can be electrically connected to the build-up circuit structure, which can improve the heat dissipation effect of the circuit board and protect the outer circuit from oxidation.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1A to FIG. 1G are schematic cross-sectional views of a manufacturing method of a circuit board according to an embodiment of the present invention. Wherein, the manufacturing method of the circuit board 100 of this embodiment may include but not limited to the following steps:

First, referring to FIG. 1A , a substrate 110 is provided, and a release layer 120 and a seed layer 130 are sequentially formed on the substrate 110 . Wherein, the material of the substrate 110 may include glass or other supporting substrate materials, but not limited thereto. The release layer 120 may be removed in subsequent steps as needed. The seed layer 130 may be a single layer or a multi-layer metal layer. In this embodiment, the seed layer 130 may include a titanium layer and a copper layer on the titanium layer.

Next, referring to FIG. 1B , a build-up wiring structure 140 is formed on the substrate 110 . The build-up wiring structure 140 includes at least one inner layer wiring 141 (FIG. 1B schematically takes 1 layer as an example, but not limited thereto), at least one dielectric layer 142 (FIG. 1B schematically takes 1 layer as an example, but not limited thereto). This limit), the outer circuit 143 and a plurality of conductive holes 144 . Wherein, the inner circuit 141 is disposed on the seed layer 130 and contacts the seed layer 130 . The dielectric layer 142 is disposed on the inner wiring 141 to cover the inner wiring 141 and the portion of the seed layer 130 exposed by the inner wiring 141 . The outer circuit 143 is disposed on the dielectric layer 142 and has a plurality of pads 1431 . The conductive hole 144 penetrates through the dielectric layer 142 to electrically connect the inner circuit 141 and the outer circuit 143 . In this embodiment, the material of the dielectric layer 142 can be, for example, a photosensitive dielectric material (Photoimageable dielectric, PID) or other suitable organic materials with low dielectric constant and low roughness, so as to achieve high frequency and high speed requirements, but not limited thereto. The inner circuit 141 and the outer circuit 143 can be thin circuits, and the material of the inner circuit 141 and the outer circuit 143 can be, for example, copper or other suitable metals, but not limited thereto.

Next, please refer to FIG. 1C , a graphene oxide layer 150 is conformally formed on the build-up wiring structure 140 to cover the outer wiring 143 and the portion of the dielectric layer 142 exposed by the outer wiring 143 . In this embodiment, the method for forming the graphene oxide layer 150 on the build-up circuit structure 140 may, for example, include the following steps: firstly, the liquid-phase graphene oxide is coated on the build-up circuit structure 140, and then, performing drying to form the graphene oxide layer 150 .

Wherein, the thickness of the graphene oxide layer 150 may be, for example, 0.5 nanometers (nm) to 500 nanometers, but not limited thereto. The material of the graphene oxide layer 150 is graphene oxide (Graphene oxide, GO) having insulating properties.

Next, referring to FIG. 1D , an insulating material layer 160 is formed on the graphene oxide layer 150 so that the insulating material layer 160 and the build-up circuit structure 140 are located on opposite sides of the graphene oxide layer 150 . Wherein, the insulating material layer 160 has an opening 161 . The opening 161 may expose a portion 151 of the graphene oxide layer 150 , and the insulating material layer 160 may cover another portion 152 of the graphene oxide layer 150 . In this embodiment, the material of the insulating material layer 160 is different from the material of the dielectric layer 142 . The insulating material layer 160 can be another dielectric layer and the material of the insulating material layer 160 can be, for example, Ajinomoto build-up film (ABF) or other suitable organic materials, but not limited thereto.

In this embodiment, since the carbonyl group (Carbonyl group), epoxy group (Epoxy group) and hydroxyl group (Hydroxy group) on the surface of graphene oxide can be combined with metal (such as the copper of the outer layer circuit 143) and organic materials (such as The photosensitive dielectric material of the dielectric layer 142 is bonded to the Ajinomoto build-up film) of the insulating material layer 160 and produces a bonding force, so that the graphite oxide disposed between the insulating material layer 160 and the build-up circuit structure 140 can be The alkene layer 150 is used as an adhesive to improve the problem of heterogeneous bonding between the insulating material layer 160 and the dielectric layer 142 and between the insulating material layer 160 and the outer circuit 143, thereby improving the reliability of the wiring board 100. reliability and yield. In addition, graphene oxide also has better ductility, and graphene oxide in liquid phase is also conducive to large-area coating.

Next, referring to FIG. 1E , the portion 151 of the graphene oxide layer 150 is reduced to a graphene layer 155 . Specifically, in this embodiment, for example, the portion 151 of the graphene oxide layer 150 is treated with hydrogen plasma (H ₂ Plasma) or water steaming (Solvothermal), so that the oxidation in the portion 151 The graphene is reduced to graphene, and the portion 151 is reduced to a graphene layer 155 . Wherein, the steaming method is, for example, treating with steam at 100° C. for at least 20 minutes. In this embodiment, since the thermal conductivity of graphene can be, for example, about 5,300 W/m·K and the resistivity can be, for example, about 10 ⁻⁶ Ω·cm, the graphene layer 155 can have excellent thermal conductivity and electrical conductivity sex. In addition, since the thermal conductivity of graphene is better than that of copper, the heat dissipation effect of the circuit board 100 can also be improved.

In this embodiment, the graphene oxide layer 150 and the graphene layer 155 are arranged at intervals. The graphene layer 155 can be disposed corresponding to the pad 1431 of the outer circuit 143 , and another portion 152 of the graphene oxide layer 150 can be disposed corresponding to the dielectric layer 142 . That is to say, another part 152 of the graphene oxide layer 150 may be located at the interface between the insulating material layer 160 and the dielectric layer 142 , and located at the interface between the insulating material layer 160 and the outer circuit 143 . In addition, in this embodiment, in the normal direction Z of the build-up circuit structure 140 , the graphene oxide layer 150 can overlap the dielectric layer 142 , and the graphene layer 155 can overlap the pad 1431 of the outer layer circuit 143 . In some embodiments, the graphene oxide layer 150 can contact the dielectric layer 142 , and the graphene layer 155 can contact the pad 1431 of the outer circuit 143 .

Next, referring to FIG. 1F , a conductive material layer 170 is formed in the opening 161 , and an inner circuit 181 is formed on the insulating material layer 160 so that the inner circuit 181 can contact the conductive material layer 170 . Wherein, the conductive material layer 170 can fill the opening 161 , can contact the graphene layer 155 , and can be electrically connected to the build-up circuit structure 140 through the graphene layer 155 . In this embodiment, the material of the conductive material layer 170 may be, for example, copper or other suitable conductive materials, but is not limited thereto.

Next, referring to FIG. 1G , a build-up circuit structure 180 is formed on the insulating material layer 160 . The build-up wiring structure 180 includes at least one inner layer wiring 181 (Figure 1G schematically takes 1 layer as an example, but not limited thereto), at least one dielectric layer 182 (Figure 1G schematically takes 1 layer as an example, but not limited to This limit), the outer circuit 183 and a plurality of conductive holes 184 . Wherein, the dielectric layer 182 is disposed on the inner circuit 181 to cover the inner circuit 181 and the insulating material layer 160 exposed by the inner circuit 181 . The outer circuit 183 is disposed on the dielectric layer 182 . The conductive hole 184 penetrates the dielectric layer 182 to electrically connect the inner circuit 181 and the outer circuit 183 . In this embodiment, the material of the dielectric layer 182 may be the same as that of the insulating material layer 160 , so details are not repeated here. So far, the circuit board 100 of this embodiment has been substantially completed.

In short, the circuit board 100 of this embodiment may include a substrate 110 , a build-up circuit structure 140 , a graphene oxide layer 150 , a graphene layer 155 and an insulating material layer 160 . The build-up wiring structure 140 is disposed on the substrate 110 . The build-up wiring structure 140 includes at least one inner wiring 141 , at least one dielectric layer 142 , outer wiring 143 and a plurality of conductive vias 144 . The dielectric layer 142 is disposed on the inner circuit 141 . The outer circuit 143 is disposed on the dielectric layer 142 . The conductive hole 144 penetrates through the dielectric layer 142 and electrically connects the inner circuit 141 and the outer circuit 143 . The graphene oxide layer 150 and the graphene layer 155 are spaced apart on the build-up circuit structure 140 . The graphene oxide layer 150 is disposed corresponding to the dielectric layer 142 , and the graphene layer 155 is disposed corresponding to the outer circuit 143 . The insulating material layer 160 is disposed on the graphene oxide layer 150 and the graphene layer 155 . The insulating material layer 160 has an opening 161 , and the opening 161 exposes the graphene layer 155 .

2A to 2D are schematic cross-sectional views of a method for manufacturing a circuit board according to another embodiment of the present invention. Wherein, the manufacturing method of the circuit board 200 of this embodiment may include but not limited to the following steps:

First, please refer to FIG. 2A , a substrate 210 is provided, and a build-up circuit structure 240 is formed on the substrate 210 . Wherein, the substrate 210 has a via hole 211 for electrically connecting to the build-up wiring structure 240 . In this embodiment, the material of the substrate 210 may include Ajinomoto build-up film (ABF), prepreg (Prepreg) such as epoxy glass with flame retardant and self-extinguishing properties (FR-4). Epoxy glass cloth or BT resin (Bismaleimide triazine resin), or photosensitive dielectric material, such as benzocyclobutene (Benzocylobutene, BCB), bismaleimide/triazine trap (Bismaleimide Triazine, BT), liquid crystal polymer, polyimide (Poly-imide, PI), polyvinyl ether, polytetrafluoroethylene (Poly (phenylene ether)), aromatic nylon (Aramide), epoxy resin (Epoxy ) and glass fibers and their compositions, but not limited thereto.

The build-up wiring structure 240 includes at least one inner layer wiring 241 (FIG. 2A schematically takes 2 layers as an example, but not limited thereto), at least one dielectric layer 242 (FIG. 2A schematically takes 2 layers as an example, but not limited thereto). This limit), the outer circuit 243 and a plurality of conductive holes 244 . Wherein, the inner circuit 241 is disposed on the substrate 210 and contacts the substrate 210 . The dielectric layer 242 is disposed on the inner circuit 241 to cover the inner circuit 241 and the portion of the substrate 210 exposed by the inner circuit 241 . The outer circuit 243 is disposed on the dielectric layer 242 and has a plurality of pads 2431 . The conductive hole 244 penetrates through the dielectric layer 242 to electrically connect the inner circuit 241 and the outer circuit 243 . In this embodiment, the material of the dielectric layer 242 can be, for example, Ajinomoto build-up film, prepreg, photosensitive dielectric material, epoxy resin/filler/glass fiber composite material, but not limited thereto. The material of the inner circuit 241 and the outer circuit 243 can be, for example, copper or other suitable metals, but is not limited thereto.

Next, please refer to FIG. 2B , a graphene oxide layer 250 is conformally formed on the build-up wiring structure 240 to cover the outer wiring 243 and the portion of the dielectric layer 242 exposed by the outer wiring 243 . Wherein, the thickness of the graphene oxide layer 250 may be, for example, 0.5 nm to 500 nm, but not limited thereto. The material of the graphene oxide layer 250 is graphene oxide with insulating properties.

Next, referring to FIG. 2C , an insulating material layer 260 is formed on the graphene oxide layer 250 so that the insulating material layer 260 and the build-up circuit structure 240 are respectively located on opposite sides of the graphene oxide layer 250 . Wherein, the insulating material layer 260 has an opening 261 . The opening 261 may expose a portion 251 of the graphene oxide layer 250 , and the insulating material layer 260 may cover another portion 252 of the graphene oxide layer 250 . In this embodiment, the material of the insulating material layer 260 is different from the material of the dielectric layer 242 . The insulating material layer 260 can be a solder resist layer and the material of the insulating material layer 160 can be, for example, green paint or other suitable solder resist ink, but not limited thereto.

In this embodiment, since the hydroxyl group (Hydroxy group) and the epoxy group (Epoxy Group) on the surface of graphene oxide can be combined with metal (such as the copper of the outer layer circuit 243) and organic materials (such as the material of the dielectric layer 242) The green paint) of the insulating material layer 260 is bonded and produces a bonding force, so the graphene oxide layer 250 disposed between the insulating material layer 260 and the build-up circuit structure 240 can be used as an adhesive to improve insulation There are problems of heterogeneity and poor bonding between the material layer 260 and the dielectric layer 242 and between the insulating material layer 260 and the outer circuit 243 , thereby improving the reliability and yield of the circuit board 200 .

For example, in this embodiment, a 3M adhesive tape is used to conduct a 100-grid test to detect the adhesion of the solder resist layer. First, comparative example 1, comparative example 2, and experimental example are provided. Wherein, in comparative example 1, the surface of the outer circuit is first roughened, and then a solder resist layer is formed on the outer circuit. In comparative example 2, the solder resist layer is directly formed on the outer circuit. The experimental example is to form graphene oxide on the outer circuit first, and then form a solder mask layer on the graphene oxide. Then, after the 100-grid test, the drop area of the solder mask of Comparative Example 1 is less than 5%, the drop area of the solder mask of Comparative Example 2 is greater than 65%, and the drop area of the solder mask of the experimental example is less than 5%. 5%. Therefore, from the above test results, it can be seen that the method of using graphene oxide can replace the method of surface roughening to effectively improve the adhesion of the solder resist layer to the outer circuit without roughening, and can avoid the surface roughening of the outer circuit. There is a problem of signal loss.

Next, referring to FIG. 2D , the portion 251 of the graphene oxide layer 250 is reduced to a graphene layer 255 . Specifically, in this embodiment, for example, the portion 251 of the graphene oxide layer 250 is treated with hydrogen plasma or water steaming, so that the graphene oxide in the portion 251 is reduced to graphene, and Portion 251 is reduced to graphene layer 255 . Among them, the graphene layer 255 can have excellent thermal conductivity and electrical conductivity, so the heat dissipation effect of the circuit board 100 can be improved. In addition, the graphene layer 255 can be used to replace surface treatments such as electroless nickel electroless palladium immersion gold (ENEPIG) to protect the pads 2431 and prevent the pads 2431 from being oxidized.

In this embodiment, the graphene oxide layer 250 and the graphene layer 255 are arranged at intervals. The graphene layer 255 can be disposed corresponding to the pad 2431 of the outer circuit 243 , and another portion 252 of the graphene oxide layer 250 can be disposed corresponding to the dielectric layer 242 . That is to say, another part 252 of the graphene oxide layer 250 may be located at the interface between the insulating material layer 260 and the dielectric layer 242 , and located at the interface between the insulating material layer 260 and the outer circuit 243 . In addition, in this embodiment, in the normal direction Z of the build-up circuit structure 240 , the graphene oxide layer 250 can overlap the dielectric layer 242 , and the graphene layer 255 can overlap the pad 2431 of the outer layer circuit 243 . In some embodiments, the graphene oxide layer 250 can contact the dielectric layer 242 , and the graphene layer 255 can contact the pad 2431 of the outer circuit 243 . So far, the circuit board 200 of this embodiment has been substantially completed.

In short, the circuit board 200 of this embodiment may include a substrate 210 , a build-up circuit structure 240 , a graphene oxide layer 250 , a graphene layer 255 and an insulating material layer 260 . The build-up wiring structure 240 is disposed on the substrate 210 . The build-up wiring structure 240 includes at least one inner wiring 241 , at least one dielectric layer 242 , outer wiring 243 and a plurality of conductive holes 244 . The dielectric layer 242 is disposed on the inner circuit 241 . The outer circuit 243 is disposed on the dielectric layer 242 . The conductive hole 244 penetrates through the dielectric layer 242 and electrically connects the inner circuit 241 and the outer circuit 243 . The graphene oxide layer 250 and the graphene layer 255 are spaced apart on the build-up circuit structure 240 . The graphene oxide layer 250 is disposed corresponding to the dielectric layer 242 , and the graphene layer 255 is disposed corresponding to the outer circuit 243 . The insulating material layer 260 is disposed on the graphene oxide layer 250 and the graphene layer 255 . The insulating material layer 260 has an opening 261 , and the opening 261 exposes the graphene layer 255 .

Other embodiments are listed below for illustration. It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 2E to FIG. 2F are cross-sectional schematic diagrams illustrating a manufacturing method of a chip package according to an embodiment of the present invention. FIG. 2E to FIG. 2F are steps following FIG. 2A to FIG. 2D . The same or similar components in the embodiment of FIG. 2E to FIG. 2F and the embodiment of FIG. 2A to FIG. 2D can be made using the same materials or methods, so the following descriptions of the same and similar in the two embodiments will not be repeated. , and mainly describe the differences between the two embodiments.

Referring to FIG. 2E , after forming the circuit board 200 of FIG. 2D , a conductive material layer 270 is then formed in the opening 261 . Wherein, the conductive material layer 270 can contact the graphene layer 255 , and the conductive material layer 270 can be electrically connected to the build-up wiring structure 140 through the graphene layer 255 . In this embodiment, the conductive material layer 270 may be, for example, solder balls or solder paste, and the material of the conductive material layer 270 may be, for example, tin or other suitable conductive materials, but not limited thereto.

Next, please refer to FIG. 2F , disposing the chip 290 on the insulating material layer 260 . Specifically, the chip 290 has pads 291 . The chip 290 can be bonded and electrically connected to the reflowed conductive material layer 270 through the pads 291 , and fixed on the insulating material layer 260 through the primer 295 . So far, the chip package 20 of this embodiment has been substantially completed.

To sum up, in the circuit board and its manufacturing method according to an embodiment of the present invention, by disposing the graphene oxide layer between the insulating material layer and the build-up circuit structure, it can be used to improve the insulating material layer and the build-up circuit structure. There is a problem of heterogeneous bonding between circuit structures (that is, improving the bonding force between the insulating material layer and the build-up circuit structure), thereby improving the reliability and yield of the circuit board. In addition, with the arrangement of graphene, the conductive material layer can be electrically connected to the build-up circuit structure, which can improve the heat dissipation effect of the circuit board and protect the outer circuit from oxidation.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

20: Chip packaging 100, 200: circuit board 110, 210: Substrate 120: release layer 130: Seed layer 140, 180, 240: layer-added line structure 141, 181, 241: inner line 142, 182, 242: dielectric layer 143, 183, 243: outer line 1431, 2431: pad 144, 184, 244: conductive holes 150, 250: graphene oxide layer 151, 251: part 152, 252: another part 155, 255: graphene layer 160, 260: insulating material layer 161, 261: opening 170, 270: conductive material layer 211: via hole 290: chip 291: Pad 295: primer Z: normal direction

FIG. 1A to FIG. 1G are schematic cross-sectional views of a manufacturing method of a circuit board according to an embodiment of the present invention. 2A to 2D are schematic cross-sectional views of a method for manufacturing a circuit board according to another embodiment of the present invention. FIG. 2E to FIG. 2F are cross-sectional schematic diagrams illustrating a manufacturing method of a chip package according to an embodiment of the present invention.

100: circuit board

110: Substrate

120: release layer

130: Seed layer

140, 180: Build-up line structure

141, 181: inner line

142, 182: dielectric layer

143, 183: outer line

1431: Pad

144, 184: conductive hole

150: graphene oxide layer

152: another part

155: graphene layer

160: insulating material layer

170: conductive material layer

Z: normal direction

Claims (15)

A circuit board, comprising: Substrate; The build-up circuit structure is arranged on the substrate and includes: at least one inner circuit; at least one dielectric layer disposed on the at least one inner layer circuit; an outer line disposed on the at least one dielectric layer; and A plurality of conductive holes penetrate the at least one dielectric layer and electrically connect the at least one inner layer circuit and the outer layer circuit; A graphene oxide layer and a graphene layer are arranged at intervals on the build-up circuit structure, wherein the graphene oxide layer is arranged corresponding to the at least one dielectric layer, and the graphene layer corresponds to the outer layer circuit settings; and The insulating material layer is disposed on the graphene oxide layer and the graphene layer, wherein the insulating material layer has an opening, and the opening exposes the graphene layer. The wiring board as claimed in claim 1, wherein the material of the at least one dielectric layer is different from the material of the insulating material layer. The circuit board according to claim 1, wherein the insulating material layer is another dielectric layer or a solder resist layer. The circuit board according to claim 1, wherein in the normal direction of the build-up circuit structure, the graphene oxide layer overlaps the at least one dielectric layer, and the graphene layer overlaps the outer line. The circuit board according to claim 1, wherein the graphene oxide layer contacts the at least one dielectric layer, and the graphene layer contacts the outer circuit. The circuit board as described in request item 1, further comprising: The conductive material layer is disposed in the opening and electrically connected to the build-up circuit structure through the graphene layer. The wiring board according to claim 1, wherein the graphene oxide layer is located at the interface between the insulating material layer and the at least one dielectric layer, and is located between the insulating material layer and the outer circuit interface. A method for manufacturing a circuit board, comprising: Provide the substrate; forming a build-up circuit structure on the substrate, wherein the build-up circuit structure includes: at least one inner circuit; at least one dielectric layer disposed on the at least one inner layer circuit; an outer line disposed on the at least one dielectric layer; and A plurality of conductive holes penetrate the at least one dielectric layer and electrically connect the at least one inner layer circuit and the outer layer circuit; forming a graphene oxide layer on the build-up circuit structure; forming an insulating material layer on the graphene oxide layer, wherein the insulating material layer has an opening, and the opening exposes a part of the graphene oxide layer; and reducing the portion of the graphene oxide layer into a graphene layer, wherein the graphene layer is disposed corresponding to the outer circuit, and another portion of the graphene oxide layer corresponds to the at least one dielectric layer set up. The method for manufacturing a circuit board as claimed in claim 8, wherein the material of the at least one dielectric layer is different from the material of the insulating material layer. The method for making a circuit board as claimed in claim 8, wherein the insulating material layer is another dielectric layer or a solder resist layer. The method for making a circuit board according to claim 8, wherein in the normal direction of the build-up circuit structure, the graphene oxide layer overlaps the at least one dielectric layer, and the graphene layer overlaps on the outer line. The method for manufacturing a circuit board according to claim 8, wherein the graphene oxide layer contacts the at least one dielectric layer, and the graphene layer contacts the outer circuit. The manufacturing method of the circuit board as described in claim item 8, also includes: A conductive material layer is formed in the opening, wherein the conductive material layer is electrically connected to the build-up circuit structure through the graphene layer. The method for making a circuit board according to claim 8, wherein the graphene oxide layer is located at the interface between the insulating material layer and the at least one dielectric layer, and is located between the insulating material layer and the outer layer interface between lines. The method for making a wiring board as claimed in item 8, wherein the method for reducing the part of the graphene oxide layer to the graphene layer comprises: using plasma or treated by steaming.

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