TWI797691B - 半導體製造方法及半導體裝置 - Google Patents
半導體製造方法及半導體裝置 Download PDFInfo
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Abstract
實施形態提供一種可在凹部內適當地形成配線的半導體製造方法及半導體裝置。根據一實施形態,半導體製造方法包含:自設於基板上方的至少局部地具有絕緣層的層的上表面朝向下方形成凹部。所述方法更包含:於凹部的內面上形成矽膜。所述方法更包含:在第一溫度下,將矽膜曝露於金屬的原料氣體及抑制金屬的成長的抑制氣體中,將位於凹部的上端側的矽膜的第一部分取代為含有金屬的第一導電膜。所述方法更包含:在較第一溫度為低的第二溫度下,將矽膜曝露於原料氣體及抑制氣體中,將與第一部分不同的矽膜的第二部分取代為含有金屬的第二導電膜。
Description
[相關申請案]
本申請案享有以日本專利申請案2021-041724號(申請日:2021年3月15日)為基礎申請案的優先權。本申請案藉由參照該基礎申請案而包含基礎申請案的全部內容。
本實施形態是有關於一種半導體製造方法及半導體裝置。
於半導體裝置的製造中,有時會在設於絕緣層的凹部內嵌入形成配線。此時,有在配線內產生空洞之虞。
本發明所欲解決的課題在於提供一種可於凹部內適當地形成配線的半導體製造方法及半導體裝置。
根據一個實施形態,半導體製造方法包含:自設於基板上方的至少局部地具有絕緣層的層的上表面朝向下方形成凹部。所述方法更包含:於凹部的內面上形成矽膜。所述方法更包含:在第一溫度下,將矽膜曝露於金屬的原料氣體及抑制金屬的成長
的抑制氣體中,將位於凹部的上端側的矽膜的第一部分取代為含有金屬的第一導電膜。所述方法更包含:在較第一溫度為低的第二溫度下,將矽膜曝露於原料氣體及抑制氣體中,將與第一部分不同的矽膜的第二部分取代為含有金屬的第二導電膜。
1、2:半導體基板
3:層間絕緣膜
4:配線層
5:矽膜
6:記憶胞元
30:積層體
31:上表面
32:凹部
41:阻障金屬膜
42:第一導電膜
43:第二導電膜
44:導電層
61:記憶體孔
301:絕緣層
302:導電層
320:狹縫
P1:第一位置
P2:第二位置
R1:第一範圍
R2:第二範圍
w:寬度
圖1是表示實施形態的半導體裝置的剖面圖。
圖2是表示實施形態的半導體製造方法的剖面圖。
圖3是表示繼圖2之後的、實施形態的半導體製造方法的剖面圖。
圖4是表示繼圖3之後的、實施形態的半導體製造方法的剖面圖。
圖5是表示繼圖4之後的、實施形態的半導體製造方法的剖面圖。
圖6是表示繼圖5之後的、實施形態的半導體製造方法的剖面圖。
圖7是表示繼圖6之後的、實施形態的半導體製造方法的剖面圖。
圖8是表示第一變形例的半導體裝置的剖面圖。
圖9是表示第二變形例的半導體裝置的剖面圖。
圖10是表示第二變形例的半導體製造方法的剖面圖。
圖11是表示繼圖10之後的、第二變形例的半導體製造方法
的剖面圖。
以下,參照圖式來說明本發明的實施形態。圖1至圖7中,對於相同或類似的結構標註相同的符號,並省略重複說明。圖1是表示實施形態的半導體裝置1的圖。
如圖1所示,實施形態的半導體裝置1包括半導體基板2、層間絕緣膜3以及配線層4。
層間絕緣膜3被設於半導體基板2的上方。於層間絕緣膜3,自層間絕緣膜3的上表面31朝向下方設有凹部32。凹部32的橫方向的寬度w於凹部32的上端與下端之間的第一位置P1處達到最大。而且,凹部32的寬度w隨著自凹部32的上端朝向第一位置P1而增加。而且,凹部32的寬度w隨著自第一位置P1朝向凹部32的下端而減少。換言之,凹部32的剖面具有大致樽型,即,大致六邊形狀。如此,於第一位置P1處達到最大寬度的凹部32的形狀是即便均勻地設計凹部32的寬度w,亦可因製程上的因素而獲得的形狀。作為製程上的因素,例如可列舉:在藉由反應離子蝕刻(Reactive Ion Etching,RIE)法來形成凹部32的情況下,於凹部32的P1附近,保護側壁不受蝕刻氣體影響的蝕刻時的副生成物的吸附少,而且蝕刻離子的傾斜方向成分容易入射。而且,凹部32的剖面亦可具有圓弧。凹部32的高度h較寬度w為大。凹部32亦可為孔。或者,凹部32亦可為沿與寬度
方向正交的縱深方向延伸的槽或狹縫。層間絕緣膜3例如為矽氧化膜。
配線層4是以填埋凹部32的方式而設在凹部32的內部。配線層4具有阻障金屬膜41、第一導電膜42、第二導電膜43以及導電層44。
阻障金屬膜41遍及整面而設於凹部32的內面上。阻障金屬膜41例如為氮化鈦膜。
第一導電膜42經由阻障金屬膜41而設於凹部32的內面的上端側的第一範圍R1上。第一範圍R1是自凹部32的內面的上端直至較第一位置P1為上側的第二位置P2為止的範圍。第一導電膜42含有金屬及抑制所述金屬的成長的抑制物質。金屬例如為鎢。抑制物質例如為氮。
第二導電膜43經由阻障金屬膜41而設於凹部32的內面的與第一範圍R1不同的第二範圍R2上。於圖1所示的示例中,第二範圍R2是凹部32的內面的第一範圍R1以外的所有範圍。第二導電膜43含有與第一導電膜42中所含的金屬相同的金屬(例如鎢)。而且,第二導電膜43含有與第一導電膜42中所含的抑制物質相同的抑制物質(例如氮)。
導電層44被設於第一導電膜42及第二導電膜43上。導電層44含有與第一導電膜42中所含的金屬相同的金屬(例如鎢)。
第一導電膜42的抑制物質的含有濃度較第二導電膜43
高。藉由第一導電膜42中的抑制物質的含有濃度高,從而可抑制於導電層44內產生空洞。
接下來,參照圖2~圖7來說明如以上般構成的半導體裝置1的製造方法。
圖2是表示實施形態的半導體製造方法的剖面圖。首先,如圖2所示,對於設在半導體基板2上的層間絕緣膜3,自層間絕緣膜3的上表面31朝向下方而形成凹部32。凹部32例如是藉由光微影(photolithography)法或RIE法而形成。於形成了凹部32之後,如圖2所示,於凹部32的內面上形成阻障金屬膜41。阻障金屬膜41的形成例如是藉由利用化學氣相沈積(Chemical Vapor Deposition,CVD)法來使氮化鈦膜成膜而進行。藉由形成阻障金屬膜41,從而可確保配線層4對凹部32的密接性,且可抑制配線層4中所含的金屬向層間絕緣膜3內的擴散。
圖3是表示繼圖2之後的、實施形態的半導體製造方法的剖面圖。於形成了阻障金屬膜41之後,如圖3所示,經由阻障金屬膜41而於凹部32的內面上形成矽膜5。矽膜5例如是藉由CVD法而形成。基於使矽膜5適當地取代為第一導電膜42、第二導電膜43的觀點,矽膜5的膜厚較佳為0.5nm~10nm。
圖4是表示繼圖3之後的、實施形態的半導體製造方法的剖面圖。於形成了矽膜5之後,如圖4所示,在第一溫度下,將矽膜5暴露於第一導電膜42中所含的金屬(例如鎢)的原料氣體及抑制所述金屬的成長的抑制氣體中。第一溫度為400℃以上,
例如亦可為500℃。藉由將第一溫度設為400℃以上,從而可將作為抑制物質的一例的氮於第一導電膜42中的含有濃度設為6[原子%]以上的高濃度。原料氣體例如為六氟化鎢(WF6)氣體。抑制氣體為已述的抑制物質的氣體,例如為氮氣。藉由在第一溫度下將矽膜5暴露於原料氣體及抑制氣體中,從而如圖4所示,將位於凹部32的上端側即第一範圍R1上的矽膜5的第一部分取代為第一導電膜42。此時,將使矽膜5暴露於原料氣體及抑制氣體中的時間設為相對較短的時間,以使得僅有第一部分被取代為第一導電膜42。第一溫度下的暴露時間例如亦可為數秒。矽膜5向第一導電膜42的局部取代例如是藉由CVD法來進行。
圖5是表示繼圖4之後的、實施形態的半導體製造方法的剖面圖。將矽膜5局部地取代為第一導電膜42後,如圖5所示,在較第一溫度為低的第二溫度下,將矽膜5暴露於所述原料氣體及抑制氣體中。第二溫度小於400℃,例如亦可為300℃。藉由使第二溫度小於400℃,從而可將氮於第二導電膜43中的含有濃度設為小於6[原子%]的低濃度。藉由在第二溫度下將矽膜5暴露於原料氣體及抑制氣體中,從而如圖5所示,將位於凹部32的第二範圍R2上的矽膜的第二部分取代為第二導電膜43。將矽膜5暴露於原料氣體及抑制氣體中的時間設為較在第一溫度下的暴露的時間為長的時間,以使得第二部分被適當地取代為第二導電膜43。在第二溫度下的暴露時間例如亦可為數十秒。矽膜5向第二導電膜43的局部取代例如是藉由CVD法來進行。
藉此,形成抑制物質的含有濃度高的第一導電膜42與抑制物質的含有濃度低的第二導電膜43。
圖6是表示繼圖5之後的、實施形態的半導體製造方法的剖面圖。於將矽膜5取代為第一導電膜42及第二導電膜43之後,如圖6所示,使用原料氣體來形成填埋凹部32的導電層44。導電層44的形成例如是藉由CVD法來進行。
此處,假如導電層44以均勻的成長速度於第一導電膜42及第二導電膜43上形成的情況下,在寬度w達到最大的第一位置P1處凹部32被導電層44填埋之前,在較第一位置P1為上方的開口側,凹部32便會被導電層44填埋。即,用於向凹部32內導入原料氣體的凹部32的開口將被導電層44堵塞。因凹部32的開口被堵塞,從而以後的導電層44的成長受到阻礙,其結果,在第一位置P1側,在導電層44產生空洞。
與此相對,根據實施形態,第一導電膜42中,抑制構成導電層44的金屬(例如鎢)的成長的抑制物質的含有濃度高。藉此,如圖6所示,導電層44優先形成於第二導電膜43上。即,導電層44在位於凹部32的上端的開口側的第一導電膜42上的形成得到抑制。藉由抑制導電層44在第一導電膜42上的形成,從而可抑制在凹部32內被導電層44填埋之前,凹部32的開口便被導電層44堵塞的現象。
再者,導電層44亦可藉由繼續在第二溫度下將矽膜5暴露於原料氣體及抑制氣體中的步驟而形成。藉此,可削減工時。
圖7是表示繼圖6之後的、實施形態的半導體製造方法的剖面圖。藉由相對於圖6而進一步進行導電層44的形成,從而如圖7所示,於第一導電膜42及第二導電膜43上形成導電層44。藉由抑制導電層44在第一導電膜42上的形成而抑制凹部32的上端的開口被導電層44堵塞的現象,從而如圖7所示,抑制導電層44內的空洞。
如上所述,根據本實施形態,藉由在第一溫度下將矽膜曝露於原料氣體及抑制氣體中而將位於凹部32的上端側的矽膜5的第一部分取代為第一導電膜42,且在較第一溫度為低的第二溫度下將矽膜5曝露於原料氣體及抑制氣體中而將與第一部分不同的矽膜5的第二部分取代為第二導電膜43,從而可抑制導電層44的空洞。藉此,可於凹部32內適當地形成配線層4。藉由形成抑制了空洞的配線層4,從而可適當地確保配線層4的電氣特性(電阻值)及機械強度。
對於所述實施形態,可適用以下所示的多個變形例。
圖8是表示第一變形例的半導體裝置1的剖面圖。圖1中,對在凹部32的內面與第一導電膜42及第二導電膜43之間具有阻障金屬膜41的半導體裝置1進行了說明。與此相對,如圖8所示,亦可省略阻障金屬膜41。根據第一變形例,可削減製造工時及成本。
圖9是表示第二變形例的半導體裝置1的剖面圖。圖1中,對在設於層間絕緣膜3的凹部32內設有配線層4的半導體裝
置1進行了說明。與此相對,如圖9所示,配線層4亦可設於自絕緣層301與導電層302的積層體30的上表面朝向下方而設的狹縫320內。圖9所示的半導體裝置1為三次元半導體記憶體。絕緣層301例如為矽氧化膜。導電層302例如含有鎢。
第二變形例的半導體裝置1包括貫穿積層體30的柱狀的記憶胞元6。記憶胞元6具有記憶體膜(未圖示)與記憶體膜的內側的矽柱(未圖示)。記憶體膜例如自外側起依序具有阻塞絕緣膜、電荷蓄積層與隧道絕緣膜。配線層4被用於將連接於配線層4下端的源極線(未圖示)連接至上層配線(未圖示)。而且,狹縫320被用於將後述的絕緣層301間的犧牲層303取代(replace)為導電層302。
圖10是表示第二變形例的半導體製造方法的剖面圖。於製造第二變形例的半導體基板1時,如圖10所示,於半導體基板2上,例如藉由CVD法而形成絕緣層301與犧牲層303的積層體30。犧牲層303例如為矽氮化膜。並且,例如在藉由RIE法而形成貫穿積層體30的記憶體孔61後,於記憶體孔61內形成記憶胞元6。記憶胞元6亦可以下層部的形成與上層部的形成這兩階段而形成。進而,例如藉由RIE法來設置貫穿積層體30的狹縫320。
圖11是表示繼圖10之後的、第二變形例的半導體製造方法的剖面圖。於形成了狹縫320後,如圖11所示,藉由通過狹縫320的濕式蝕刻而自積層體30選擇性地去除犧牲層303。
去除了犧牲層303後,在藉由犧牲層303的去除而形成
的空洞內,例如藉由CVD法而形成導電層302。而且,於狹縫320內,利用與圖1~圖8同樣的方法形成配線層4。
根據第二變形例,在三次元半導體記憶體的製造步驟中,可於狹縫320內適當地形成配線層4。
以上,對若干實施形態進行了說明,但該些實施形態僅作為例示而提示,並不意圖限定發明的範圍。本說明書中說明的新穎的裝置及方法能以其他的各種形態來實施。而且,對於在本說明書中說明的裝置及方法的形態,可在不脫離發明主旨的範圍內進行各種省略、替換、變更。隨附的申請專利範圍及與其均等的範圍意圖涵蓋發明的範圍或主旨中所含的此種形態或變形例。
1、2:半導體基板
3:層間絕緣膜
4:配線層
31:上表面
32:凹部
41:阻障金屬膜
42:第一導電膜
43:第二導電膜
44:導電層
P1:第一位置
P2:第二位置
R1:第一範圍
R2:第二範圍
w:寬度
Claims (20)
- 一種半導體製造方法,包含: 自設於基板上方的至少局部地具有絕緣層的層的上表面朝向下方形成凹部; 於所述凹部的內面上形成矽膜; 在第一溫度下,將所述矽膜曝露於金屬的原料氣體及抑制所述金屬的成長的抑制氣體中,將位於所述凹部的上端側的所述矽膜的第一部分取代為含有所述金屬的第一導電膜;以及 在較所述第一溫度為低的第二溫度下,將所述矽膜曝露於所述原料氣體及所述抑制氣體中,將與所述第一部分不同的所述矽膜的第二部分取代為含有所述金屬的第二導電膜。
- 如請求項1所述的半導體製造方法,更包含: 於所述第一導電膜及所述第二導電膜上形成含有所述金屬的導電層。
- 如請求項1所述的半導體製造方法,其中 在所述第二溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中,藉此,所述第二部分被取代為所述第二導電膜,且在所述第一導電膜及所述第二導電膜上形成含有所述金屬的導電層。
- 如請求項1所述的半導體製造方法,其中 在所述第一溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間,較在所述第二溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間為短。
- 如請求項2所述的半導體製造方法,其中 在所述第一溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間,較在所述第二溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間為短。
- 如請求項3所述的半導體製造方法,其中 在所述第一溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間,較在所述第二溫度下將所述矽膜曝露於所述原料氣體及所述抑制氣體中的時間為短。
- 如請求項1所述的半導體製造方法,其中 所述第一導電膜的所述抑制氣體的成分的濃度較所述第二導電膜為高。
- 如請求項2所述的半導體製造方法,其中 所述第一導電膜的所述抑制氣體的成分的濃度較所述第二導電膜為高。
- 如請求項3所述的半導體製造方法,其中 所述第一導電膜的所述抑制氣體的成分的濃度較所述第二導電膜為高。
- 如請求項4所述的半導體製造方法,其中 所述第一導電膜的所述抑制氣體的成分的濃度較所述第二導電膜為高。
- 如請求項1所述的半導體製造方法,更包含: 在形成所述矽膜之前,於所述凹部的內面上形成金屬膜。
- 如請求項1所述的半導體製造方法,其中 所述金屬為鎢。
- 如請求項12所述的半導體製造方法,其中 所述原料氣體為六氟化鎢氣體, 所述抑制氣體為氮氣。
- 如請求項1所述的半導體製造方法,其中 所述第一溫度為400℃以上, 所述第二溫度小於400℃。
- 如請求項1所述的半導體製造方法,其中 所述矽膜形成為0.5 nm~10 nm的厚度。
- 如請求項1所述的半導體製造方法,其中 所述凹部的寬度在所述凹部的上端與下端之間的第一位置處達到最大,隨著自所述上端朝向所述第一位置而增加,且隨著自所述第一位置朝向所述下端而減少。
- 如請求項16所述的半導體製造方法,其中 所述第一部分是形成於自所述凹部的上端直至較所述第一位置為上側的第二位置為止的範圍上的所述矽膜的部分。
- 一種半導體裝置,包括: 層,設於基板的上方,自上表面朝向下方而設有凹部且至少局部地具有絕緣層; 第一導電膜,設於所述凹部的內面的上端側的第一範圍上,含有金屬及抑制所述金屬的成長的抑制物質; 第二導電膜,設於所述凹部的內面的與第一範圍不同的第二範圍上,含有所述金屬及所述抑制物質;以及 導電層,設於所述第一導電膜及所述第二導電膜上,含有所述金屬, 所述第一導電膜的所述抑制物質的含有濃度較所述第二導電膜為高。
- 如請求項18所述的半導體裝置,其中 所述金屬為鎢, 所述抑制物質為氮。
- 如請求項18所述的半導體裝置,其中 具有所述絕緣層的層為所述絕緣層與導電層的積層體。
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