TWI794730B - 半導體晶圓及其製造方法 - Google Patents

半導體晶圓及其製造方法 Download PDF

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TWI794730B
TWI794730B TW110101549A TW110101549A TWI794730B TW I794730 B TWI794730 B TW I794730B TW 110101549 A TW110101549 A TW 110101549A TW 110101549 A TW110101549 A TW 110101549A TW I794730 B TWI794730 B TW I794730B
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insulator
substrate
wafer
edge
semiconductor wafer
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TW110101549A
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TW202137396A (zh
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飯島純
中木寛
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日商鎧俠股份有限公司
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Abstract

本文描述之實施例係關於一種半導體晶圓及其製造方法。 在一實施例中，一種半導體晶圓包含一第一基板、提供於該第一基板上之一第一絕緣體及提供於該第一絕緣體中之複數個第一墊。該晶圓進一步包含提供於該第一絕緣體上之一第二絕緣體、提供於該第二絕緣體中之該等第一墊上之複數個第二墊、提供於該第二絕緣體中之交替地包含複數個第一絕緣層及複數個第二絕緣層之一堆疊膜及提供於該第二絕緣體上之一第二基板。此外，該第一絕緣體及該第二絕緣體在該第一絕緣體之一邊緣面與該第二絕緣體之一邊緣面之間彼此連接，且該第二絕緣體在該第一絕緣體及該第二絕緣體之該等邊緣面處插置於該第一絕緣體與該堆疊膜之間。

Description

半導體晶圓及其製造方法
本文描述之實施例係關於一半導體晶圓及其製造方法。
當藉由接合晶圓(基板)之金屬墊來製造一半導體裝置時，期望減少對晶圓之邊緣部分之浪費處置。
在一實施例中，一種半導體晶圓包含一第一基板、提供於該第一基板上之一第一絕緣體及提供於該第一絕緣體中之複數個第一墊。該晶圓進一步包含提供於該第一絕緣體上之一第二絕緣體、提供於該第二絕緣體中之該等第一墊上之複數個第二墊、提供於該第二絕緣體中之交替地包含複數個第一絕緣層及複數個第二絕緣層之一堆疊膜及提供於該第二絕緣體上之一第二基板。此外，該第一絕緣體及該第二絕緣體在該第一絕緣體之一邊緣面與該第二絕緣體之一邊緣面之間彼此連接，且該第二絕緣體在該第一絕緣體及該第二絕緣體之該等邊緣面處插置於該第一絕緣體與該堆疊膜之間。
根據該實施例，可減少對該等基板之該等邊緣部分或其類似者之浪費處置。
現將參考隨附圖式闡釋實施例。在圖1至圖23中，相同組件由相同元件符號表示，且將省略對其之重複描述。 (第一實施例)
圖1係繪示第一實施例之一半導體裝置之結構之一橫截面圖。圖1所繪示之半導體裝置係一三維記憶體，其包含接合在一起之一陣列晶片1及電路晶片2。
陣列晶片1包含：包含複數個記憶體單元之一記憶體單元陣列11、記憶體單元陣列11上之一絕緣體12及記憶體單元陣列11之下之一層間介電質13。絕緣體12例如係氧化矽膜或氮化矽膜。層間介電質13例如係氧化矽膜，或包含氧化矽膜及另一絕緣體之一堆疊膜。層間介電質13係一第二絕緣體之一實例。
電路晶片2提供於陣列晶片1下方。陣列晶片1與電路晶片2接合在由元件符號S指示之一接合面處。電路晶片2包含一層間介電質14及層間介電質14之下之一基板15。層間介電質14例如係氧化矽膜，或包含氧化矽膜及另一絕緣體之一堆疊膜。層間介電質14係一第一絕緣體之一實例。基板15例如係諸如一矽基板之一半導體基板。
圖1繪示與基板15之一表面平行且彼此垂直之X及Y方向及垂直於基板15之表面之Z方向。在本說明書中，+Z方向被視為一向上方向，且-Z方向被視為一向下方向。-Z方向可能與重力方向匹配，亦可能與重力方向不匹配。
陣列晶片1包含複數個字線WL及一源線SL作為記憶體單元陣列11中之電極層。圖1繪示記憶體單元陣列11之一階梯結構部分21。各字線WL經由一接觸插頭22電連接至一字線層23。穿透複數個字線WL之各柱狀部分CL經由一通孔插頭24電連接至一位元線BL，且電連接至源線SL。源線SL包含作為一半導體層之一初級層SL1及作為一金屬層之一次級層SL2。
電路晶片2包含複數個電晶體31。各電晶體31包含經由一閘極絕緣體提供於基板15上之一閘極電極32及提供於基板15中之一源極擴散層(未繪示)及一汲極擴散層(未繪示)。進一步而言，電路晶片2包含提供於此等電晶體31之閘極電極32、源極擴散層或汲極擴散層上之複數個接觸插頭33、提供於此等接觸插頭33上並包含複數個線之一線層34及提供於線層34上並包含複數個線之一線層35。
電路晶片2進一步包含提供於線層35上並包含複數個線之一線層36、提供於線層36上之複數個通孔插頭37及提供於此等通孔插頭37上之複數個金屬墊38。金屬墊38例如係一銅(Cu)層或一鋁(Al)層。金屬墊38係一第一墊之一實例。電路晶片2用作一控制陣列晶片1之操作之一控制電路(一邏輯電路)。控制電路經組態具有電晶體31及其類似者，且電連接至金屬墊38。
陣列晶片1包含提供於金屬墊38上之複數個金屬墊41及提供於金屬墊41上之複數個通孔插頭42。進一步而言，陣列晶片1包含提供於此等通孔插頭42上並包含複數個線之一線層43及提供於線層43上並包含複數個線之一線層44。金屬墊41例如係一Cu層或一Al層。金屬墊41係一第二墊之一實例。以上提及之位元線BL包含在線層44中。控制電路經由金屬墊41及38及其類似者電連接至記憶體單元陣列11，且經由金屬墊41及38及其類似者控制記憶體單元陣列11之操作。
陣列晶片1進一步包含提供於線層44上之複數個通孔插頭45、提供於此等通孔插頭45或絕緣體12上之一金屬墊46及提供於金屬墊46或絕緣體12上之一鈍化膜47。金屬墊46例如一係Cu層或一Al層，且用作圖1所繪示之半導體裝置之一外部連接墊(一接合墊)。鈍化膜47例如係諸如氧化矽膜之一絕緣體，且具有曝露金屬墊46之一上表面之一孔P。金屬墊46可透過孔P借助於一接合線、一焊球、一金屬凸塊或其類似者連接至安裝基板或另一裝置。
圖2係繪示第一實施例之柱狀部分CL之結構之一橫截面圖。
如圖2所繪示，記憶體單元陣列11包含交替地堆疊在層間介電質13上之複數個字線WL及複數個絕緣層51 (見圖1)。字線WL例如係一鎢(W)層。絕緣層51例如係氧化矽膜。
柱狀部分CL包含依次配置之一塊絕緣體52、一電荷儲存層53、一隧道絕緣體54、一通道半導體層55及核心絕緣體56。電荷儲存層53例如係氮化矽膜，且經由塊絕緣體52形成於字線WL及絕緣層51之側面上。電荷儲存層53可為諸如一多晶矽層之一半導體層。通道半導體層55例如係一多晶矽層，且經由隧道絕緣體54形成於電荷儲存層53之一側面上。塊絕緣體52、隧道絕緣體54及核心絕緣體56之各者例如係氧化矽膜或一金屬絕緣體。
圖3及圖4係繪示製造第一實施例之半導體裝置之一方法之橫截面圖。
圖3繪示包含複數個陣列晶片1之一陣列晶圓W1及包含複數個電路晶片2之一電路晶圓W2。陣列晶圓W1亦指稱「記憶體晶圓」，且電路晶圓W2亦指稱「CMOS晶圓」。
注意，圖3中所繪示之陣列晶圓W1之定向與圖1所繪示之陣列晶片1之定向相反。在本實施例中，陣列晶圓W1與電路晶圓W2接合在一起以製造一半導體裝置。圖3繪示陣列晶圓W1之定向被翻轉以進行接合之前的一狀態，且圖1繪示陣列晶片1之定向被翻轉以進行接合接著被接合及切割之後的一狀態。
在圖3中，元件符號S1指示陣列晶圓W1之一上表面，且元件符號S2指示電路晶圓W2之一上表面。注意，陣列晶圓W1包含提供於絕緣體12之下之一基板16。基板16例如係諸如一矽基板之一半導體基板。基板15係一第一基板之一實例，且基板16係一第二基板之一實例。圖3中所繪示之基板15及基板16之各者係在被切割之前的一半導體晶圓，且具有一盤形狀。
在本發明實施例中，製造方法包含：首先，在陣列晶圓W1之基板16上形成記憶體單元陣列11、絕緣體12、層間介電質13、階梯結構部分21及金屬墊41及其類似者，接著在電路晶圓W2之基板15上形成層間介電質14、電晶體31、金屬墊38及其類似者，如圖3中所繪示。例如，在基板16上依次形成通孔插頭45、線層44、線層43、通孔插頭42及金屬墊41。進一步而言，在基板15上依次形成接觸插頭33、線層34、線層35、線層36、通孔插頭37及金屬墊38。該方法包含隨後在一機械壓力下將陣列晶圓W1與電路晶圓W2接合在一起，如圖4所繪示。結果，層間介電質13與層間介電質14接合在一起。該方法包含隨後在400℃對陣列晶圓W1及電路晶圓W2進行退火。結果，金屬墊41與金屬墊38結合在一起。
該方法包含隨後藉由化學機械拋光(CMP)使基板15變薄，且在藉由CMP移除基板16之後，將陣列晶圓W1及電路晶圓W2切割為複數個晶圓。以此方式，製造了圖1之半導體裝置。圖1繪示包含金屬墊38及層間介電質14之電路晶片2及分別安置於金屬墊38及層間介電質14上之包含金屬墊41及層間介電質13之陣列晶片1。金屬墊46及鈍化膜47例如在基板15變薄及基板16移除之後形成於絕緣體12上。
在本發明實施例中，雖然陣列晶圓W1與電路晶圓W2接合在一起，但改為將陣列晶圓W1接合在一起可能係可行的。參考圖1至圖4描述之上述內容及將參考圖5A至圖23描述之以下內容亦適用於陣列晶圓W1之接合。
進一步而言，儘管圖1繪示層間介電質13與層間介電質14之間的邊界面及金屬墊41與金屬墊38之間的一邊界面，但通常在上述退火之後未觀察到此等邊界面。然而，可藉由偵測例如金屬墊41之側面或金屬墊38之側面之傾斜或金屬墊41之側面與金屬墊38之側面之間的位置偏差來估計存在此等邊界面之位置。
本發明實施例之半導體裝置可為在被切割為複數個晶圓之後在圖1所繪示之狀態下被處理之一物件，或可為在被切割為複數個晶圓之前在圖4所繪示之狀態下被處理之一物件。圖1繪示處於一晶片狀態之半導體裝置，且圖4繪示處於一晶片狀態之半導體裝置。在本發明實施例中，可自一單個晶片狀態半導體裝置(見圖4)製造複數個晶片狀態半導體裝置(見圖1)。圖4所繪示之晶片狀態半導體裝置例如在下文將描述之修整之後的一狀態下成為要處理之一物件。圖4所繪示之晶片狀態半導體裝置係半導體晶圓之一實例。
在下文中，參考圖5A至圖11，將更詳細地描述製造本發明實施例之半導體裝置之方法。
圖5A至圖8B係繪示製造第一實施例之陣列晶圓W1之方法之橫截面圖。
圖5A繪示基板16、作為層間介電質13之一部分之一絕緣體13a及在絕緣體13a中形成之複數個柱狀部分CL。然而，未繪示基板16與柱狀部分CL之間的絕緣體12及源線SL (如與圖3相比所理解)。絕緣體13a係一第一膜之一實例。
圖5A進一步繪示在絕緣體13a中之此等柱狀部分CL上依次形成之線層43及複數個通孔插頭42。然而，未繪示柱狀部分CL與線層43之間的通孔插頭24及位元線BL (線層43)(如與圖3相比所理解的)。
如上所述，圖5A繪示在圖3中所繪示之程序中形成通孔插頭42之後及在形成金屬墊41之前的一階段。
圖5A中所繪示之基板16係在被切割之前的一半導體晶圓，且具有一盤形狀。圖5A進一步繪示基板16之一中心部分A1、一邊緣部分B1及一最外部分C1。中心部分A1係基板16之中心軸側上之一區域，且邊緣部分B1係基板16之最外部分C1側上之一區域。本發明實施例之邊緣部分B1具有環繞中心部分A1之一環形(環狀)形狀。
在本實施例中，基板16之邊緣部分B1之一上表面低於基板16之中心部分A1之一上表面。進一步而言，邊緣部分B1上之絕緣體13a之一上表面低於中心部分A1上之絕緣體13a之一上表面。原因係因為：在圖3中所繪示之程序中，當基板16之表面及絕緣體13a之表面藉由CMP來平坦化時，基板16之表面及絕緣體13a之表面在邊緣部分B1中被過度拋光。在圖5A中，邊緣部分B1上之絕緣體13a之上表面與中心部分A1上之絕緣體13a之上表面之間在豎直方向上之位準差例如為1 μm至2 μm，且在此實施例中約為1.5 μm。
當此一位準差保持至陣列晶圓W1與電路晶圓W2接合為止時，邊緣部分B1上之層間介電質13不接合至層間介電質14。即，邊緣部分B1上之層間介電質13之表面成為一未接合區域。在本發明實施例中，藉由修整來切割非接合區域上方及下方之陣列晶圓W1及電路晶圓W2。因此，當未接合區域較寬時，陣列晶圓W1及電路晶圓W2具有較小之有效晶圓區域，且陣列晶圓W1及電路晶圓W2之修整部分被浪費地丟棄。因此，在本發明實施例中，期望減少對邊緣部分B1之浪費處置。因此，在本發明實施例中，藉由以下方法消除了上述位準差。
該方法包含隨後經由絕緣體13a在基板16之中心部分A1及邊緣部分B1上方形成一絕緣體13b，絕緣體13b係層間介電質13之一部分(見圖5B)。絕緣體13b例如係一緻密正矽酸乙酯(dTEOS)膜，且形成為具有1 μm至2 μm之一厚度。注意，在圖5B中，邊緣部分B1上方之絕緣體13b之上表面低於中心部分A1上方之絕緣體13b之上表面。絕緣體13b係一第二膜之一實例。
該方法包含隨後經由絕緣體13a及絕緣體13b在基板16之中心部分A1及邊緣部分B1上方形成一光阻膜17 (見圖6A)。形成光阻膜17以便具有例如約1 μm之一厚度。
該方法包含隨後移除基板16之中心部分A1上方之光阻膜17 (見圖6A)。此時，中心部分A1上方之光阻膜17被部分地移除(即，不完全移除)。具體而言，在中心部分A1上方之光阻膜17之中心部分A1與邊緣部分B1之間的邊界附近之光阻膜17被留下。
該方法包含隨後藉由使用光阻膜17進行蝕刻來移除基板16之中心部分A1上方之絕緣體13b (見圖6B)。此時，由於僅移除自光阻膜17曝露之絕緣體13b，因此中心部分A1上方之絕緣體13b被部分地移除(即，不完全移除)。具體而言，在中心部分A1上方之絕緣體13b在中心部分A1與邊緣部分B1之間的邊界附近之絕緣體13b保持不變。圖6B繪示保持於中心部分A1與邊緣部分B1之間的邊界附近之絕緣體13b之一突出部分T1。本發明實施例之突出部分T1具有與邊緣部分B1類似之一環形形狀。圖6B所繪示之程序中之蝕刻例如係使用含有緩衝氫氟酸(BHF)之一液體藥物之濕蝕刻。
該方法包含隨後移除光阻膜17 (見圖7A)。例如，藉由幹灰化移除光阻膜17。圖7A繪示在圖6B之程序中自絕緣體13b曝露之通孔插頭42。
該方法包含隨後經由絕緣體13a及絕緣體13b在基板16之中心部分A1及邊緣部分B1上方形成絕緣體13c，該絕緣體13c係層間介電質13之一部分(見圖7B)。結果，通孔插頭42被絕緣體13c覆蓋。進一步而言，絕緣體13c部分地自絕緣體13b之突出部分T1突出。本發明實施例之絕緣體13c係由與絕緣體13b相同之絕緣材料形成之一絕緣體。因此，絕緣體13c例如係一dTEOS膜。絕緣體13c之厚度例如為0.5 μm至1.5 μm。絕緣體13c係一第三膜之一實例。
該方法包含隨後藉由CMP平坦化絕緣體13c及13b之上表面(見圖8A)。結果，絕緣體13c之突出被消除，且絕緣體13b之突出部分T1自絕緣體13c曝露。如自圖8A所理解的，絕緣體13b及13c消除了以上提及之位準差。注意，邊緣部分B1上方之層間介電質13之上表面與中心部分A1上方之層間介電質13之上表面具有相同之高度。
該方法包含隨後在層間介電質13中之通孔插頭42上形成金屬墊41 (見圖8B)。本發明實施例之金屬墊41形成於絕緣體13c中。以此方式，製造了本發明實施例之陣列晶圓W1。
圖9係繪示製造第一實施例之電路晶圓W2之一方法之一橫截面圖。
與陣列晶圓W1類似，本發明實施例之電路晶圓W2可藉由自圖5A至圖8B之程序來製造。圖9繪示以此方式製造之電路晶圓W2。
圖9繪示基板15、作為層間介電質14之一部分之一絕緣體14a、形成於絕緣體14a中之電晶體31、閘極電極32、複數個接觸插頭33、線層36及複數個通孔插頭37。然而，未繪示接觸插頭33與線層36之間的線層34及線層35 (見圖3)。絕緣體14a係第一膜之一實例。圖9進一步繪示基板15之一中心部分A2、一邊緣部分B2及一最外部分C2。圖9進一步繪示作為層間介電質14之一部分之一絕緣體14b、作為層間介電質14之一部分之一絕緣體14c、絕緣體14b之一突出部分T2及形成於絕緣體14c中之複數個金屬墊38。絕緣體14b係第二膜之一實例，且絕緣體14c係第三膜之一實例。圖9中所繪示之基板15係在被切割之前的一半導體晶圓，且具有盤形狀。
圖9中所繪示之電路晶圓W2之相應組件之材料及形狀與陣列晶圓W1之組件之材料及形狀類似。例如，絕緣體14a、14b及14c分別對應絕緣體13a、13b及13c。進一步而言，基板15之中心部分A2、邊緣部分B2及最外部分C2分別對應基板16之中心部分A1、邊緣部分B1及最外部分C1。進一步而言，金屬墊38及通孔插頭37分別對應金屬墊41及通孔插頭42。關於此等組件之材料及形狀之實例，參考圖5A至圖8B中所繪示之程序之描述。
在本發明實施例中，絕緣體13b及13c消除了絕緣體13a之位準差，且邊緣部分B1下方之層間絕緣體13之下表面具有與中心部分A1下方之層間絕緣體13之下表面相同之高度(見圖8B)。類似地，絕緣體14b及14c消除了絕緣體14a之位準差，且邊緣部分B2上方之層間絕緣體14之上表面具有與中心部分A2上方之層間絕緣體14之上表面相同之高度(見圖9)。
因此，如下文將描述之圖11所繪示，本發明實施例之層間介電質13與層間介電質14接合在一起，使得基板16之整個中心部分A1與基板15之整個中心部分A2彼此接觸。如上所述，根據本發明實施例，可減少層間介電質13及14之未接合區域，且可增加陣列晶圓W1及電路晶圓W2之有效晶圓區域。此使得能夠抑制對陣列晶圓W1及電路晶圓W2之修整部分之浪費處置，且減少對基板16及15之邊緣部分B1及B2之浪費處置。
圖10及圖11係繪示第一實施例之半導體裝置之製造方法之橫截面圖。
與圖4類似，圖10繪示將陣列晶圓W1與電路晶圓W2接合在一起之一程序。因此，圖10所繪示之陣列晶圓W1之定向與圖5A至圖8B所繪示之陣列晶圓W1之定向相反。因此，在圖10中，基板16之邊緣部分B1之上表面高於基板16之中心部分A1之上表面。
在本發明實施例中，絕緣體13b及13c消除了絕緣體13a之位準差，且邊緣部分B1下方之層間絕緣體13之下表面具有與中心部分A1下方之層間絕緣體13之下表面相同之高度。類似地，絕緣體14b及14c消除了絕緣體14a之位準差，且邊緣部分B2上方之層間絕緣體14之上表面具有與中心部分A2上方之層間絕緣體14之上表面相同之高度。
因此，本發明實施例之層間介電質13與層間介電質14接合在一起，以便不僅在基板16之中心部分A1與基板15之中心部分A2之間彼此接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間彼此接觸。如上文所提及，根據本發明實施例，可減小層間介電質13及14之未接合區域且增加陣列晶圓W1及電路晶圓W2之有效晶圓區域。此使得能夠抑制對陣列晶圓W1及電路晶圓W2之修整部分之浪費處置，且減少對基板16及15之邊緣部分B1及B2之浪費處置。
圖10繪示接合在一起之金屬墊38及41。本發明實施例之金屬墊38及41提供於基板16之中心部分A1與基板15之中心部分A2之間，而不提供於基板16之邊緣部分B1與基板15之邊緣部分B2之間。增大中心部分A1及A2之比例並減小邊緣部分B1及B2之比例可增大陣列晶圓W1及電路晶圓W2之有效晶圓區域。如上文所提及，隨後對圖10所繪示之陣列晶圓W1及電路晶圓W2進行圖11所繪示之修整並將其切割為複數個晶圓。
圖11繪示修整後之陣列晶圓W1及電路晶圓W2。在本發明實施例中，執行修整以移除基板16及15之邊緣部分B1與B2之間的層間介電質13及14。此時，藉由修整移除基板16之邊緣部分B1及基板15之邊緣部分B2之一部分。
圖11繪示經修整層間介電質13之一邊緣面D1、經修整層間介電質14之一邊緣面D2及經修整基板16之一邊緣面D3。邊緣面D1、D2及D3分別係藉由在層間介電質13、層間介電質14及基板16上進行修整來形成之修整面。由於層間介電質13、層間介電質14及基板16係在相同之修整程序中被修整，因此邊緣面D1豎直地延伸至邊緣面D2上方並與邊緣面D2相連，且邊緣面D3豎直地延伸至邊緣面D1上方並與邊緣面D1相連。本發明實施例之層間介電質13及層間介電質14在層間介電質13之邊緣面D1與層間介電質14之邊緣面D2之間彼此連接。
如上文所提及，本發明實施例之層間介電質13與層間介電質14接合在一起，以便不僅在基板16之中心部分A1與基板15之中心部分A2之間彼此接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間彼此接觸(見圖10)。因此，在本發明實施例中，藉由幾乎僅修整邊緣部分B1與B2之間的層間介電質13及14，可移除所有未接合區域。此使得能夠抑制對許多修整部分之浪費處置。在圖11中，幾乎僅修整並移除中心部分A1與A2之間及邊緣部分B1與B2之間的層間介電質13及14之邊緣部分B1與B2之間的層間介電質13及14。如上文所提及，隨後將圖11中所繪示之陣列晶圓W1及電路晶圓W2切割為複數個晶圓。此時，丟棄修整部分之下之基板15 (基本上係基板15之邊緣部分B2)。在本發明實施例之修整中，中心部分A1及A2上之層間介電質13及14可被部分地移除，或邊緣部分B1及B2上之層間介電質13及14可被部分地留下。
如上文所提及，本發明實施例之層間介電質13及層間介電質14不僅在基板16之中心部分A1與基板15之中心部分A2之間彼此接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間彼此接觸，如圖10所繪示。因此，根據本發明實施例，可減少對基板16及15之邊緣部分B1及B2或其類似者之浪費處置。例如，在本發明實施例中，藉由修整移除之層間介電質13及14可幾乎僅限於邊緣部分B1與B2之間的層間介電質13及14，且在修整之後，中心部分A1與A2之間的層間介電質13及14可幾乎被留下。進一步而言，根據本發明實施例，要藉由修整來移除之基板16可幾乎僅限於基板16之邊緣部分B1，且基板16之中心部分A1可在修整之後幾乎被留下。在此情況下，由於修整來丟棄之基板15可幾乎僅限於基板15之邊緣部分B2。 (第二實施例)
在下文中，將參考圖12A至圖23描述製造第二實施例之半導體裝置之一方法。在執行圖3及圖4所繪示之方法時，圖12A至圖23所繪示之方法採用與圖5A至圖11所繪示之方法之程序不同之程序。
圖12A至圖21B係繪示製造第二實施例之一陣列晶圓W1 (及一電路晶圓W2)之一方法之橫截面圖。
該方法包含：首先，在基板16上形成一堆疊膜61，以形成記憶體單元陣列11之一部分(見圖12A)。堆疊膜61包含在基板16上交替地形成之複數個絕緣層51及複數個絕緣層57，且形成一覆蓋絕緣體58以覆蓋絕緣層51及絕緣層57之表面。絕緣層51例如係氧化矽膜。絕緣層57例如係氮化矽膜。覆蓋絕緣體58例如係氧化矽膜。絕緣層51係一第一絕緣層之一實例，絕緣層57係一第二絕緣層之一實例。該方法包含隨後形成穿透堆疊膜61之一周邊孔H1 (見圖12A)。未繪示基板16上之絕緣體12及源極層SL (見圖3)。
圖12A所繪示之基板16係在被切割之前的一半導體晶圓，且具有一盤形狀。與圖5A類似，圖12A進一步繪示基板16之一中心部分A1、一邊緣部分B1及一最外部分C1。中心部分A1係基板16之中心軸側上之一區域，且邊緣部分B1係基板16之最外部分C1側上之一區域。本發明實施例之邊緣部分B1具有環繞中心部分A1之一環形(環狀)形狀。甚至在本發明實施例中，基板16之邊緣部分B1之上表面可低於基板16之中心部分A1之上表面。
堆疊膜61例如係藉由以下方法形成。該方法包含：首先，在基板16上交替地形成複數個絕緣層51及複數個絕緣層57。該方法包含隨後將絕緣層51及絕緣層57部分地加工成一階梯形狀，如圖12A所繪示。圖12A繪示在邊緣部分B1附近傾斜之絕緣層51及絕緣層57之表面。該方法包含隨後在絕緣層51及絕緣層57上形成覆蓋絕緣體58。隨後，在邊緣部分B1附近之堆疊膜61中形成周邊孔H1。堆疊膜61之厚度例如約為3 μm。堆疊膜61係一第一堆疊膜之一實例。
該方法包含隨後經由堆疊膜61在基板16上形成作為層間介電質13之一部分之絕緣體13d (見圖12B)。絕緣體13d例如係一dTEOS膜。形成本發明實施例之絕緣體13d，使得周邊孔H1被絕緣體13d填充。進一步而言，本發明實施例之絕緣體13d不僅形成於中心部分A1上，而且形成於邊緣部分B1上。
該方法包含隨後藉由微影及蝕刻在周邊孔H1上方之絕緣體13d上形成光阻膜62 (見圖13A)。
該方法包含隨後藉由微影及蝕刻在邊緣部分B1上方之絕緣體13d上形成一光阻膜63 (見圖13B)。本發明實施例之光阻膜63亦形成於邊緣部分B1附近之中心部分A1上方之絕緣體13d上。如圖13B所繪示，光阻膜63覆蓋堆疊膜61之階梯部分。
該方法包含隨後藉由使用光阻膜62及63作為遮罩進行蝕刻來移除絕緣體13d之一部分(見圖14A)。結果，絕緣體13d保持於周邊孔H1中、周邊孔H1附近、邊緣部分B1上及邊緣部分B1附近之中心部分A1上。該方法包含隨後移除光阻膜62及63 (見圖14A)。
該方法包含隨後藉由CMP平坦化絕緣體13d之表面(見圖14B)。結果，移除了留在周邊孔H1附近之絕緣體13d。注意，在本發明實施例中，絕緣體13d保持於邊緣部分B1上。
該方法包含隨後執行圖15A至圖17B中所繪示之與圖12A至圖14B中所繪示之程序類似之程序。
該方法包含：首先，經由堆疊膜61及絕緣體13d在基板16上形成一堆疊膜64，以形成記憶體單元陣列11之另一部分(見圖15A)。與堆疊膜61類似，堆疊膜64包含交替地形成於基板16上之複數個絕緣層51及複數個絕緣層57及形成為覆蓋絕緣層51及絕緣層57之表面之一覆蓋絕緣體58。該方法包含隨後形成穿透堆疊膜64之周邊孔H2 (見圖15A)。周邊孔H2形成於周邊孔H1上。
堆疊膜64例如係藉由以下方法形成。該方法包含：首先，在基板16上交替地形成複數個絕緣層51及複數個絕緣層57。該方法包含隨後將絕緣層51及絕緣層57部分地加工成一階梯形狀，如圖15A所繪示。圖15A繪示在邊緣部分B1附近傾斜之絕緣層51及絕緣層57之表面。該方法包含隨後在絕緣層51及絕緣層57上形成覆蓋絕緣體58。隨後，在邊緣部分B1附近之疊層膜64中形成周邊孔H2。堆疊膜64之厚度例如約為3 μm。堆疊膜64係一第二堆疊膜之一實例。
在本發明實施例中，與堆疊膜61之階梯部分之尖端相比，堆疊膜64之階梯部分之尖端位元於基板16之中心軸側。換言之，在圖15A中，堆疊膜64之階梯部分之右端位元於堆疊膜61之階梯部分之右端之左側。本發明實施例之堆疊膜61及64形成為具有此等形狀。
該方法包含隨後經由堆疊膜61及64及絕緣體13d在基板16上形成一絕緣體13e，絕緣體13e係層間介電質13之另一部分(見圖15B)。絕緣體13e例如係一dTEOS膜。形成本發明實施例之絕緣體13e，使得周邊孔H2被絕緣體13e填充。進一步而言，本發明實施例之絕緣體13e不僅形成於中心部分A1上，而且形成於邊緣部分B1上。
該方法包含隨後藉由微影及蝕刻在周邊孔H2上方之絕緣體13e上形成一光阻膜65 (見圖16A)。
該方法包含隨後藉由微影及蝕刻在邊緣部分B1上方之絕緣體13e上形成一光阻膜66 (見圖16B)。本發明實施例之光阻膜66亦形成於邊緣部分B1附近之中心部分A1上方之絕緣體13e上。如圖16B所繪示，光阻膜66覆蓋堆疊膜64之階梯部分。
該方法包含隨後藉由使用光阻膜65及66作為一遮罩進行蝕刻來移除絕緣體13e之一部分(見圖17A)。結果，絕緣體13e保持於周邊孔H2中、周邊孔H2附近、邊緣部分B1上及邊緣部分B1附近之中心部分A1上。該方法包含隨後移除光阻膜65及66 (見圖17A)。
該方法包含隨後藉由CMP平坦化絕緣體13e之表面(見圖17B)。結果，移除了留在周邊孔H2附近之絕緣體13e。注意，在本發明實施例中，絕緣體13e保持於邊緣部分B1上。進一步而言，注意，在本發明實施例中，絕緣體13d之一部分插置於堆疊膜61之階梯部分與堆疊膜64之階梯部分之間。
該方法包含隨後執行用於用字線WL替換絕緣層57之部分之一替換程序(見圖18A)。例如，藉由以下方法執行替換程序。該方法包含：首先，形成穿透堆疊膜61及64之狹縫(未繪示)，並藉由使用此等狹縫進行濕蝕刻來移除絕緣層57。結果，在彼此相鄰之絕緣層51之間形成了空腔。該方法包含隨後用字線WL之材料填充空腔。結果，堆疊膜61及64經改變以包含交替地排列之複數個絕緣層51及複數個字線WL。然而，當移除絕緣層57時，圖18A所繪示之階梯部分之絕緣層57保持不變，但移除了除圖18A所繪示之階梯部分以外之絕緣層57。因此，圖18A所繪示之階梯部分仍包含交替地配置之複數個絕緣層51及複數個絕緣層57。由於以此方式藉由部分地移除絕緣層57來形成字線WL，因此形成之字線WL具有與剩餘絕緣層57相同之高度。字線WL係電極層之一實例。
該方法包含隨後在周邊孔H1及H2中之絕緣體13d及13e中形成通孔插頭45，且在包含字線WL之堆疊膜61及64中形成柱狀部分CL (見圖18A)。
該方法包含隨後經由堆疊膜61及64及絕緣體13d及13e在基板16上形成一絕緣體13f，該絕緣體13f係層間絕緣體13之另一部分(見圖18A)。絕緣體13f例如係一dTEOS膜。本發明實施例之絕緣體13f不僅形成於中心部分A1上，而且形成於邊緣部分B1上。
該方法包含隨後在絕緣體13f中形成複數個通孔插頭42 (見圖18A)。圖18A示範性地繪示經由線層44及43電連接至通孔插頭45之一個通孔插頭42及經由線層44及43電連接至柱狀部分CL之另一通孔插頭42。在本發明實施例中，在形成此等通孔插頭42之前形成線層44及43。柱狀部分CL與通孔插頭42之間的線層44對應位元線BL。未繪示柱狀部分CL與線層43之間的通孔插頭24 (見圖3)。
該方法包含隨後在絕緣體13f上形成一絕緣體13g，該絕緣體13g係層間介電質13之另一部分，以便覆蓋此等通孔插頭42 (見圖18B)。絕緣體13g例如係一dTEOS膜。本發明實施例之絕緣體13g不僅形成於中心部分A1上，而且形成於邊緣部分B1上。
該方法包含隨後藉由微影及蝕刻在邊緣部分B1上方之絕緣體13g上形成一光阻膜67 (見圖19A)。本發明實施例之光阻膜67亦形成於邊緣部分B1附近之中心部分A1上方之絕緣體13g上。如圖19A所繪示，光阻膜66覆蓋堆疊膜64之階梯部分上方之絕緣體13g。
該方法包含隨後藉由使用光阻膜67作為遮罩進行蝕刻來移除絕緣體13g之一部分(見圖19B)。結果，絕緣體13g保持於邊緣部分B1上，且保持於邊緣部分B1附近之中心部分A1上。圖19B繪示自絕緣體13g曝露之通孔插頭42。
該方法包含隨後移除光阻膜67，接著在絕緣體13f及13g上形成絕緣體13h，該絕緣體13h係層間絕緣體13之另一部分，以便覆蓋此等通孔插頭42 (見圖20A)。絕緣體13h例如係一dTEOS膜。本發明實施例之絕緣體13h不僅形成於中心部分A1上，而且形成於邊緣部分B1上。本發明實施例之絕緣體13h之厚度與絕緣體13g之厚度基本上相同。圖20A繪示在直接形成於絕緣體13f之上表面上之絕緣體13h與直接形成於絕緣體13g之上表面上之絕緣體13h之間形成之位準不同之一部分。
該方法包含隨後藉由CMP平坦化絕緣體13h之表面(見圖20B)。結果，直接形成於絕緣體13g之上表面上之絕緣體13h在位準不同之部分附近被部分地移除。注意，在本發明實施例中，絕緣體13g及其類似者保持於邊緣部分B1上。進一步而言，注意在圖20B中，邊緣部分B1上方之層間介電質13之上表面具有與中心部分A1上方之層間介電質13之上表面相同之高度。
該方法包含隨後在絕緣體13h中之通孔插頭42上形成金屬墊41 (見圖21A)。以此方式，製造了本發明實施例之陣列晶圓W1。
圖21B繪示本發明實施例之電路晶圓W2。圖21B繪示一基板15、一層間介電質14、在層間介電質14中形成之一電晶體31、一閘極電極32、複數個接觸插頭33、線層34、35及36、複數個通孔插頭37及複數個金屬墊38。圖21B進一步繪示基板15之一中心部分A2、一邊緣部分B2及一最外部分C2，如圖9。中心部分A2係基板15之中心軸側上之一區域，且邊緣部分B2係基板15之最外部分C2側上之一區域。本發明實施例之邊緣部分B2具有環繞中心部分A2之一環形(環狀)形狀。甚至在此實施例中，基板15之邊緣部分B2之上表面可低於基板15之中心部分A2之上表面。圖21B中所繪示之基板15係在被切割之前的半導體晶圓，且具有一盤形狀。
本發明實施例之電路晶圓W2可藉由任何方法來製造，但可藉由例如參考圖9描述之程序來製造。此使得能夠將邊緣部分B2上方之層間介電質14之上表面設置為與中心部分A2上方之層間介電質14之上表面具有相同之高度。
與第一實施例一樣，本發明實施例之層間介電質13與層間介電質14接合在一起，使得基板16之整個中心部分A1與基板15之整個中心部分A2彼此接觸(見下文將描述之圖22)。如上所述，根據本發明實施例，可減少層間介電質13及14之未接合區域，且可增加陣列晶圓W1及電路晶圓W2之有效晶圓區域。此使得能夠抑制對陣列晶圓W1及電路晶圓W2之修整部分之浪費處置，且減少對基板16及15之邊緣部分B1及B2之浪費處置。
圖22及圖23係繪示製造第二實施例之半導體裝置之方法之橫截面圖。
與圖4類似，圖22繪示將陣列晶圓W1與電路晶圓W2接合在一起之一程序。因此，圖22所繪示之陣列晶圓W1之定向與圖12A至21A所繪示之陣列晶圓W1之定向相反。
與第一實施例一樣，本發明實施例之層間介電質13與層間介電質14接合在一起，以便不僅在基板16之中心部分A1與基板15之中心部分A2之間彼此接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間彼此接觸。如上文所提及，根據本發明實施例，可減少層間介電質13及14之未接合區域，且可增加陣列晶圓W1及電路晶圓W2之有效晶圓區域。此使得能夠抑制對陣列晶圓W1及電路晶圓W2之修整部分之浪費處置，且減少對基板16及15之邊緣部分B1及B2之浪費處置。
圖22繪示接合在一起之金屬墊38及41。本發明實施例之金屬墊38及41提供於基板16之中心部分A1與基板15之中心部分A2之間，而不提供於基板16之邊緣部分B1與基板15之邊緣部分B2之間。增大中心部分A1及A2之比例並減小邊緣部分B1及B2之比例可增大陣列晶圓W1及電路晶圓W2之有效晶圓區域。圖22所繪示之陣列晶圓W1及電路晶圓W2隨後進行圖23所繪示之修整，並如上文所提及而切割為複數個晶片。
圖23繪示修整後之陣列晶圓W1及電路晶圓W2。在本發明實施例中，執行修整以移除基板16及15之邊緣部分B1與B2之間的層間介電質13及14。此時，藉由修整移除基板16之邊緣部分B1及基板15之邊緣部分B2之一部分。
圖23繪示經修整層間介電質13之一邊緣面D1、經修整層間介電質14之一邊緣面D2及經修整基板16之邊緣面D3。邊緣面D1、D2及D3分別係藉由在層間介電質13、層間介電質14及基板16上進行修整來形成之修整面。由於層間介電質13、層間介電質14及基板16係在相同之修整程序中被修整，因此邊緣面D1豎直地延伸至邊緣面D2上方並與邊緣面D2相連，且邊緣面D3豎直地延伸至邊緣面D1上方並與邊緣面D1相連。本發明實施例之層間介電質13及層間介電質14在層間介電質13之邊緣面D1與層間介電質14之邊緣面D2之間彼此連接。
如上文所提及，本發明實施例之層間介電質13與層間介電質14接合在一起，以便不僅在基板16之中心部分A1與基板15之中心部分A2之間接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間接觸(見圖22)。因此，在本發明實施例中，藉由幾乎僅修整邊緣部分B1與B2之間的層間介電質13及14，可移除所有未接合區域。此使得能夠抑制對許多修整部分之浪費處置。在圖23中，幾乎僅修整並移除中心部分A1與A2之間及邊緣部分B1與B2之間的層間介電質13及14之邊緣部分B1與B2之間的層間介電質13及14。如上文所提及，隨後將圖23所繪示之陣列晶圓W1及電路晶圓W2切割為複數個晶圓。此時，丟棄修整部分下之基板15 (基本上係基板15之邊緣部分B2)。在本發明實施例之修整中，中心部分A1及A2上之層間介電質13及14可被部分地移除，或邊緣部分B1及B2上之層間介電質13及14可被部分地留下。
包含本發明實施例之邊緣面D1及D2之修整面(見圖23)在堆疊膜64之階梯部分之尖端附近藉由。因此，在本發明實施例之修整中，移除堆疊膜61之階梯部分之一尖端側部分，且堆疊膜61之剩餘階梯部分保持不變(見圖23)。另一方面，在本發明實施例之修整中，幾乎所有之堆疊膜64之階梯部分都保持不變(見圖23)。結果，圖23所繪示之層間介電質13在層間介電質13及14之邊緣面D1及D2處插置於層間介電質14與堆疊膜64 (階梯部分)之間。在圖23所繪示之層間介電質13之邊緣面D1上，絕緣體13d至13h存在於堆疊膜61之下，且絕緣體13e至13h存在於堆疊膜64之下。進一步而言，圖23所繪示之堆疊膜64 (階梯部分)經由層間介電質13之一部分安置於堆疊膜61 (階梯部分)之下。層間介電質13部分地插置於堆疊膜61與堆疊膜64之間。如上所述，在本發明實施例中，藉由減少修整部分，絕緣體13d至13h在修整之後幾乎保持不變。
如上文所提及，本發明實施例之層間介電質13及層間介電質14不僅在基板16之中心部分A1與基板15之中心部分A2之間彼此接觸，而且在基板16之邊緣部分B1與基板15之邊緣部分B2之間彼此接觸，如圖22所繪示。因此，根據本發明實施例，可減少對基板16及15之邊緣部分B1及B2之浪費處置。例如，根據本發明實施例，藉由修整移除之層間介電質13及14可幾乎僅限於邊緣部分B1與B2之間的層間介電質13及14，且在修整之後，中心部分A1與A2之間的層間介電質13及14可幾乎被留下。進一步而言，根據本發明實施例，要藉由修整來移除之基板16可幾乎僅限於基板16之邊緣部分B1，且基板16之中心部分A1可在修整之後幾乎被留下。在此情況下，由於修整來丟棄之基板15可幾乎僅限於基板15之邊緣部分B2。
進一步而言，本發明實施例之層間介電質13及14在如下之一位置被修整：在該位置，層間介電質13在層間介電質13及14之邊緣面D1及D2處插置於層間介電質14與堆疊膜64之間。因此，根據本發明實施例，層間介電質13及14之邊緣面D1及D2可靠近基板15及16之最外部分C1及C2安置，且可減少對基板16及15之邊緣部分B1及B2之浪費處置。
雖然已經描述了某些實施例，但此等實施例僅以實例之方式呈現，且不意欲限制本發明之範疇。實際上，本文所描述之新穎晶圓及方法可以各種其他形式來體現；此外，在不脫離本發明之精神之情況下，可對本文所描述之晶圓及方法之形式進行各種省略、代替及改變。隨附發明申請專利範圍及其等效物意欲涵蓋屬於本發明之範疇及精神之此等形式或修改。 相關申請案之交叉參考
本申請案係基於2020年3月23日申請之先前日本專利申請案第2020-051539號及2020年9月2日申請之先前美國專利申請案第17/010,196號且主張該等案之優先權權利，該等案之全部內容以引用方式併入本文中。
1:陣列晶片 2:電路晶片 11:記憶體單元陣列 12:絕緣體 13:層間介電質 13a:絕緣體 13b:絕緣體 13c:絕緣體 13d:絕緣體 13e:絕緣體 13f:絕緣體 13g:絕緣體 13h:絕緣體 14:層間介電質 14a:絕緣體 14b:絕緣體 14c:絕緣體 15:基板 16:基板 17:光阻膜 21:階梯結構部分 22:接觸插頭 23:字線層 24:通孔插頭 31:電晶體 32:閘極電極 33:接觸插頭 34:線層 35:線層 36:線層 37:通孔插頭 38:金屬墊 41:金屬墊 42:通孔插頭 43:線層 44:線層 45:通孔插頭 46:金屬墊 47:鈍化膜 51:絕緣層 52:塊絕緣體 53:電荷儲存層 54:隧道絕緣體 55:通道半導體層 56:核心絕緣體 57:絕緣層 58:覆蓋絕緣體 61:堆疊膜 62:光阻膜 63:光阻膜 64:堆疊膜 65:光阻膜 66:光阻膜 67:光阻膜 A1:中心部分 A2:中心部分 B1:邊緣部分 B2:邊緣部分 BL:位元線 C1:最外部分 C2:最外部分 CL:柱狀部分 D1:邊緣面 D2:邊緣面 D3:邊緣面 H1:周邊孔 H2:周邊孔 P:孔 S:接合面 S1:陣列晶圓W1之上表面 S2:電路晶圓W2之上表面 SL:源線 SL1:初級層 SL2:次級層 T1:突出部分 T2:突出部分 W1:陣列晶圓 W2:電路晶圓 WL:字線
圖1係繪示一第一實施例之一半導體裝置之結構之一橫截面圖；
圖2係繪示第一實施例之一柱狀部分CL之結構之一橫截面圖；
圖3及圖4係繪示製造第一實施例之半導體裝置之一方法之橫截面圖；
圖5A至圖8B係繪示製造第一實施例之一陣列晶圓W1之一方法之橫截面圖；
圖9係繪示製造第一實施例之一電路晶圓W2之一方法之一橫截面圖；
圖10及圖11係繪示製造第一實施例之半導體裝置之方法之橫截面圖；
圖12A至圖20B係繪示製造一第二實施例之陣列晶圓W1之一方法之橫截面圖；
圖21A及圖21B係繪示製造第二實施例之陣列晶圓W1及電路晶圓W2之一方法之橫截面圖；及
圖22及圖23係繪示製造第二實施例之半導體裝置之一方法之橫截面圖。
13:層間介電質
13d:絕緣體
13e:絕緣體
13f:絕緣體
13g:絕緣體
13h:絕緣體
14:層間介電質
15:基板
16:基板
31:電晶體
32:閘極電極
33:接觸插頭
34:線層
35:線層
36:線層
37:通孔插頭
38:金屬墊
41:金屬墊
42:通孔插頭
43:線層
44:線層
45:通孔插頭
51:絕緣層
57:絕緣層
58:覆蓋絕緣體
61:堆疊膜
64:堆疊膜
A1:中心部分
A2:中心部分
B2:邊緣部分
BL:位元線
C2:最外部分
CL:柱狀部分
D1:邊緣面
D2:邊緣面
D3:邊緣面
W1:陣列晶圓
W2:電路晶圓
WL:字線

Claims (20)

  1. 一種半導體晶圓，其包括：第一晶圓，其包含：一第一基板；及一第一絕緣體，其提供(provided)於該第一基板上；第二晶圓，其接合於該第一晶圓，且包含：一第二絕緣體，其提供於該第一絕緣體上；及一堆疊膜，其交替地包含：複數個第一絕緣層及複數個第二絕緣層，其提供於該第二絕緣體中；及複數個墊，其提供於該第一晶圓與該第二晶圓之接合面；其中該半導體晶圓包括：複數個晶片單元，其等之各者包含陣列晶片及電路晶片，該陣列晶片包含記憶體單元陣列，該電路晶片包含複數個電晶體；該複數個電晶體經由該複數個墊而電性連接於該記憶體單元陣列，該第一絕緣體及該第二絕緣體在該第一絕緣體及該第二絕緣體之晶圓邊緣面(wafer-edge face)處彼此連接，且該第二絕緣體在該第一絕緣體及該第二絕緣體之該等晶圓邊緣面處配置於該第一絕緣體與該堆疊膜之間。
  2. 如請求項1之半導體晶圓，其中該第一絕緣體之該晶圓邊緣面及該第二絕緣體之該晶圓邊緣面係該第一絕緣體之一修整面及該第二絕緣體之一 修整面。
  3. 如請求項1之半導體晶圓，其中該堆疊膜包含：一第一堆疊膜，其交替地包含該等第一絕緣層及該等第二絕緣層；及一第二堆疊膜，其交替地包含該等第一絕緣層及該等第二絕緣層，且經由該第二絕緣體之一部分提供於該第一堆疊膜之下。
  4. 如請求項1之半導體晶圓，其進一步包括提供與該複數個該等第二絕緣層之高度相同之高度處之複數個電極層。
  5. 如請求項1之半導體晶圓，其中該第二晶圓包含一第二基板，該第二基板之一邊緣面提供於該第二絕緣體之該晶圓邊緣面上。
  6. 如請求項5之半導體晶圓，其中該第二基板之該邊緣面係該第二基板之一修整面。
  7. 如請求項1之半導體晶圓，其中該記憶體單元陣列提供於該第一基板上方之該第二絕緣體中，且電連接至包括於上述複數個墊中之一第二墊；且該半導體晶圓進一步包括：一控制電路，其提供於該第一基板上之該第一絕緣體中，電連接至包括於上述複數個墊中之一第一墊，且經組態以控制該記憶體單元陣列。
  8. 如請求項1之半導體晶圓，其中該第一絕緣層包含矽及氧，且該第二絕緣層包含矽及氮。
  9. 一種半導體晶圓製造方法，其包括：在一第一晶圓包含之一第一基板上形成一第一絕緣體；在一第二晶圓中形成交替地包含複數個第一絕緣層及複數個第二絕緣層之一堆疊膜及一第二絕緣體；在該第一晶圓及該第二晶圓之接合面，形成複數個墊；將該第一晶圓及該第二晶圓接合；及修整該第一絕緣體及該第二絕緣體，使得該第一絕緣體及該第二絕緣體在該第一絕緣體之一晶圓邊緣面與該第二絕緣體之一晶圓邊緣面處彼此接觸，且該第一絕緣體及該第二絕緣體經修整使得該第二絕緣體在該第一絕緣體及該第二絕緣體之該等晶圓邊緣面處配置於該第一絕緣體與該堆疊膜之間。
  10. 如請求項9之半導體晶圓製造方法，其中該第一絕緣體及該第二絕緣體經修整使得該堆疊膜包含：一第一堆疊膜，其交替地包含該等第一絕緣層及該等第二絕緣層；及一第二堆疊膜，其交替地包含該等第一絕緣層及該等第二絕緣層，且經由該第二絕緣體之一部分提供於該第一堆疊膜之下。
  11. 如請求項9之半導體晶圓製造方法，其進一步包括用複數個電極層替換該複數個第二絕緣層之部分。
  12. 如請求項9之半導體晶圓製造方法，其中用該第一絕緣體及該第二絕緣體修整該第二晶圓所包含之第二基板。
  13. 如請求項9之半導體晶圓製造方法，其進一步包括：在該接合之前在該第二晶圓所包含之第二基板上形成一記憶體單元陣列；及在該接合之前在該第一基板上形成經組態以控制該記憶體單元陣列之一控制電路。
  14. 如請求項9之半導體晶圓製造方法，其中該第一絕緣層包含矽及氧，且該第二絕緣層包含矽及氮。
  15. 一種半導體晶圓製造方法，其包括：在一第一基板上形成一第一絕緣體，其中一邊緣部分之一上表面低於一中心部分之一上表面；在該第一絕緣體中形成複數個第一墊；在一第二基板上形成一第二絕緣體，其中一邊緣部分之一上表面低於一中心部分之一上表面；在該第二絕緣體中形成複數個第二墊； 藉由將形成於該第一基板上之該等第一墊及該第一絕緣體分別接合至形成於該第二基板上之該等第二墊及該第二絕緣體來將該等第二墊及該第二絕緣體分別安置於該等第一墊及該第一絕緣體上；及修整該第一絕緣體及該第二絕緣體，其中該第一絕緣體及該第二絕緣體經接合以便在該第一基板之該邊緣部分與該第二基板之該邊緣部分之間彼此接觸，且該第一絕緣體及該第二絕緣體經修整使得該第一絕緣體及該第二絕緣體在該第一絕緣體之一邊緣面與該第二絕緣體之一邊緣面之間彼此接觸。
  16. 如請求項15之半導體晶圓製造方法，其中該第一絕緣體及該第二絕緣體之各者係藉由以下操作來形成：在該第一基板或該第二基板之該中心部分及該邊緣部分上形成一第一膜，使得該第一基板或該第二基板之該中心部分與該邊緣部分之間存在一位準差；在該第一基板或該第二基板之該中心部分及該邊緣部分上形成一第二膜；移除該第一基板或該第二基板之該中心部分上之該第二膜之一部分，使得該第二膜之一突出部分保持於該第一基板或該第二基板之該中心部分與該邊緣部分之間的一邊界附近；在該第一基板或該第二基板之該中心部分及該邊緣部分上形成一第三膜；及 平坦化該第二膜及該第三膜之上表面。
  17. 如請求項16之半導體晶圓製造方法，其中該第二膜及該第三膜由一相同材料形成。
  18. 如請求項16之半導體晶圓製造方法，其中該等第一墊及該等第二墊之各者形成於該第三膜中。
  19. 如請求項16之半導體晶圓製造方法，其中該等第一墊及該等第二墊安置於該第一基板之該中心部分及該第二基板之該中心部分上方，且不安置於該第一基板之該邊緣部分及該第二基板之該邊緣部分上方。
  20. 如請求項16之半導體晶圓製造方法，其中用該第一絕緣體及該第二絕緣體修整該第二基板。
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