TWI792260B - 利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件 - Google Patents

利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件 Download PDF

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TWI792260B
TWI792260B TW110113002A TW110113002A TWI792260B TW I792260 B TWI792260 B TW I792260B TW 110113002 A TW110113002 A TW 110113002A TW 110113002 A TW110113002 A TW 110113002A TW I792260 B TWI792260 B TW I792260B
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photoresist
metal
manufacturing
lift
semiconductor element
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TW110113002A
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TW202240322A (zh
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鄒政興
趙大翔
胡榮森
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晶瑞光電股份有限公司
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Priority to TW110113002A priority Critical patent/TWI792260B/zh
Priority to JP2021131936A priority patent/JP2022161792A/ja
Priority to US17/401,877 priority patent/US20220328312A1/en
Priority to DE102021121082.8A priority patent/DE102021121082A1/de
Priority to CN202110931375.XA priority patent/CN115206779A/zh
Priority to KR1020210107118A priority patent/KR20220140394A/ko
Publication of TW202240322A publication Critical patent/TW202240322A/zh
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

一種利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件，透過光阻塗佈、曝光、顯影、再鍍上金屬層，並利用光阻去除液去除光阻層，在去除光阻層時會將光阻層頂部的金屬剝離，係可不需蝕刻製程，即可完成半導體元件所需之電路佈設；此外，透過製程參數安排，讓光阻層的輪廓呈現特定角度，使光阻層表面的金屬可被完全剝離，達到節省成本，有效提升競爭優勢之功效。

Description

利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件
本發明應用於半導體元件之製造，尤指一種透過簡化並改善製程，以提升製造流程效率、節約成本與縮短製造時間、且不易造成金屬殘留、也不易破壞底材表面之利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件。
一般在製造半導體元件時，經常需要利用蝕刻(Etch)方式來作為移除金屬的製程，以此佈設出所需的電路，請參閱「第1圖」，其為利用蝕刻製程流程示意圖，習知蝕刻製程依序為: (1)金屬鍍膜:在一基板S表面先鍍上一金屬層M； (2)光阻塗佈:塗佈一光阻P於金屬層M表面； (3)曝光:透過一光源及一光罩曝光光阻P； (4)顯影:以一顯影液將未曝光之光阻P去除，使金屬層M表面成型有圖案的一光阻層P’； (5)蝕刻:利用蝕刻液將未被光阻層P’覆蓋之金屬層M去除； (6)剝膜:將光阻層P’由金屬層M表面剝離，使基板S表面留下之金屬層形成電路。
一般在製造半導體元件時，係採用蝕刻的方式將不需要保留的金屬區域移除，只留下需要保留的金屬區域以形成電路；但是為了要能達到能把金屬都蝕刻乾淨以及不可有金屬殘留情況，需要搭配多種金屬蝕刻液(金屬蝕刻液種類包含HF，HNO3，H2O2，KOH，NH4OH，H2SO4，DHF，H3PO4)，才能達到較佳的蝕刻效果。
然而使用蝕刻(etch)方式來移除金屬層的製程方式在實際實施時具有以下缺點: (1)  用蝕刻(Etch)的方式來移除濺鍍或蒸鍍製程所沉積下來的金屬層所需成本較高，原因是蝕刻機台費用昂貴，所搭配使用的金屬蝕刻液同時也是一項昂貴的費用成本； (2)  遇到如耐腐蝕的特殊金屬層，例如金屬膜層是比較耐腐蝕的金屬，則會有不易蝕刻的問題，因而造成金屬殘留情況，但為了提高金屬蝕刻液的效能，通常會以增加蝕刻液的濃度、或是延長浸泡時間來處理，但高濃度的蝕刻方式卻也可能破壞底材表面，造成良率上損失； (3)  因為多了蝕刻製程步驟流程，因此增加了較多生產的時間，同時也提高製作成本(如電費、工時、人力…等) 。
有鑑於上述的問題，本發明人係依據多年來從事相關製程的經驗，針對蝕刻製程進行研究及改進；緣此，本發明之主要目的在於提供一種利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件，供以解決用蝕刻(etch)製程所導致金屬殘留以及機台費用昂貴所導致製作成本較高的問題等諸多問題。
為達上述目的，本發明之利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件，主要係於一基板經過光阻塗佈、曝光、顯影等製程在基板的表面形成具圖樣的光阻層，並將此基板經過金屬鍍膜，再用光阻去除液(PR-Strip，成分為NMP和DMSO和glycol ethers)來去除光阻層，光阻去除液(PR-strip)在去除光阻層時，會同時將光阻層頂部的金屬剝離；此外，經由本發明之利用金屬掀離製程的半導體元件製造方法，將使光阻層的輪廓具有獨特的角度，使光阻層側面不易被金屬覆蓋，係不會造成金屬蝕刻不潔導致金屬殘留問題，如此便可捨棄用蝕刻(etch)方式去除金屬，省下昂貴的蝕刻機台費用，與蝕刻藥水費用，也使流程簡化，生產時間大幅降低，產能因此增加，致使公司的人力、電力、氣體等資源成本也會降低，大大提升競爭優勢。
為使 貴審查委員得以清楚了解本發明之目的、技術特徵及其實施後之功效，茲以下列說明搭配圖示進行說明，敬請參閱。
於此先予敘明，本發明所揭之製程中所應用之金屬掀離系統，係指至少包含有一中央控制模組，另有一塗佈模組、一曝光模組、一顯影模組、一鍍膜模組、及一掀離模組與中央控制模組資訊連接，以下例示各組成要件的功能: (1)中央控制模組供以運行金屬掀離系統，驅動上述各模組之作動，並可供操作者監控、操作調整金屬掀離系統，其具備邏輯運算、暫存運算結果、保存執行指令位置等功能，可以為中央處理器(Central Processing Unit，CPU)，但不以此為限； (2)塗佈模組供以將一基板塗佈一光阻(Photoresist)，其可選為旋轉塗佈機(SpinCoater)、噴塗機(Sprayer)等，凡能將光阻均勻塗佈於基板之設備皆可實施，並不以此為限；其中光阻可為正型光阻或負型光阻，可選的，塗佈模組在光阻塗佈完畢後，便可進行一軟烤作業； (3)曝光模組供以將一光阻以一曝光製程參數、一光源、及一具有圖樣之光罩將光阻進行曝光，進而在被一顯影液(Developer)沖洗後產生有不同圖樣效果之光阻層，如，負型光阻其未曝光的部分會溶於顯影液，而照到光的部份不會溶於光阻顯影液，係可根據需求，調整曝光條件；曝光模組可例如為對準式曝光機(aligner)、步進式曝光機（stepper）、掃描式曝光機（scanner）凡能達成圖樣解析度及曝光條件之設備皆可實施，並不以此為限，可選的，曝光模組供以進行一曝光後的烘烤作業； (4)顯影模組供以將已曝光完成之光阻以顯影液進行清洗，以使具有設計圖樣之光阻層顯現，其係可利用噴灑、浸泡、沖洗、超音波震盪等其中一種或其組合之方式作為利用顯影液清洗之方式，但不以此為限，可選的，顯影模組供以將顯影完畢之基板以去離子水(Deionized water)洗淨，去除殘餘在基板及光阻層上之顯影液，此外，便可供執行一硬烤作業； (5)鍍膜模組供以將成型有光阻層之基板，以物理氣象沉積法(Physical Vapor Deposition)與化學氣相沉積法(Chemical Vapor Deposition)在基板及光阻層表面鍍上一第一金屬層及一第二金屬層； (6)掀離模組供以利用光阻去除液(PR-Strip)將光阻層掀離去除，且在光阻層去除同時，係一併使附著於光阻層頂部之第一金屬層去除，僅留下附著於基板表面之第二金屬層，其中，光阻去除液係包含有N-甲基吡咯烷酮（NMP）、二甲基亞碸(DMSO)、及乙二醇醚(glycol ethers)等溶劑組合，但不以此為限。
請參閱「第2圖」，為本發明之方法流程示意圖，本發明之利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件步驟如下: (1)一光阻塗佈步驟S1:請搭配參閱「第3圖」，金屬掀離系統係將一光阻P均勻塗佈於一基板S，較佳的，光阻P為負型光阻，光阻P成分由樹脂(resin)、增感劑(sensitizer)、溶劑(solvent)組成，並藉由旋轉塗佈(Spin coating)方式進行塗佈，其旋轉轉數參數與塗膜厚度關係請參照「第4圖」，較佳的，塗佈厚度為1um~15um，進一步，在光阻P塗佈完畢後，便可進行溫度為70~120℃，持續時間為60~90秒的軟烤作業； (2)一曝光步驟S2:請搭配參閱「第5圖」，金屬掀離系統係將塗佈於基板S之光阻P以一曝光製程參數、一光源、及一具有圖樣之光罩進行曝光製程，以將光阻P成型為具有圖樣的光阻層P’，較佳的，負型光阻P係為被曝光之部分成型為光阻層P’，未被曝光部分保持光阻P狀態，其中，較佳的，曝光製程參數包含有使用對準式曝光機(aligner)且曝光模式為接觸式寬頻（Proximity broadband)350~450nm，或使用步進式曝光機（stepper）燈源可例如為 g-line、 h-line、i-line，搭配間隙為0~50um，曝光能量介於40~450mJ/cm 2之間，其曝光條件之曝光能量及光阻厚度百分比(Sensitivity curve)請搭配參照「第6圖」；較佳的，在曝光完成後，係可進行溫度為40~100℃，持續時間為60~90秒的曝光後烘烤作業； (3)一顯影步驟S3:請搭配參閱「第7圖」，金屬掀離系統係利用一顯影液，將塗佈於基板S之未曝光的光阻P進行清洗，顯影液可為包含有1~5wt%的四甲基氫氧化銨(TMAH)溶液，以此進行40~120秒清洗，可選的，並使用去離子水進行10~60秒的噴灑清洗，亦可進行溫度為100~250℃，持續時間為5~20分鐘的硬烤作業，沖洗完畢後之基板S表面係顯現具圖樣的光阻層P’； (4)一鍍膜步驟S4:請搭配參閱「第8圖」，金屬掀離系統係使用PVD（Physical Vapor Deposition）技術，使光阻層P’鍍上一第一金屬層M1，基板S鍍上一第二金屬層M2； (5)一掀離步驟S5:請搭配參閱「第9圖」，金屬掀離系統利用一光阻去除液(PR-Strip)將光阻層P’掀離去除，光阻層P’去除同時，係一併使附著於光阻層P’頂部之第一金屬層M1去除，僅留下附著於基板S表面之第二金屬層M2，所留下之第二金屬層M2即為半導體元件所欲佈設之電路，其中，光阻去除液係包含有N-甲基吡咯烷酮（NMP）、二甲基亞碸(DMSO)、及乙二醇醚(glycol ethers)等溶劑組合，但不以此為限。
請參閱「第3圖」、「第5圖」、及「第7圖」~「第9圖」，本發明之利用金屬掀離製程的半導體元件，係包含有一基板S及一第二金屬層M2，基板S表面塗佈有一光阻P，並利用一光源，經由具有一圖樣之一光罩，對塗佈於基板S表面的光阻P進行曝光，光阻P受光與未受光處係分別形成為光阻層P’與光阻P，其中，若光阻P為負型光阻，則受光處為光阻層P’，若光阻P為正型光阻，則未受光處為光阻層P’；利用一顯影液係可將光阻P洗淨，留下可顯現圖樣的基板S及光阻層P’，並將基板S及光阻層P’表面利用PVD或CVD製程鍍上金屬，其中，光阻P’表面係為第一金屬層M1，基板S表面係為第二金屬層M2，利用一光阻去除液將光阻層P’去除，此時，第一金屬層M1係連同光阻層P’一併去除，即可藉由去除光阻層P’使基板S表面之第二金屬層M2成形為電路。
請參閱「第10圖」及「第11圖」，為本發明之另一實施例，並請搭配參閱本發明之實施示意圖(一)~(五)，本發明之利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件，透過前述本發明之光阻塗佈步驟S1、曝光步驟S2、顯影步驟S3中之各製程參數相互搭配，係可使光阻層P’由上至下成型為漸縮樣態，如此在執行鍍膜步驟S4後，將不會如「第10圖」所示將光阻層P’完全覆蓋，而將如「第11圖」所示，金屬層(M1、M2)係不易覆蓋光阻層P’之側面，而只披覆在裸露的基板S及光阻層P’表面，較佳的，請搭配參閱「第12圖」，係使光阻層P’與基板S之間具有40度~100度之夾角，如此，在進行掀離步驟S5時，係可輕易將光阻層P’掀離，而不會因金屬層(M1、M2)披覆於側面，導致掀離困難進而造成金屬殘留，而需進行蝕刻(Etch)之製程；其中，較佳的請參照「第13圖」，為本發明之製程參數示例，其中，係以P型晶圓(p-silicon wafer)作為基板，塗佈光阻為負光阻，其成分由樹脂 (resin)，增感劑(sensitizer)，溶劑(solvent)組成，且塗佈厚度為1~15um，於塗佈完成後進行一溫度70~120℃，時間為60~90秒的軟烤，接續軟烤，曝光參數可例如Aligner proximity broadband:40~120mJ/cm 2、Stepper,搭配g-line, h-line, l-line之其中一種或其組合:120~200mJ/cm 2、或Stepper,搭配l-line only: 300~450mJ/cm 2、與gap:0~50um,25mW/cm 2，並於曝光後進行一溫度40~100℃，時間為60~90秒的烘烤，接續曝光，以2.38%wt四甲基氫氧化銨(TMAH)溶液清洗40~120秒顯影，再以去離子水(DIW)噴灑沖洗10~60秒作清洗後，以一溫度100~250℃，時間為5~20分鐘的硬烤，此製程參數僅為示例，並不以此為限制。
綜上可知，本發明之利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件，係將一基板依序進行光阻塗佈、曝光、顯影、鍍膜、及掀離步驟，即可利用光阻去除液將光阻層去除，如此，係可連同光阻層頂部之金屬層一併去除，使半導體元件電路佈設完成；此外，更透過製程參數安排，使光阻層由上至下呈一漸縮狀，與基板具有夾角，使在執行金屬鍍膜時，光阻層係不被金屬完全覆蓋，使光阻去除液可完整將光阻層掀離，如此便可不需借助蝕刻製程，仍可完成電路之佈設，據此，本發明據以實施後，確實可達到免去蝕刻製程，進而節省蝕刻所需成本，有效提升競爭優勢之功效。
以上所述者，僅為本發明之較佳之實施例而已，並非用以限定本發明實施之範圍；任何熟習此技藝者，在不脫離本發明之精神與範圍下所作之均等變化與修飾，皆應涵蓋於本發明之專利範圍內。
綜上所述，本發明係具有「產業利用性」、「新穎性」與「進步性」等專利要件；申請人爰依專利法之規定，向　鈞局提起發明專利之申請。
S1:光阻塗佈步驟 S2:曝光步驟 S3:顯影步驟 S4:鍍膜步驟 S5:掀離步驟 S:基板 P:光阻 P’:光阻層 M:金屬層 M1:第一金屬層 M2:第二金屬層
第1圖，為習知蝕刻製程流程示意圖。 第2圖，為本發明之方法流程示意圖。 第3圖，為本發明之實施示意圖(一)。 第4圖，為本發明之塗膜厚度與旋轉塗佈條件關係圖。 第5圖，為本發明之實施示意圖(二)。 第6圖，為本發明之光阻反應厚度與曝光能量關係圖。 第7圖，為本發明之實施示意圖(三)。 第8圖，為本發明之實施示意圖(四)。 第9圖，為本發明之實施示意圖(五)。 第10圖，為本發明之另一實施例(一)。 第11圖，為本發明之另一實施例(二)。 第12圖，為本發明之另一實施示意圖。 第13圖，為本發明之製程參數示例。
S1:光阻塗佈步驟
S2:曝光步驟
S3:顯影步驟
S4:鍍膜步驟
S5:掀離步驟

Claims (22)

  1. 一種利用金屬掀離製程的半導體元件製造方法，供以使一基板完成一電路的佈設，其包含：一光阻塗佈步驟，將一光阻塗佈於該基板；一曝光步驟，將該光阻以一光源、一光罩、及一曝光製程參數進行曝光，使該基板表面成型具有圖樣的一光阻層；一顯影步驟，利用一顯影液對曝光完成之該光阻進行清洗，使具有圖樣的該光阻層顯現，顯影完畢之該光阻層由上至下成型為一漸縮樣態，且該光阻層與該基板之一夾角為45度~80度；一鍍膜步驟，使該光阻層表面被鍍有一第一金屬層，且該基板表面被鍍一第二金屬層；以及一掀離步驟，以一光阻去除液對該光阻層進行掀離，達到使該第一金屬層連同該光阻層被掀離，使被留下的該第二金屬層形成該電路。
  2. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該光阻塗佈步驟中，該光阻為負型光阻。
  3. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該光阻塗佈步驟中，該光阻之塗佈厚度為1um~15um。
  4. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該光阻塗佈步驟中，包含有溫度為70℃~120℃搭配持續時間為60秒~90秒的一軟烤作業。
  5. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含一曝光波長範圍為寬頻350nm~450nm。
  6. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含使用對準式曝光機(aligner)、或步進式曝光機(stepper)之其中一種或其組合進行曝光。
  7. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含一燈源為g-line、h-line或i-line之其中一種或其組合。
  8. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含一曝光模式為接觸式。
  9. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含一間隙為0~50um。
  10. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光製程參數包含一曝光能量為40mJ/cm2~450mJ/cm2。
  11. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該曝光步驟中，該曝光步驟包含有溫度為40℃~100℃，持續時間為60秒~90秒的一烘烤作業。
  12. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該顯影步驟中，該顯影液為1wt%~5wt%的四甲基氫氧化銨溶液。
  13. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該顯影步驟中，該顯影液清洗時間為40秒~120秒。
  14. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該顯影步驟中，包含有在該顯影液清洗完畢後，使用去離子水噴灑清洗10秒~60秒。
  15. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該顯影步驟中，該顯影步驟包含有溫度為100℃~250℃，持續時間為5分鐘~20分鐘的一硬烤作業。
  16. 如請求項1所述之利用金屬掀離製程的半導體元件製造方法，其中，該掀離步驟中，該光阻去除液包含有N-甲基吡咯烷酮、二甲基亞碸、及乙二醇醚之組合。
  17. 一種利用金屬掀離製程的半導體元件製造方法所製成之半導體元件，透過由一光阻曝光而成的一光阻層，佈設有一電路，其包含：一基板； 該光阻，塗佈於該基板表面，被一光源經由具有圖樣之一光罩曝光，並由一顯影液將未反應之該光阻去除；該光阻層，藉由一光阻去除液掀離，該光阻層由上至下成型為一漸縮樣態，且該光阻層與該基板之一夾角為45度~80度；一第一金屬層，成形於該光阻層表面，與該光阻層被一同掀離；以及一第二金屬層，成形於該基板表面形成該電路。
  18. 如請求項17所述之利用金屬掀離製程的半導體元件，其中，該光阻為負型光阻。
  19. 如請求項17所述之利用金屬掀離製程的半導體元件，其中，該光阻成分包含有樹脂、增感劑、溶劑之組合。
  20. 如請求項17所述之利用金屬掀離製程的半導體元件，其中，該光阻塗佈厚度為1um~15um。
  21. 如請求項17所述之利用金屬掀離製程的半導體元件，其中，該顯影液為包含有1wt%~5wt%的四甲基氫氧化銨溶液。
  22. 如請求項17所述之利用金屬掀離製程的半導體元件，其中，該光阻去除液包含有N-甲基吡咯烷酮、二甲基亞碸、及乙二醇醚之組合。
TW110113002A 2021-04-09 2021-04-09 利用金屬掀離製程的半導體元件製造方法及其製成之半導體元件 TWI792260B (zh)

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JP2021131936A JP2022161792A (ja) 2021-04-09 2021-08-13 金属リフトオフプロセスを用いた半導体素子の製造方法及びこの方法により製造する半導体素子
US17/401,877 US20220328312A1 (en) 2021-04-09 2021-08-13 Method for manufacturing semiconductor elements by metal lift-off process and semiconductor element manufactured thereby
DE102021121082.8A DE102021121082A1 (de) 2021-04-09 2021-08-13 Verfahren zum Herstellen von Halbleiterelementen unter Verwendung eines Metall-Lift-off-Vorgangs und dadurch hergestelltes Halbleiterelement
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