TWI790664B - 半導體元件及製造方法 - Google Patents
半導體元件及製造方法 Download PDFInfo
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- TWI790664B TWI790664B TW110123722A TW110123722A TWI790664B TW I790664 B TWI790664 B TW I790664B TW 110123722 A TW110123722 A TW 110123722A TW 110123722 A TW110123722 A TW 110123722A TW I790664 B TWI790664 B TW I790664B
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- Prior art keywords
- layer
- dielectric
- passivation layer
- pac
- dielectric material
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Images
Classifications
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
提供鈍化層及導通孔,其中成像能量的穿透率在鈍化層的材料內增加。穿透率的增加允許進行更大的交聯,此有助於增加對形成於鈍化層內的開口的輪廓的控制。一旦形成開口,便可在開口內形成導通孔。
Description
本揭露實施例是有關於一種半導體元件及製造方法。
由於各種電子部件(例如,電晶體、二極體、電阻器、電容器等)的整合密度的持續提高,半導體行業已經歷快速增長。在很大程度上,整合密度的此種提高是源自最小特徵大小(minimum feature size)的連番減小(例如,朝向20奈米節點以下(sub-20nm node)縮減半導體製程節點),而使更多的部件能夠整合於所給定的區域中。隨著近來對小型化、提高速度、增加頻寬、降低功率損耗及縮短延遲的需求的增加,對更小且更具創造性的半導體晶粒封裝技術的需要亦隨著增加。
隨著半導體技術的進一步推進,經堆疊及結合的半導體元件已出現作為一種有效的替代選擇,以進一步減小半導體元件的物理大小。在經堆疊的半導體元件中,例如邏輯、記憶體、處理器電路及類似物等主動電路至少部分地在單獨的基底上製作,且然後再物理及電性結合在一起以形成功能元件(functional
device)。此種結合製程利用精密的技術,且期望有所改進。
依據本發明實施例提出一種製造半導體元件的方法,所述方法包括:在基底上方形成重佈線層;將第一介電材料施加至所述重佈線層及所述基底,其中所述第一介電材料對第一能量的穿透率大於約0.5%;以及用所述第一能量對所述第一介電材料進行成像。
依據本發明實施例提出一種製造半導體元件的方法,所述方法包括:將介電塗層施加至載體基底上;藉由將所述介電塗層暴露於經圖案化的能量源來起始所述介電塗層內的交聯,其中在所述起始所述交聯之後,所述介電塗層的第一區具有較所述介電塗層的第二區高的交聯度,所述第一區位於所述第二區與所述載體基底之間;使所述介電塗層顯影以形成介層窗孔;以及在所述介層窗孔中形成導通孔。
依據本發明實施例提出一種製造半導體元件,包括:第一介電層;第一通孔,延伸貫穿所述第一介電層,所述通孔具有介於約55°與約78°之間的錐形側壁角度;第二通孔,延伸貫穿載體基底,所述第二通孔電性連接至所述第一通孔;以及第一半導體晶粒,位於所述載體基底的與所述第一通孔相對的一側上,所述第一半導體晶粒電性連接至所述第二通孔。
101:載體
103:膜膠帶
105:第一晶種層
107、401:第一開口
201:第一重佈線層
203:導通孔/穿孔
301:第一鈍化層
403:虛線框
501:第二重佈線層
503:第二鈍化層
601:第三重佈線層
701:第三鈍化層
901:載體基底/載體晶圓
1001:第四重佈線層
1101:第一半導體晶粒
1103:第一外部連接
1105:第一保護層
1201:包封體
1301:第一組重佈線層
1401:穿孔
1403:第二半導體晶粒/積體電路晶粒
1405:包封體
1407:前側重佈線結構
1501:環結構
1601:第二外部連接
1701:系統晶片(SoC)
1703:載體
1705:包封體
1707:第一系列金屬化層
1709:第二系列金屬化層
1801:積體基底
1803:重佈線結構
θ1:第一角度
結合附圖閱讀以下詳細說明會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的載體。
圖2示出根據一些實施例的重佈線層的形成。
圖3示出根據一些實施例的第一鈍化層的形成。
圖4A至圖4B示出根據一些實施例的第一鈍化層的圖案化。
圖5示出根據一些實施例的第二重佈線層的形成。
圖6示出根據一些實施例的第三重佈線層的形成。
圖7示出根據一些實施例的第三鈍化結構的形成。
圖8示出根據一些實施例的膜膠帶的移除。
圖9示出根據一些實施例的載體晶圓的貼合。
圖10示出根據一些實施例的第四重佈線層的形成。
圖11示出根據一些實施例的第一半導體元件的放置。
圖12示出根據一些實施例的包封體的放置。
圖13示出根據一些實施例的第一組重佈線層的形成。
圖14示出根據一些實施例的第二半導體元件的放置。
圖15示出根據一些實施例的環形結構的貼合。
圖16示出根據一些實施例的第二外部連接的形成。
圖17示出根據一些實施例的晶圓上系統(system on
wafer)。
圖18示出根據一些實施例的積體基底上系統(system on integrated substrate)。
以下揭露內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述部件及排列的具體實例以簡化本揭露。當然,該些僅為實例而非旨在進行限制。舉例而言,在以下說明中,在第二特徵上方或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露在各種實例中可重複使用參考編號及/或字母。此種重複使用是為了簡明及清晰起見,且自身並不表示所討論的各個實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「在...下方(beneath)」、「在...下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個組件或特徵與另一(其他)組件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括元件在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或其他取向),且本文中所用的空間相對性描述語可同樣相應地進行解釋。
現在將關於特定結構及材料(例如,積體扇出型封裝)
來描述實施例。然而,在本文中描述的實施例可用於各種各樣的實施例中,並且所有此類實施例皆完全旨在包括於實施例的範圍內。
現在參照圖1,示出載體101、位於載體101的第一側上的膜膠帶103以及已形成於載體101上的第一晶種層105。在實施例中,載體可包含例如氮化鋁(AlN)、氧化矽、矽、氧化鋁、其組合或類似物等材料。另外,對載體101進行成形以適應上覆層的形成。然而,可利用任何合適的材料及形狀。
另外,載體101包括貫穿載體101的第一開口107。對第一開口107進行放置以幫助形成導通孔203(圖1中未示出,但以下將關於圖2進一步示出及討論)。在實施例中,可使用微影遮罩及蝕刻製程來形成第一開口107。然而,可利用任何合適的製程。
膜膠帶103沿著載體101的第一側放置及定位。在實施例中,膜膠帶103可為當暴露於紫外光時會失去其黏合性質的紫外膠帶。然而,亦可使用其他類型的膠帶,例如壓敏膠帶、可輻射固化膠帶、其組合、或類似物。可利用任何合適的膜膠帶103。
第一晶種層105形成於載體101上方及第一開口107內。在實施例中,第一晶種層105是導電材料的薄層,其有助於在後續處理步驟中形成更厚的層。第一晶種層105可包括約1,000埃厚的鈦層,隨後是約5,000埃厚的銅層。第一晶種層105可依據所需的材料使用例如濺射、蒸鍍或電漿增強型化學氣相沈積(PECVD)製程等製程來生成。第一晶種層105可被形成為具有約0.3微米與
約1微米之間(例如,約0.5微米)的厚度。
圖2示出位於載體101上並貫穿載體101的第一重佈線層201及穿孔203的形成。在實施例中,藉由首先在第一晶種層105上形成光阻(圖2中未單獨示出)來形成第一重佈線層201及穿孔203。在實施例中,可使用例如旋轉塗佈技術將光阻放置在第一晶種層105上至約50微米與約250微米之間(例如,約120微米)的高度。一旦就位,接著便可藉由以下方式將光阻圖案化:將光阻暴露於經圖案化的能量源(例如,經圖案化的光源)以引發化學反應,藉此引發光阻的被暴露於經圖案化的光源的該些部分的物理變化。然後對被暴露的光阻施加顯影劑,以利用所述物理變化並依據所期望的圖案而選擇性地移除光阻的被暴露的部分或光阻的未暴露部分。
在實施例中,形成於光阻中的圖案是用於穿孔203及第一重佈線層201的圖案。一旦光阻就位,便在光阻內形成穿孔203及第一重佈線層201。在實施例中,穿孔203及第一重佈線層201包含一或多種導電材料(例如銅、鎢、其他導電金屬或類似物),且可例如藉由電鍍、無電鍍覆或類似技術來形成。在實施例中,使用電鍍製程,在所述電鍍製程中,將第一晶種層105及光阻浸沒或浸漬在電鍍溶液中。第一晶種層105的表面電性連接至外部直流(direct current,DC)電源的負極側(negative side),以使得第一晶種層105在電鍍製程中充當陰極。實心導電陽極(例如銅陽極)亦浸漬在所述溶液中並將所述實心導電陽極貼合至電源的
正極側。來自陽極的原子溶解在溶液中,陰極(例如,第一晶種層105)自所述溶液獲取所溶解的原子,藉此鍍覆第一晶種層105的在光阻的開口中暴露出的導電區域。
一旦使用光阻及第一晶種層105形成了穿孔203及第一重佈線層201,便可使用合適的移除製程移除光阻。在實施例中,可使用電漿灰化製程來移除光阻,藉此可增加光阻的溫度直至光阻經歷熱分解且可被移除。然而,可利用任何其他合適的製程,例如濕式剝離。移除光阻可暴露出第一晶種層105的下伏部分。
一旦暴露出第一晶種層105之後,便可執行第一晶種層105的被暴露部分的移除。在實施例中,可藉由例如濕式蝕刻製程或乾式蝕刻製程來移除第一晶種層105的被暴露部分(例如,未被穿孔203及第一重佈線層201覆蓋的該些部分)。舉例而言,在乾式蝕刻製程中,可使用穿孔203及第一重佈線層201作為罩幕將反應導向第一晶種層105。在另一實施例中,可噴灑蝕刻劑或以其他方式使蝕刻劑與第一晶種層105接觸,以移除第一晶種層105的被暴露部分。在已蝕刻掉第一晶種層105的被暴露部分之後,在穿孔203與第一重佈線層201之間暴露出一部分的載體101。
在實施例中,第一重佈線層201(具有或不具有第一晶種層105)可被形成為具有大於約20微米(例如在約20微米與約70微米之間)的厚度。藉由利用如此大的厚度,可減少穿透率損失,此亦使得功率效率提高。然而,可利用任何合適的厚度。
圖3示出第一鈍化層301在第一重佈線層201上方的放
置。在實施例中,第一鈍化層301包括在後續製程期間不會顯著收縮並且在後續曝光製程(例如,微影曝光)期間亦將具有高穿透率的材料。舉例而言,在一些實施例中,第一鈍化層301可為例如聚醯亞胺、聚苯並噁唑(polybenzoxazole,PBO)、環氧樹脂、雙馬來醯亞胺三嗪(BT)、聚(對伸苯基氧化物)、其組合或類似物等材料。然而,可使用任何合適的材料。
在第一鈍化層301是聚醯亞胺材料的實施例中,第一鈍化層301可藉由最初產生聚醯亞胺組成物來形成,所述聚醯亞胺組成物可包括聚醯亞胺樹脂以及置於聚醯亞胺溶劑中的光活化組分(photoactive component,PAC)。在實施例中,聚醯亞胺樹脂可包含由下式的單體構成的聚合物:
此外,儘管聚醯亞胺樹脂可為如上所述的實施例,但聚醯亞胺樹脂並不旨在僅限於在本文中描述的具體實例。相反,可利用任何合適的聚醯亞胺樹脂,並且所有此類感光性聚醯亞胺樹脂皆完全旨在包括於實施例的範圍內。
PAC可為光活化組分,例如光酸產生劑、光鹼產生劑(photobase generator)、自由基產生劑或類似物,且PAC可為發揮正作用的或發揮負作用的。在實施例中,PAC可包括一或多種化合物(例如,第一PAC化合物、第二PAC化合物、第三PAC化合物及第四PAC化合物)的第一PAC混合物。然而,可利用任何合適數量的PAC化合物。
在實施例中,第一PAC化合物可包括具有膦基的多環化合物。在一些實施例中,所述多環化合物包括三或更多個碳環,其中一或多個碳環經由膦基彼此連接。在特定實施例中,第一PAC化合物包括以下結構:
然而,可利用任何合適的結構。
在實施例中,第二PAC化合物可包含另一種具有膦基的多環化合物。在一些實施例中,另一種多環化合物包括三或更多個碳環,其中一或更多個碳環以不同於第一PAC化合物的結構利用膦基彼此連接。在特定實施例中,第二PAC化合物包括以下結
構:
然而,可使用任何合適的結構。
在實施例中,第三PAC化合物可包含另一種多環化合物,但不含膦基。相反,在實施例中,第三PAC化合物包括在不存在膦基的情況下彼此直接連接的三或更多個碳環。在一些實施例中,第三PAC化合物包括三或更多個碳環,其中一或多個碳環以不同於第一PAC化合物的結構在不存在膦基的情況下彼此連接。在特定實施例中,第二PAC化合物包括以下結構:
然而,可利用任何合適的結構。
在實施例中,第四PAC化合物可包括另一種環結構,但在本實施例中,環的數量小於3,例如具有單個碳環。另外,第四PAC化合物可包括連接至碳環的胺基。因此,在實施例中,第四PAC化合物包括以下結構:
其中n在1與1000之間。然而,可利用任何合適的結構。
在實施例中,第一PAC化合物、第二PAC化合物、第三PAC化合物及第四PAC化合物共同形成第一PAC混合物。舉例而言,在第一PAC混合物中,第一PAC化合物的濃度可在約0.03重量%與約1.0重量%之間,第二PAC化合物的濃度可在約0.03重量%與約1.0重量%之間,第三PAC化合物的濃度可在約0.03重量%與約1.0重量%之間,且第四PAC化合物的濃度可在約0.03重量%與約1.0重量%之間。然而,可利用任何合適的濃度。
將本文中呈現的材料用於第一PAC混合物,可增加第一鈍化層301的總穿透率。藉由增加穿透率,隨後的成像(以下參照圖4A進一步描述)允許在第一鈍化層301內更深處發生更大的
交聯。此種交聯允許在顯影期間具有更佳的耐化學性,藉此允許達成具有更多受控角度的介層窗孔。
在另一實施例中,可使用允許降低第一鈍化層301內PAC的總濃度的第二PAC混合物,而非使用如上所述的用於第一PAC混合物的材料組成物。在本實施例中,第二PAC混合物可包括第五PAC化合物、第六PAC化合物、第七PAC化合物、第八PAC化合物、第九PAC化合物及第十PAC化合物。在本實施例中,第五PAC化合物、第六PAC化合物、第七PAC化合物、第八PAC化合物、第九PAC化合物及第十PAC化合物中的一或多者包括環數小於或等於2的碳環(包括飽和及不飽和環)。
在實施例中,第七PAC化合物可包括又一種環結構,其中環的數量小於或等於2,例如具有兩個碳環。此外,在本實施例中,環經由包含甲氧基的結構連接。舉例而言,在實施例中,第七PAC化合物包括以下結構:
然而,可利用任何合適的結構。
在實施例中,第五PAC化合物、第六PAC化合物、第七PAC化合物、第八PAC化合物、第九PAC化合物及第十PAC化
合物共同形成第二PAC混合物。舉例而言,在第二PAC混合物中,第五PAC化合物的濃度可在約0.03重量%與約1重量%之間,第六PAC化合物的濃度可在約0.03重量%與約1重量%之間,第七PAC化合物的濃度可在約0.03重量%與約1重量%之間,且第八PAC化合物的濃度可在約0.03重量%與約1重量%之間,第九PAC化合物的濃度可在約0.03重量%與約1重量%之間,且第十PAC化合物的濃度可在約0.03重量%與約1重量%之間。然而,可利用任何合適的濃度。
藉由將本文中呈現的材料用於第二PAC混合物,可利用較低的PAC總濃度,藉此藉由降低存在的PAC的量來降低第一鈍化層301的總穿透率。藉由增加穿透率,隨後的成像(以下參照圖4A進一步描述)允許在第一鈍化層301內更深處發生更大的交聯。此種交聯允許在顯影期間具有更佳的耐化學性,藉此允許達成具有更多受控角度的介層窗孔。
在實施例中,聚醯亞胺溶劑可為有機溶劑,且可包含任何合適的溶劑,例如酮、醇、多元醇、醚、乙二醇醚、環醚、芳族烴、酯、丙酸酯、乳酸鹽、乳酸酯、烷二醇單烷基醚(alkylene glycol monoalkyl ethers)、乳酸烷基酯(alkyl lactates)、烷氧基丙酸烷基酯(alkyl alkoxypropionates)、環內酯(cyclic lactones)、包含環的一元酮化合物、碳酸伸烷基酯(alkylene carbonates)、烷氧基乙酸烷基酯(alkyl alkoxyacetate)、丙酮酸烷基酯(alkyl pyruvates)、乙二醇烷基醚乙酸酯(ethylene glycol alkyl ether
acetates)、二乙二醇(diethylene glycols)、丙二醇烷基醚乙酸酯(propylene glycol alkyl ether acetates)、烷二醇烷基醚酯(alkylene glycol alkyl ether esters)、烷二醇單烷基酯(alkylene glycol monoalkyl esters)或類似物。
可用作聚醯亞胺組成物的聚醯亞胺溶劑的材料的具體實例包括丙酮、甲醇、乙醇、甲苯、二甲苯、4-羥基-4-甲基-2-戊酮(4-hydroxy-4-methyl-2-pentatone)、四氫呋喃(tetrahydrofuran)、甲基乙基酮(methyl ethyl ketone)、環己酮(cyclohexanone)、甲基異戊基酮(methyl isoamyl ketone)、2-庚酮、乙二醇、乙二醇單乙酸酯(ethylene glycol monoacetate)、乙二醇二甲醚(ethylene glycol dimethyl ether)、乙二醇甲乙醚(ethylene glycol methylethyl ether)、乙二醇單乙醚(ethylene glycol monoethyl ether)、甲基溶纖劑乙酸酯(methyl celluslve acetate)、乙基溶纖劑乙酸酯(ethyl cellosolve acetate)、二乙二醇、二乙二醇單乙酸酯、二乙二醇單甲醚、二乙二醇二乙醚、二乙二醇二甲醚、二乙二醇乙甲醚、二乙二醇單乙醚、二乙二醇單丁醚、2-羥基丙酸乙酯、2-羥基-2-甲基丙酸甲酯、2-羥基-2-甲基丙酸乙酯、乙氧基乙酸乙酯、羥基乙酸乙酯、2-羥基-2-甲基丁酸甲酯、3-甲氧基丙酸甲酯、3-甲氧基丙酸乙酯、3-乙氧基丙酸甲酯、3-乙氧基丙酸乙酯、乙酸乙酯、乙酸丁酯、乳酸甲酯及乳酸乙酯、丙二醇、丙二醇單乙酸酯、丙二醇單乙醚乙酸酯、丙二醇單甲醚乙酸酯、丙二醇單丙甲醚乙酸酯、丙二醇單丁醚乙酸酯、丙二醇單甲醚丙酸酯、丙二醇單乙醚丙酸酯、
丙二醇單甲基醚乙酸酯、丙二醇單乙基醚乙酸酯、乙二醇單甲醚乙酸酯、乙二醇單乙醚乙酸酯、丙二醇單甲醚、丙二醇單乙醚、丙二醇單丙醚、丙二醇單丁醚、乙二醇單甲醚、乙二醇單乙醚、乳酸丙酯及乳酸丁酯、3-乙氧基丙酸乙酯、3-甲氧基丙酸甲酯、3-乙氧基丙酸甲酯及3-甲氧基丙酸乙酯、β-丙內酯(β-propiolactone)、β-丁內酯(β-butyrolactone)、γ-丁內酯(γ-butyrolactone)、α-甲基-γ-丁內酯(α-methyl-γ-butyrolactone)、β-甲基-γ-丁內酯(β-methyl-γ-butyrolactone)、γ-戊內酯(γ-valerolactone)、γ-己內酯(γ-caprolactone)、γ-辛內酯(γ-octanoic lactone)、α-羥基-γ-丁內酯(α-hydroxy-γ-butyrolactone)、2-丁酮、3-甲基丁酮、頻哪酮(pinacolone)、2-戊酮、3-戊酮、4-甲基-2-戊酮、2-甲基-3-戊酮、4,4-二甲基-2-戊酮、2,4-二甲基-3-戊酮、2,2,4,4-四甲基-3-戊酮、2-己酮、3-己酮、5-甲基-3-己酮、2-庚酮、3-庚酮、4-庚酮、2-甲基-3-庚酮、5-甲基-3-庚酮、2,6-二甲基-4-庚酮、2-辛酮、3-辛酮、2-壬酮、3-壬酮、5-壬酮、2-癸酮、3-癸酮、4-癸酮、5-己-2-酮、3-戊-2-酮、環戊酮、2-甲基環戊酮、3-甲基環戊酮、2,2-二甲基環戊酮、2,4,4-三甲基環戊酮、環己酮、3-甲基環己酮、4-甲基環己酮、4-乙基環己酮、2,2-二甲基環己酮、2,6-二甲基環己酮、2,2,6-三甲基環己酮、環庚酮、2-甲基環庚酮、3-甲基環庚酮、丙烯碳酸酯、伸乙烯碳酸酯、乙烯碳酸酯、及丁烯碳酸酯、乙酸-2-甲氧基乙酯、乙酸-2-乙氧基乙酯、乙酸-2-(2-乙氧基乙氧)乙酯、乙酸-3-甲氧基-3-甲基丁酯、乙酸-1-甲氧基-2-
丙酯、二丙二醇、單甲醚、單乙醚、單丙醚、單丁醚、單苯基醚、二丙二醇單乙酸酯、二噁烷、乳酸乙酯、乙酸甲酯、乙酸乙酯、乙酸丁酯、丙酮酸甲酯、丙酮酸乙酯、丙酮酸丙酯、甲氧基丙酸甲酯、乙氧基丙酸乙酯、正甲基吡咯烷酮(n-methylpyrrolidone,NMP)、2-甲氧基乙基醚(二甘醇二甲醚)、乙二醇單甲醚、丙二醇單甲醚;丙酸甲酯、丙酸乙酯、及乙氧基丙酸乙酯、甲乙酮、環己酮、2-庚酮、二氧化碳、環戊酮、環己酮、3-乙氧基丙酸乙酯、丙二醇甲醚乙酸酯(propylene glycol methyl ether acetate,PGMEA)、亞甲基溶纖劑(methylene cellosolve)、乙酸丁酯、及2-乙氧基乙醇、N-甲基甲醯胺、N,N-二甲基甲醯胺、N-甲基甲醯苯胺、N-甲基乙醯胺、N,N-二甲基乙醯胺、N-甲基吡咯烷酮(N-methylpyrrolidone)、二甲基亞碸(dimethylsulfoxide)、苯甲基乙醚、二己醚、丙酮基丙酮、異佛爾酮(isophorone)、己酸、辛酸、1-辛醇、1-壬醇、苯甲醇、乙酸苯甲酯、苯甲酸乙酯、草酸二乙酯、馬來酸二乙酯(diethyl maleate)、γ-丁內酯(γ-butyrolactone)、乙烯碳酸酯、丙烯碳酸酯、苯基溶纖劑乙酸酯(phenyl cellosolve acetate)或類似物。
在實施例中,聚醯亞胺樹脂及PAC(例如,第一PAC混合物及/或第二PAC混合物)與任何所需的添加劑或其他試劑一起被添加至聚醯亞胺溶劑中用於應用。舉例而言,聚醯亞胺樹脂的濃度可在約15%與約25%之間。此外,在其中利用第一PAC混合物的實施例中,PAC共同的濃度可在約0.1重量%與約15重量%
之間。在其他實施例(例如在其中利用第二PAC混合物的實施例)中,PAC共同的濃度可小於約5重量%。然而,可利用任何合適的濃度。
一經加入,便接著對所述混合物進行混合以在整個聚醯亞胺組成物中達成均勻組成,以確保不存在由不均勻混合或非恆定組成引起的缺陷。一旦混合在一起,便可將聚醯亞胺組成物在其使用之前進行儲存或者立即使用。
一旦準備好,便可藉由首先將聚醯亞胺組成物施加至第一重佈線層201上來利用第一鈍化層301。在其中聚醯亞胺組成物是清漆的實施例中,第一鈍化層301可被施加至第一重佈線層201,使得第一鈍化層301塗佈第一重佈線層201的上部暴露表面,並且可利用例如旋塗製程、浸塗法、氣刀塗佈法(air-knife coating method)、簾塗法(curtain coating method)、絲-桿(wire-bar)塗佈法、凹版塗佈法、層疊法、擠壓塗佈法、其組合或類似製程來施加。
一經施加,便可對第一鈍化層301進行烘烤,以便在曝光之前固化及乾燥第一鈍化層301(以下進一步描述)。第一鈍化層301的固化及乾燥移除溶劑組分,同時留下了樹脂、PAC及任何其他所選添加劑。在實施例中,可在適於蒸鍍溶劑的溫度(例如在約40℃與150℃之間,例如約150℃)下執行預烘烤,但精確的溫度取決於為第一鈍化層301選擇的材料。預烘烤執行足以固化及乾燥第一鈍化層301的時間,例如在約10秒至約5分鐘之間,
例如約270秒。
圖4A示出,一經固化及乾燥,便可對第一鈍化層301進行圖案化以形成至第一重佈線層201的第一開口401(例如,通孔開口)。在實施例中,可藉由將第一鈍化層301放入成像元件(在圖4A中未單獨示出)中進行曝光來起始圖案化。成像元件可包括支撐板、能量源以及位於支撐板與能量源之間的圖案化罩幕。
在實施例中,能量源向第一鈍化層301供應例如光等能量,以便引發PAC的反應,此繼而與樹脂反應,以化學地改變第一鈍化層301的能量撞擊的該些部分。在實施例中,能量可為電磁輻射,例如g射線(波長約為436奈米)、i射線(波長約為365奈米)、紫外線輻射、遠紫外線輻射、x射線、電子束或類似物。能量源可為電磁輻射源,並且可為KrF準分子雷射光(波長為248奈米)、ArF準分子雷射光(波長為193奈米)、F2準分子雷射光(波長為157奈米)或類似物,但亦可利用任何其他合適的能量源,例如汞蒸汽燈、氙燈、碳弧燈或類似物。
經圖案化的罩幕位於能量源與第一鈍化層301之間,以便在能量實際撞擊在第一鈍化層301上之前阻擋能量的一些部分以形成經圖案化的能量。在實施例中,經圖案化的罩幕可包括一系列層(例如,基底、吸收層、抗反射塗層、屏蔽層等)以反射、吸收或以其他方式阻擋能量的一些部分到達第一鈍化層301的不期望被照射的該些部分。藉由以期望的照明形狀貫穿經圖案化的罩幕形成開口,可在經圖案化的罩幕中形成期望的圖案。
在實施例中,第一鈍化層301放置在支撐板上。一旦圖案已與第一鈍化層301對準,能量源便產生穿過經圖案化的罩幕到達第一鈍化層301的期望的能量(例如,光)。舉例而言,在其中PAC包括第一PAC混合物的實施例中,經圖案化的能量可包括波長在約380奈米與約440奈米之間的光(例如,G/H線(G/H-line)),同時,在其中PAC包括第二PAC混合物的實施例中,所述經圖案化的能量可包括波長在約200奈米與約380奈米之間的光(例如,I線(I-line))。然而,可利用任何合適波長的光。
撞擊在第一鈍化層301的一些部分上的經圖案化的能量引發第一鈍化層301內PAC的反應。PAC吸收經圖案化的能量後的化學反應產物(例如,酸/鹼/自由基)然後與樹脂反應,從而化學地改變經由經圖案化的罩幕被照射的該些部分中的第一鈍化層301。在一些實施例中,化學改變包括聚合物樹脂的單獨聚合物之間的交聯。
然而,由於由第一PAC混合物引起的穿透率增加或第二PAC混合物的濃度降低(例如,穿透率大於約0.5%至約1%),更多的經圖案化的能量將在曝光過程中穿過第一鈍化層301。經圖案化的能量然後將到達下伏導電材料(例如,銅)並散射,且然後散射光導致PAC再次產生更多的自由基,藉此導致鄰近下伏導電材料的更大程度的交聯。因此,在曝光過程起始交聯之後,第一鈍化層301的第一區較第一鈍化層301的第二區具有更高的交聯
度,第一區位於第二區與載體101之間。
在第一鈍化層301已被曝光之後,可利用第一曝光後烘烤(post-exposure bake,PEB),以助於在曝光期間由能量撞擊在PAC上產生的酸/鹼/自由基的產生、分散及反應。此種幫助有助於創造或增強化學反應,所述化學反應在被能量撞擊的該些區與未被能量撞擊的該些區之間產生化學差異及不同的極性。該些化學差異亦導致在被能量撞擊的區與未被能量撞擊的該些區之間溶解度的差異。在實施例中,第一鈍化層301的溫度可在約40秒與約120秒的時間段(例如約2分鐘)內升高至約70℃與約150℃之間。然而,可利用任何合適的溫度及時間。
一旦第一鈍化層301已被曝光及烘烤,便可利用顯影劑對第一鈍化層301進行顯影。在其中第一鈍化層301是聚醯亞胺的實施例中,第一顯影劑可為有機溶劑,或者可利用臨界流體來移除第一鈍化層301的未被暴露於能量的該些部分,並且因此保持其原始溶解度。可利用的材料的具體實例包括烴類溶劑、醇類溶劑、醚類溶劑、酯類溶劑、臨界流體、其組合或類似物。可用於負性溶劑的材料的具體實例包括環戊酮、己烷、庚烷、辛烷、甲苯、二甲苯、二氯甲烷、氯仿、四氯化碳、三氯乙烯、甲醇、乙醇、丙醇、丁醇、臨界二氧化碳、二乙醚、二丙醚、二丁醚、乙基乙烯基醚、二噁烷、氧化丙烯、四氫呋喃、溶纖劑、甲基溶纖劑、丁基溶纖劑、甲基卡必醇、二甘醇單乙醚、丙酮、甲基乙基酮、甲基異丁基酮、異佛爾酮、環己酮、乙酸甲酯、乙酸乙酯、
乙酸丙酯、乙酸丁酯、吡啶、甲醯胺、N,N-二甲基甲醯胺或類似物。
可使用例如旋塗製程將第一顯影劑施加至第一鈍化層301。在此製程中,當第一鈍化層301被旋轉時,第一顯影劑自第一鈍化層301上方施加至第一鈍化層301。在實施例中,第一顯影劑可處於約10℃與約80℃之間、例如約50℃的溫度下,並且顯影可持續約1分鐘至約60分鐘,例如約30分鐘。
然而,儘管本文中所述的旋塗法為一種適合於在曝光之後對第一鈍化層301進行顯影的方法,但其旨在為說明性的,而並不旨在限制實施例。相反,可作為另一選擇使用用於顯影的任何合適的方法,包括浸漬製程、液浸製程(puddle process)、噴塗製程、其組合或類似物。所有此種顯影製程皆完全旨在包括於實施例的範圍內。
一旦第一鈍化層301已被顯影,便可對第一鈍化層301進行沖洗。在實施例中,可用例如丙二醇單甲醚乙酸酯(C260)等沖洗液對第一鈍化層301進行沖洗,但可使用任何合適的沖洗溶液,例如水。
在顯影之後,可利用顯影後烘烤製程,以便在顯影製程之後幫助聚合及穩定第一鈍化層301。在實施例中,顯影後烘烤過程可在約80℃與約200℃之間、例如約140℃的溫度下執行約60秒與約300秒之間的時間,例如約2分鐘。
在顯影後烘烤之後,第一鈍化層301可固化。在第一鈍
化層301包含聚醯亞胺的實施例中,可在低於約230℃的溫度下、例如在約200℃與230℃之間的溫度下、例如在約220℃下將固化製程執行約1小時與約2小時之間的時間。然而,可利用任何合適的溫度及時間。
圖4B示出由圖4A中的虛線框403包圍的第一開口401中的一者的特寫視圖。藉由利用如本文中所述的第一鈍化層301,可形成具有在約55°與約78°之間、例如約78°的第一角度θ1(例如,錐角)的第一開口401。舉例而言,當利用第一PAC混合物時,第一角度θ1可為約78°,而當利用第二PAC混合物時,第一角度θ1可在約55°與約78°之間。然而,可利用任何合適的角度。
在其中利用第二PAC混合物的特定實施例中,第一開口401可具有約45微米的寬度。另外,第一鈍化層301可具有約30微米的厚度。利用該些尺寸,第一角度θ1的錐度可在約55°與約78°之間,而非具有大於78°(例如,100°)的錐角(此實際上會導致形成凹面)。
在其中利用第一PAC混合物的另一特定實施例中,第一開口401可具有約40微米的寬度。另外,第一鈍化層301可具有約28微米的厚度。利用該些尺寸,第一角度θ1的錐度可為約78°。然而,第一開口401的尺寸並非僅限於在本文中描述的尺寸,乃因當第一鈍化層301為5微米或5.5微米厚時,第一開口401亦可具有7微米的寬度,或者當第一鈍化層301為19微米厚時,第一開口401可為21微米寬。可利用任何合適的尺寸。
另外,在形成第一鈍化層301期間,第一鈍化層301將經歷一些收縮。然而,藉由利用本文中所述的實施例,收縮可被限制在約1%與約5%之間。因此,可施加更薄的第一鈍化層301,同時仍然確保足夠的覆蓋及隔離。在一些實施例中,第一鈍化層301在形成後可具有約10微米至約60微米之間的厚度。
圖5示出在第一鈍化層301已被圖案化之後,第二重佈線層501可被形成為延伸貫穿形成於第一鈍化層301內的開口,呈現第一開口401的形狀,並且與第一重佈線層201電性連接。在實施例中,第二重佈線層501可使用類似於第一重佈線層201的材料及製程形成有通孔部分及線部分。舉例而言,可施加晶種層並由經圖案化的光阻覆蓋所述晶種層,可將例如銅等導電材料施加至晶種層上,可移除經圖案化的光阻,並且可利用導電材料作為罩幕來蝕刻晶種層。然而,可利用任何合適的材料或製造製程。
然而,在實施例中,第二重佈線層501可被形成為較第一重佈線層201薄。因此,第二重佈線層501可被形成至約5微米與約8微米之間的厚度。然而,可利用任何合適的厚度。
在形成第二重佈線層501之後,在第二重佈線層501上方施加、曝光及顯影第二鈍化層503,以助於隔離及保護第二重佈線層501。在實施例中,第二鈍化層503可由與第一鈍化層301類似的材料並以與第一鈍化層301類似的方式形成。舉例而言,第二鈍化層503可由已如上關於第一鈍化層301所述被施加及圖
案化的聚醯亞胺形成。
然而,在另一實施例中,第二鈍化層503可使用濃度高於第一鈍化層301的第二PAC混合物形成。舉例而言,在本實施例中,第二鈍化層503使用與第一鈍化層301相同的材料(例如,聚合物樹脂、溶劑、PAC)形成,但第二PAC混合物的濃度增加至約15重量%,此產生約65%的穿透率(使用I線)。因此,在本實施例中,第二鈍化層503的厚度可減小至小於約10微米,例如在約5微米與約7微米之間。然而,可利用任何合適的厚度。
圖6示出在第二鈍化層503已被圖案化之後,可形成具有延伸貫穿形成於第二鈍化層503內的開口的通孔的第三重佈線層601,並且第三重佈線層601與第二重佈線層501電性連接。在實施例中,第三重佈線層601可使用類似於第一重佈線層201的材料及製程來形成。舉例而言,可施加晶種層並由經圖案化的光阻覆蓋所述晶種層,可將例如銅等導電材料施加至晶種層上,可移除經圖案化的光阻,並且可利用導電材料作為罩幕來蝕刻晶種層。然而,可使用任何合適的材料或製造製程。
然而,在其中第二鈍化層503由增加量的第二PAC混合物形成的實施例中(例如,約15重量%的第二PAC混合物),貫穿第二鈍化層503的通孔可被形成為具有約7微米的高度及約0.8與約1.0之間的縱橫比,並且具有約78°的錐角。因此,延伸貫穿第一鈍化層301的通孔與延伸貫穿第二鈍化層503的通孔具有約0與約20之間的錐角差。
另外,在本實施例中,延伸貫穿第二鈍化層503的通孔具有約為30%的階梯覆蓋率(例如,第二鈍化層503內的晶種層的減薄厚度與第二鈍化層503上方的晶種層的厚度的厚度比)。然而,延伸貫穿第一鈍化層301的通孔的晶種層具有大於30%的階梯覆蓋率。
圖7示出在已形成第三重佈線層601之後,在第三重佈線層601上方施加、曝光及顯影第三鈍化層701,以助於隔離及保護第三重佈線層601。在實施例中,第三鈍化層701可由與第二鈍化層503類似的材料並以與第二鈍化層503類似的方式形成。舉例而言,第三鈍化層701可由已如上關於第二鈍化層503所述被施加及圖案化的聚醯亞胺形成。然而,可利用任何合適的材料或製造製程。
圖8示出自膜膠帶103剝離載體101。在膜膠帶103是紫外膠帶的實施例中,利用例如紫外(ultraviolet,UV)雷射、二氧化碳(CO2)雷射或紅外(infrared,IR)雷射等能量源來照射及加熱膜膠帶103,直至膜膠帶103失去其至少一些黏合性質。一經執行,載體101與膜膠帶103便可物理分離。
圖9示出一旦膜膠帶103已被移除,便將載體基底901貼合至第三鈍化層701。在實施例中,載體基底901可為玻璃晶圓、矽晶圓、矽鍺晶圓、其組合或類似物,並且可利用例如熔融結合、介電質對介電質結合、其組合或類似方法等方法來結合。在其他實施例中,載體基底901可使用黏著層來貼合,例如亦可
使用紫外膠帶、壓敏膠帶、可輻射固化膠帶、其組合或類似物。然而,可利用任何合適的材料及結合方法。
圖10示出在載體晶圓901已被結合之後,將所述結構被翻轉,並且可將第四重佈線層1001形成為與現在暴露出的穿孔203接觸。在實施例中,第四重佈線層1001可利用類似於第一重佈線層201的材料及製程來形成。舉例而言,可施加晶種層並由經圖案化的光阻覆蓋所述晶種層,可將例如銅等導電材料施加至晶種層上,可移除經圖案化的光阻,並且可利用導電材料作為罩幕來蝕刻晶種層。然而,可使用任何合適的材料或製造製程。
圖11示出將第一半導體晶粒1101放置在第四重佈線層1001的部分之間。在實施例中,第一半導體晶粒1101可被設計及製造成向上覆第二半導體晶粒1403(例如,感測器晶粒-圖11中未示出,但以下關於圖14進一步示出及描述)提供所需的功能。舉例而言,第一半導體晶粒1101可為數位訊號處理晶粒、輸入/輸出(I/O)晶粒、高電壓晶粒(用於增加上覆感測器晶粒的靈敏度)、其組合或類似物。然而,可利用任何合適的晶粒。
在實施例中,第一半導體晶粒1101可包括半導體基底(未單獨示出)、主動元件(未單獨示出)、用於內連第一半導體晶粒1101的主動元件的金屬化層(未單獨示出)、以及第一外部連接1103,以內連第一半導體晶粒1101。半導體基底可包括經摻雜或未經摻雜的塊狀矽,或者絕緣體上矽(silicon-on-insulator,SOI)基底的主動層。一般而言,SOI基底包含一層半導體材料,例如
矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator,SGOI)或其組合。可使用的其他基底包括多層式基底、梯度基底或混合取向基底。
主動元件包括各種各樣的主動元件及被動元件,例如可用於產生第一半導體晶粒1101的設計的所需結構及功能要求的電容器、電阻器、電感器及類似物。主動元件可利用任何合適的方法在半導體基底內或在半導體基底上形成。
金屬化層形成於半導體基底及第一半導體晶粒1101的主動元件上方,並且被設計成連接各種主動元件以形成功能電路系統。在實施例中,金屬化層由介電材料與導電材料形成的交替層形成,並且可藉由任何合適的製程(例如,沈積、鑲嵌、雙鑲嵌等)形成。在實施例中,可存在藉由至少一個層間介電層(interlayer dielectric layer,ILD)與半導體基底分離的四個金屬化層,但金屬化層的精確數量取決於第一半導體晶粒1101的設計。
第一外部連接1103可被形成為將第一半導體晶粒1101內連至其他結構。因此,在一些實施例中,第一外部連接1103可為例如導電柱,例如銅柱。然而,可利用任何合適的連接,例如接觸凸塊。
可另外於第一外部連接1103周圍形成第一保護層1105。第一保護層1105可由例如以下一或多種合適的介電材料製成:氧化矽、氮化矽、低介電常數介電質(例如,碳摻雜氧化物)、極低介電常數介電質(例如,多孔碳摻雜二氧化矽)、其組合或類似物。
第一保護層1105可藉由例如化學氣相沈積(CVD)等製程形成,但可利用任何合適的製程。
圖12示出用包封體1201包封第一半導體晶粒1101及第四重佈線層1001。包封可在模製元件(圖12中未示出)中執行,所述模製元件可包括頂部模製部分及可與所述頂部模製部分分離的底部模製部分。當頂部模製部分降低至與底部模製部分相鄰時,可為包括第一半導體晶粒1101及第四重佈線層1001的結構形成模製空腔。
在包封製程期間,頂部模製部分可鄰近底部模製部分放置,因此將包括第一半導體晶粒1101及第四重佈線層1001的結構封閉在模製空腔內。一經封閉,頂部模製部分及底部模製部分便可形成氣密密封,以控制氣體自模製空腔的流入及流出。一經密封,便可將包封體1201放置在模製空腔內。包封體1201可為模製化合物樹脂,例如聚醯亞胺、聚苯硫醚(polyphenylene sulfide,PPS)、聚醚醚酮(polyetheretherketone,PEEK)、聚醚碸(Polyethersulfone,PES)、耐熱晶體樹脂、其組合或類似物。可在對準頂部模製部分與底部模製部分之前將包封體1201放置於模製空腔內,抑或可經由注射口將包封體1201注射至模製空腔內。
一旦包封體1201已被放置於模製空腔內而使得包封體1201包封包括第一半導體晶粒1101及第四重佈線層1001的結構,便可將包封體1201固化以硬化包封體1201來實現最佳保護。確切固化製程至少部分地相依於為包封體1201選擇的特定材料,
在其中選擇模製化合物作為包封體1201的實施例中,可藉由例如將包封體1201加熱至約100℃與約130℃之間(例如約125℃)達約60秒至約3000秒(例如約600秒)等製程而發生固化。另外,在包封體1201內可包含起始劑及/或觸媒以更佳地控制固化製程。
然而,如此項技術中具有通常知識者將認識到,上述固化製程僅為示例性製程,而非旨在限制當前實施例。可作為另外一種選擇使用其他固化製程,例如輻照或甚至使包封體1201在周圍環境溫度下硬化。可使用任何合適的固化製程,且所有此類製程皆完全旨在包括於本文中所論述實施例的範圍內。
圖12亦示出使包封體1201薄化以暴露出第一半導體晶粒1101及第四重佈線層1001以供進一步處理。可例如使用機械拋光製程或化學機械研磨(CMP)製程來執行薄化,藉此利用化學蝕刻劑及磨料來發生反應並研磨掉包封體1201、第一半導體晶粒1101及第四重佈線層1001,直至第一半導體晶粒1101及第四重佈線層1001已被暴露出。因此,包括第一半導體晶粒1101及第四重佈線層1001的結構可具有亦與包封體1201呈平面的平面表面。
然而,儘管上述CMP製程被呈現為一個說明性實施例,但其並不旨在限制所述實施例。可作為另一選擇使用任何其他合適的移除製程來使包封體1201、第一半導體晶粒1101及第四重佈線層1001薄化。舉例而言,可利用一系列化學蝕刻。可利用此製
程及任何其他合適的製程來使包封體1201、第一半導體晶粒1101及第四重佈線層1001薄化,且所有此種製程皆完全旨在包含於實施例的範圍內。
圖13示出一旦已放置包封體1201,便可於包封體1201上方形成第一組重佈線層1301。在實施例中,第一組重佈線層1301包括由多個介電鈍化層(為清楚起見,未個別標記)分開的多個導電重佈線層。所述多個介電鈍化層中的每一者可如以上關於第二鈍化層503所述被放置及圖案化,並且所述多個導電重佈線層中的每一者可如以上關於第二重佈線層501所述被形成。然而,可利用任何合適的方法及材料。
在圖14中,將穿孔1401形成為遠離第一組重佈線層1301的最頂部介電層延伸。作為形成穿孔1401的實例,例如在第一組重佈線層1301上形成晶種層(未示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中,晶種層包括鈦層及位於所述鈦層上方的銅層。晶種層可使用例如物理氣相沈積(PVD)或類似技術形成。在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似技術形成,並且可被暴露至光以進行圖案化。光阻的圖案對應於穿孔1401的佈局。圖案化形成貫穿光阻的開口以暴露出晶種層。於光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆或類似鍍覆等鍍覆形成。導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。移除
光阻及晶種層的上面未形成導電材料的部分。光阻可藉由可接受的灰化或剝離製程(例如使用氧電漿或類似物)移除。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如,藉由濕法或乾法蝕刻)移除晶種層的被暴露部分。晶種層及導電材料的剩餘部分形成穿孔1401。
圖14亦示出將第二半導體晶粒1403放置於穿孔1401之間。第二半導體晶粒1403可為被設計成與第一半導體晶粒1101一起工作的感測器晶粒。在一些實施例中,感測器晶粒可為使用例如拾取及放置過程放置的指紋感測器、影像感測器、微機電系統(micro-electromechanical systems,MEMS)感測器、其組合或類似物。然而,可利用任何合適的製程。
在實施例中,第二半導體晶粒1403包括第二半導體基底、形成於第二半導體基底內或上方的感測組件、電性佈線及接觸接墊。第二半導體基底、電性佈線及接觸接墊可類似於以上關於第一半導體晶粒1101所討論的結構,並且感測組件可基於期望的感測器類型使用任何合適的方法及製程來形成。然而,可利用任何合適的結構及方法。
一旦已放置了第二半導體晶粒1403,便於各種部件上及周圍形成包封體1405。在形成之後,包封體1405包封穿孔1401及第二半導體晶粒1403。包封體1405可為模製化合物、環氧樹脂或類似物。包封體1405可藉由壓縮模製、轉移模製或類似模製來施加,並且可被放置或形成為使得穿孔1401及/或第二半導體晶粒
1403被掩埋或覆蓋。包封體1405可以液體或半液體形式施加,且接著隨後固化。
在放置包封體1405之後,對包封體1405執行平坦化製程,以暴露出穿孔1401及第二半導體晶粒1403。平坦化製程亦可移除穿孔1401的材料,直至穿孔1401被暴露出。在平坦化製程之後,穿孔1401及包封體1405的頂表面在製程變化內實質上共面。平坦化製程可為例如化學機械研磨(CMP)、研磨製程或類似製程。在一些實施例中,舉例而言,若穿孔1401已被暴露出,則可省略平坦化。
一旦包封體1405已被平坦化,便於包封體1405、穿孔1401及積體電路晶粒1403上方形成前側重佈線結構1407。前側重佈線結構1407包括介電層及金屬化圖案。金屬化圖案亦可被稱為重佈線層或重佈線線(redistribution line)。示出前側重佈線結構1407作為具有一個金屬化圖案的實例。若要形成更多的介電層及金屬化圖案,則可重複以下所討論的步驟及製程。
在實施例中,於包封體1405及穿孔1401上沈積第一介電層。在一些實施例中,第一介電層由可利用微影罩幕來圖案化的感光性材料(例如,PBO、聚醯亞胺、苯並環丁烯(benzocyclobutene,BCB)或類似物)形成。第一介電層可藉由旋轉塗佈、層疊、化學氣相沈積(CVD)、類似技術或其組合來形成。在一些實施例中,執行平坦化製程以給予第一介電層實質上平坦的上表面。
一旦就位,便接著將第一介電層圖案化。圖案化形成暴露出穿孔1401的一些部分的開口、暴露出接觸接墊的一些部分的開口及暴露出感測組件的開口。圖案化可藉由可接受的製程進行,例如當第一介電層是感光性材料時藉由對第一介電層進行曝光及顯影、或者藉由使用例如非等向性蝕刻進行蝕刻。在其他實施例中,可在第一介電層上方形成罩幕層(未具體示出)並將其圖案化,並且可藉由例如蝕刻來移除第一介電層的被暴露部分。
一旦第一介電層被圖案化,便接著形成金屬化圖案。金屬化圖案包括沿著第一介電層的主表面延伸並延伸貫穿第一介電層以物理及電性耦合至穿孔1401及積體電路晶粒1403的接觸接墊的導電組件。作為實例,為形成金屬化圖案,於第一介電層上方及延伸貫穿第一介電層的開口中形成晶種層(未具體示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層上方的銅層。晶種層可使用例如PVD或類似技術形成。然後在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似技術形成,並且可被暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案。圖案化形成貫穿光阻的開口以暴露出晶種層(包括晶種層的位於穿孔1401上方的開口及接觸接墊上方的開口內的部分)。然後於光阻的開口中及晶種層的被暴露部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆或類似鍍覆等鍍覆形成。導電材料可包括金屬,如銅、鈦、鎢、
鋁或類似物。導電材料與晶種層的下伏部分的組合形成金屬化圖案。移除光阻及晶種層的上面未形成導電材料的部分(包括光阻及晶種層的在感測組件上方的開口內的一些部分)。光阻可藉由可接受的灰化或剝離製程(例如使用氧電漿或類似物)移除。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如,藉由濕法或乾法蝕刻)移除晶種層的被暴露部分。
一旦已形成金屬化圖案,便於金屬化圖案及位於金屬化圖案下方的第一介電層上沈積第二介電層。第二介電層可以類似於金屬化圖案下方的第一介電層的方式形成,並且可由與金屬化圖案下方的第一介電層類似的材料形成。此外,第二介電層可被圖案化以形成開口來暴露出感測組件。舉例而言,圖案化可藉由可接受的製程進行,例如當第二介電層是感光性材料時藉由對第二介電層進行曝光及顯影、或者藉由使用例如非等向性蝕刻進行蝕刻。所述開口可具有與貫穿金屬化圖案下方的第一介電層的開口不同或實質上相同的側向寬度,並且在一些實施例中,具有更大的側向寬度。然後可形成附加的金屬化圖案及介電層(若存在)。
圖15示出將所述結構貼合至環結構1501。環結構1501可為金屬環,用於在剝離製程期間及之後為結構提供支撐及穩定性。在實施例中,前側重佈線結構1407使用例如紫外膠帶貼合至環結構,但亦可使用任何其他合適的黏著劑或貼合。
圖16示出一旦前側重佈線結構1407已貼合至環結構1501,便可使用例如改變黏著層的黏合性質的製程來剝離載體基
底901(在實施例中,其中使用黏著層來貼合載體基底901)。在其中黏著層是紫外黏著劑的特定實施例中,利用例如紫外(UV)雷射、二氧化碳(CO2)雷射或紅外(IR)雷射等能量源來照射及加熱黏著層,直至黏著層失去其至少一些黏合性質。一經執行,載體基底901及黏著層便可自第三鈍化層701物理分離及移除。
圖16另外示出將第三鈍化層701圖案化,以暴露出第三重佈線層601。在實施例中,第三鈍化層701可利用例如雷射鑽孔方法進行圖案化。在此種方法中,首先在第三鈍化層701上方沈積保護層,例如光-熱轉換(light-to-heat conversion,LTHC)層或黑格麥克斯(hogomax)層(圖16中未單獨示出)。一旦被保護,便朝向第三鈍化層701的期望被移除的該些部分引導雷射,以暴露出下伏第三重佈線層601。在雷射鑽孔製程期間,鑽孔能量可在0.1毫焦耳(mJ)至約30毫焦耳的範圍內,並且鑽孔角度相對於第三鈍化層701的法線為約0度(垂直於第三鈍化層701)至約85度。
在另一實施例中,可藉由首先將光阻(圖16中未單獨示出)施加至第三鈍化層701上、且然後將光阻暴露於經圖案化的能量源(例如,經圖案化的光源)以引發化學反應而將第三鈍化層701圖案化,藉此引發光阻的被暴露於經圖案化的光源的該些部分的物理變化。然後對被暴露的光阻施加顯影劑,以利用所述物理變化並依據所期望的圖案而選擇性地移除光阻的被暴露的部分或光阻的未暴露部分,並且利用例如乾法蝕刻製程移除第三鈍
化層701的下伏被暴露部分。然而,可利用用於圖案化第三鈍化層701的任何其他合適的方法。
此外,在載體基底901用黏著層保持就位的實施例中,一旦第三鈍化層701已被圖案化,便可執行清潔製程,以確保黏著層的任何剩餘部分可被移除。在實施例中,清潔製程可包括合適的溶劑、蝕刻劑、其組合或類似物,以為額外的製造步驟清潔並準備表面。
圖16另外示出第二外部連接1601的放置可形成。在實施例中,第二外部連接1601可為例如微凸塊或受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊等接觸凸塊,並且可包含例如錫等材料或例如銀或銅等其他合適的材料。在其中第二外部連接1601是接觸凸塊的實施例中,第二外部連接1601可包含例如錫等材料或例如銀、無鉛錫或銅等其他合適的材料。在其中第二外部連接1601是錫焊料凸塊的實施例中,可藉由首先經由此類常用方法(例如蒸鍍、電鍍、印刷、焊料轉移、球放置等)將錫層形成至例如約100微米的厚度來形成第二外部連接1601。一旦已在所述結構上形成了一層錫,便可執行回焊以使材料成形為所需的凸塊形狀,所述凸塊形狀的臨界尺寸可在約60微米與約100微米之間,並且可形成為圓形形狀或橢圓形形狀。
一旦第二外部連接1601已被放置,便可將封裝單體化。在實施例中,可藉由使用鋸片(未示出)切穿所述結構來執行單體化,藉此將一個區段與另一區段分開。然而,如此項技術中具
有通常知識者將認識到,利用鋸片來單體化所述結構僅為一個說明性實施例,而非旨在為限制性的。亦可利用用於單體化所述結構的其他方法,例如利用一或多個蝕刻來分離所述結構。可利用該些方法及任何其他合適的方法來單體化所述結構。
藉由改變用於形成第一鈍化層301的材料的穿透率,可達成更可控的通孔形狀。具體而言,藉由達成更高的穿透率,在成像製程中將會散射更多的能量,藉此在材料的下部區內產生更大的交聯。此種交聯會產生較以其他方式可達成的形狀更可控的形狀。
圖17示出本文中描述的實施例可應用於其他實施例,例如包括晶圓上系統(system-on-wafer,SOW)實施例的實施例。在該些實施例中,一或多個系統晶片(system-on-chip,SoC)1701位於載體1703上並嵌入包封體1705中。第一系列金屬化層1707(具有如本文中所述形成的重佈線層及鈍化層)及第二系列金屬化層1709(具有如本文中所述形成的重佈線層及鈍化層)形成於包封體1705上方。然而,可利用任何合適的結構。
圖18亦示出在本文中描述的實施例可應用於其他實施例,例如包括積體基底上系統(systems on integrated substrate,SOIS)的實施例。在該些實施例中,利用積體基底1801,並且具有多個重佈線層、通孔及介電層(各自使用在本文中描述的一或多種方法形成)的重佈線結構1803使用例如焊球及底層填料被貼合至積體基底1801。然而,可利用任何合適的結構。
在實施例中,一種製造半導體元件的方法,所述方法包括:在基底上方形成重佈線層;將第一介電材料施加至所述重佈線層及所述基底,其中所述第一介電材料對第一能量的穿透率大於約0.5%;以及用所述第一能量對所述第一介電材料進行成像。在實施例中,所述第一介電材料的厚度在約20微米與約60微米之間。在實施例中,所述重佈線層的厚度大於或等於約20微米。在實施例中,所述第一介電材料的光活化組分的濃度小於15重量%。在實施例中,所述方法更包括使所述第一介電材料顯影,其中在所述使所述第一介電材料顯影之後,第一開口具有介於約55°與約78°之間的錐角。在實施例中,所述第一介電材料的光活化組分的濃度小於5重量%。在實施例中,所述方法更包括使所述第一介電材料顯影,其中在所述使所述第一介電材料顯影之後,第一開口具有約78°的錐角。
在實施例中,一種製造半導體元件的方法,所述方法包括:將介電塗層施加至載體基底上;藉由將所述介電塗層暴露於經圖案化的能量源來起始所述介電塗層內的交聯,其中在所述起始所述交聯之後,所述介電塗層的第一區具有較所述介電塗層的第二區高的交聯度,所述第一區位於所述第二區與所述載體基底之間;使所述介電塗層顯影以形成介層窗孔;以及在所述介層窗孔中形成導通孔。在實施例中,所述介層窗孔具有介於約55°與約78°之間的錐角。在實施例中,所述錐角為約78°。在實施例中,所述介電塗層的光活化組分濃度小於約15重量%。在實施例中,
所述介電塗層的光活化組分濃度小於約5重量%。在實施例中,所述光活化組分包括胺基及膦基。在實施例中,所述光活化組分包括具有第一碳環及第二碳環的化學製品,所述第一碳環是飽和的,所述第二碳環是不飽和的。
在實施例中,一種半導體元件包括:第一介電層;第一通孔,延伸貫穿所述第一介電層,所述通孔具有介於約55°與約78°之間的錐形側壁角度;第二通孔,延伸貫穿載體基底,所述第二通孔電性連接至所述第一通孔;以及第一半導體晶粒,位於所述載體基底的與所述第一通孔相對的一側上,所述第一半導體晶粒電性連接至所述第二通孔。在實施例中,所述錐形側壁角度為約78°。在實施例中,所述第一介電材料的厚度在約20微米與約60微米之間。在實施例中,所述半導體元件更包括位於所述第一介電層與所述第一通孔之間的重佈線層,所述重佈線層具有大於或等於約20微米的厚度。在實施例中,所述半導體元件更包括與所述第一介電層相鄰的第二介電層,其中所述第二介電層的厚度在約5微米與約7微米之間。
以上內容概述了若干實施例的特徵以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解,其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。熟習此項技術者還應認識到,此類等效構造並不背離本揭露的精神及範圍,而且其可在不背離本揭露的精
神及範圍的條件下對其作出各種改變、代替及變更。
201:第一重佈線層
301:第一鈍化層
401:第一開口
403:虛線框
θ1:第一角度
Claims (10)
- 一種製造半導體元件的方法,所述方法包括:在基底上方形成重佈線層;將第一介電材料施加至所述重佈線層及所述基底,其中所述第一介電材料對第一能量的穿透率大於約0.5%;以及用所述第一能量對所述第一介電材料進行成像。
- 如請求項1所述的製造半導體元件的方法,其中所述第一介電材料的厚度在約20微米與約60微米之間。
- 如請求項2所述的製造半導體元件的方法,其中所述重佈線層的厚度大於或等於約20微米。
- 如請求項1所述的製造半導體元件的方法,其中所述第一介電材料的光活化組分的濃度小於15重量%,且更包括使所述第一介電材料顯影,其中在所述使所述第一介電材料顯影之後,第一開口具有介於約55°與約78°之間的錐角。
- 如請求項1所述的製造半導體元件的方法,其中所述第一介電材料的光活化組分的濃度小於5重量%,且更包括使所述第一介電材料顯影,其中在所述使所述第一介電材料顯影之後,第一開口具有約78°的錐角。
- 一種製造半導體元件的方法,所述方法包括:將介電塗層施加至載體基底上;藉由將所述介電塗層暴露於經圖案化的能量源來起始所述介電塗層內的交聯,其中在所述起始所述交聯之後,所述介電塗層 的第一區具有較所述介電塗層的第二區高的交聯度,所述第一區位於所述第二區與所述載體基底之間;使所述介電塗層顯影以形成介層窗孔;以及在所述介層窗孔中形成導通孔。
- 如請求項6所述的製造半導體元件的方法,其中所述介層窗孔具有介於約55°與約78°之間的錐角,且所述介電塗層的光活化組分濃度小於約15重量%。
- 如請求項6所述的製造半導體元件的方法,其中所述光活化組分包括胺基、膦基或具有第一碳環及第二碳環的化學製品,所述第一碳環是飽和的,所述第二碳環是不飽和的。
- 一種半導體元件,包括:第一介電層;第一通孔,延伸貫穿所述第一介電層,所述通孔具有介於約55°與約78°之間的錐形側壁角度;第二通孔,延伸貫穿載體基底,所述第二通孔電性連接至所述第一通孔;以及第一半導體晶粒,位於所述載體基底的與所述第一通孔相對的一側上,所述第一半導體晶粒電性連接至所述第二通孔。
- 如請求項9所述的半導體元件,其中所述錐形側壁角度為約78°。
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