TWI789414B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI789414B
TWI789414B TW107128148A TW107128148A TWI789414B TW I789414 B TWI789414 B TW I789414B TW 107128148 A TW107128148 A TW 107128148A TW 107128148 A TW107128148 A TW 107128148A TW I789414 B TWI789414 B TW I789414B
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film
region
metal
insulating film
mentioned
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TW107128148A
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TW201916179A (zh
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吉田哲也
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日商瑞薩電子股份有限公司
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Abstract

本發明之課題在於使半導體裝置之可靠性提高。 本發明係於具有半導體基板SB、絕緣層BX及半導體層SM之SOI基板上，形成有具有絕緣膜IF1及高介電常數膜HK1之閘極絕緣膜GF2。高介電常數膜HK1為介電常數高於氧化矽膜之膜，且包含第1金屬及第2金屬。於高介電常數膜HK1中，第1金屬之原子數相對於第1金屬與第2金屬之總原子數之比例為75%以上，且不滿100%。

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造方法，例如關於應用於使用SOI基板之半導體裝置並有效之技術。
作為適合低消耗電力之半導體裝置，有於SOI(Silicon On Insulator：絕緣層上覆矽)基板形成MISFET(Metal Insulator Semiconductor Field Effect Transistor：金屬絕緣半導體場效電晶體)之技術。又，隨著MISFET之微細化，為了使閘極絕緣膜之氧化矽等效膜厚改善，研究將稱為High-k膜之高介電常數膜利用於閘極絕緣膜。
例如，於專利文獻1中，揭示有如下之技術：於形成於SOI基板之MISFET之閘極絕緣膜，作為高介電常數膜，應用氧化鉿(HfO2 )等。
又，於專利文獻2中，揭示有如下之技術：於MISFET之閘極絕緣膜與閘極電極之界面，設置包含鉿(Hf)或鋯(Zr)之金屬層。 [先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2016-18936號公報 [專利文獻2]日本專利特開2007-318012號公報
[發明所欲解決之問題]
作為形成於SOI基板之MISFET之閥值調整方法之一，有藉由高介電常數膜中所包含之金屬之功函數控制閥值之方法。然而，已知此種高介電常數膜係膜中之陷阱能級較氧化矽膜更多，而擔心因高介電常數膜中所包含之金屬之比例，MISFET之可靠性下降。
其他課題與新穎之特徵應可自本說明書之記述及附加圖式而明確。 [解決問題之技術手段]
根據一實施形態，半導體裝置具有：半導體基板；絕緣層，其形成於半導體基板上；半導體層，其形成於絕緣層上；第1閘極絕緣膜，其包含形成於半導體層上之第1絕緣膜、及形成於第1絕緣膜上之高介電常數膜；及第1閘極電極，其形成於第1閘極絕緣膜上。於此處，高介電常數膜為介電常數高於氧化矽膜之膜，且包含第1金屬及第2金屬，於高介電常數膜中，第1金屬之原子數相對於第1金屬及第2金屬之總原子數之比例為75%以上，且不滿100%。
根據一實施形態，半導體裝置之製造方法具備以下步驟：(a)準備半導體基板、形成於上述半導體基板上之絕緣層、及形成於上述絕緣層上之半導體層；(b)於半導體層上，形成第1絕緣膜；(c)於第1絕緣膜上，堆積金屬膜；及(d)對金屬膜實施熱處理。於此處，金屬膜包含第1金屬與第2金屬，且第1金屬之原子數相對於第1金屬及第2金屬之總原子數之比例為75%以上，且不滿100%。
根據一實施形態，半導體裝置之製造方法具有以下步驟：(a)準備半導體基板、形成於半導體基板上之絕緣層、及形成於絕緣層上之半導體層；(b)於半導體層上，形成第1絕緣膜；(c)於第1絕緣膜上，形成第1金屬膜及第2金屬膜；及(d)對第1金屬膜及第2金屬膜，實施熱處理。 [發明之效果]
根據一實施形態，可使半導體裝置之可靠性提高。
於以下實施形態中，為了方便起見，於有必要時分割為複數個部分或實施形態而說明，但除特別明示之情形外，其等並非相互無關係者，而為一方係另一方之一部分或全部之變化例、細節、補充說明等之關係。又，於以下實施形態中，提及要件之數量等(包含個數、數值、量、範圍等)之情形時，除特別明示之情形及原理上明確限定於特定之數量之情形等外，並非限定於該特定之數量者，亦可為特定之數量以上或以下。再者，於以下實施形態中，其構成要件(亦包含要件步驟等)除特別明示之情形及認為原理上明確為必須之情形等外，當然並非為必須者。同樣地，於以下實施形態中，提及構成要件等之形狀、位置關係等時，除特別明示之情形及認為原理上明確並非如此之情形等外，包含實質上與該形狀等近似或類似者等。此點對於上述數值及範圍亦同樣。
以下，基於圖式對實施形態進行詳細說明。另，於用以說明實施形態之全部圖中，對具有同一功能之構件標註同一符號，並省略其重複之說明。又，於以下之實施形態中，除特別必要時以外，原則上不重複同一或同樣之部分之說明。
另，於實施形態所使用之圖式中，亦有為了容易觀察圖式而省略陰影線之情形。
(實施形態1) 圖1顯示本實施形態之半導體裝置即n型MISFET1Tr及p型MISFET2Tr之剖面構造。
本實施形態之半導體裝置具備：區域An，其形成n型MISFET1Tr；區域TAn，其為用於對區域An之井區域PW供電之區域；區域Ap，其形成p型MISFET2Tr；及區域TAp，其為用於對區域Ap之井區域NW供電之區域。
區域An與區域TAn係藉由形成於半導體基板SB之元件分離部STI區劃。井區域PW形成為較元件分離部STI更深，跨越區域An與區域TAn形成。區域Ap與區域TAp係藉由元件分離部STI區劃。井區域NW形成為較元件分離部STI更深，跨越區域Ap與區域TAp形成。
於半導體基板SB上形成有絕緣層BX，於絕緣層BX上形成有半導體層SM。絕緣層BX之厚度係10～20 nm左右，半導體層SM之厚度係10～20 nm左右。又，於供電區域即區域TAn及區域TAp中，去除絕緣層BX及半導體層SM。因此，可經由磊晶層EP，對井區域PW及井區域NW個別地施加電壓。
首先，說明區域An之MISFET1Tr之構造。
於區域An中，於半導體基板SB形成有n型井區域DNW，於井區域DNW內形成有p型井區域PW。藉由該井區域DNW，井區域PW與半導體基板SB電性分離。於與絕緣層BX相接之井區域PW之表面，形成有具有較井區域PW更高之雜質濃度之p型地平面區域(雜質區域)GP1。地平面區域GP1作為MISFET1Tr之背閘極發揮功能，MISFET1Tr之閥值電壓係藉由地平面區域GP1之內部電位調整。
井區域PW及地平面區域GP1係導入硼(B)等p型雜質之區域。又，井區域PW之雜質濃度係5×1017 ～5×1018 /cm3 左右，地平面區域GP1之雜質濃度係1×1018 ～2×1019 /cm3 左右。
於區域An之半導體層SM上，介隔閘極絕緣膜GF1，形成有閘極電極G1。於此處，閘極絕緣膜GF1包含將氧化矽膜作為主體之絕緣膜IF1、與形成於絕緣膜IF1上之高介電常數膜HK1。高介電常數膜HK1為介電常數高於氧化矽膜之膜，且為用於調整MISFET1Tr之閥值之膜，至少包含第1金屬、與不同於第1金屬之第2金屬。於本實施形態中，第1金屬係例如鉿(Hf)，第2金屬係例如鋁(Al)，高介電常數膜HK1係包含Hf、Al及O之膜。
具體而言，本實施形態之高介電常數膜HK1包含Hfx Al(1-x) ON(1＞X≧0.75)或Hfx Al(1-x) O(1＞X≧0.75)。即，於高介電常數膜HK1中，第1金屬之原子數(Hf)相對於第1金屬及第2金屬之總原子數(Hf+Al)之比例係75%以上，且不滿100%。
於閘極電極G1之側面，介隔偏移間隔物OS，形成有側壁間隔物SW。於偏移間隔物OS下及側壁間隔物SW下之半導體層SM，形成有低濃度之n型雜質區域即延伸區域EX1。又，於半導體層SM上之一部分形成有磊晶層EP。於該磊晶層EP，形成有較延伸區域EX1更高濃度之n型雜質區域即擴散區域D1。該等延伸區域EX1及擴散區域D1構成MISFET1Tr之源極區域或汲極區域。
於區域TAn，與區域An同樣，形成有井區域DNW及井區域PW。另，雖於井區域PW之表面形成有地平面區域GP1，但亦可不形成區域TAn之地平面區域GP1。如上所述，由於區域TAn中去除絕緣層BX及半導體層SM，故以與包含地平面區域GP1之井區域PW直接相接之方式，形成有磊晶層EP。於磊晶層EP，形成有p型雜質區域即擴散區域D2。因此，供給至區域TAn之插塞PG之電壓係藉由磊晶層EP及井區域PW，而供給至區域An之地平面區域GP1。
接著，說明區域Ap之MISFET2Tr之構造。
於區域Ap中，於半導體基板SB形成有n型井區域NW。於與絕緣層BX相接之井區域NW之表面，形成有具有較井區域NW更高之雜質濃度之n型地平面區域GP2。地平面區域GP2作為MISFET2Tr之背閘極發揮功能，MISFET2Tr之閥值電壓係藉由地平面區域GP2之內部電位調整。
又，井區域NW及地平面區域GP2為導入砷(As)等n型雜質之區域。又，井區域NW之雜質濃度係5×1017 ～5×1018 /cm3 左右，地平面區域GP2之雜質濃度係1×1018 ～2×1019 /cm3 左右。
於區域Ap之半導體層SM上，介隔閘極絕緣膜GF2，形成有閘極電極G2。於此處，閘極絕緣膜GF2具有包含氧化矽膜等之絕緣膜IF1、與形成於絕緣膜IF1上之高介電常數膜HK1。高介電常數膜HK1為介電常數高於氧化矽膜之膜，且為用於調整MISFET2Tr之閥值之膜，包含上述第1金屬與第2金屬。即，於本實施形態中，閘極絕緣膜GF1及閘極絕緣膜GF2由相同之膜構成。
於閘極電極G2之側面，介隔偏移間隔物OS，形成有側壁間隔物SW。於偏移間隔物OS下及側壁間隔物SW下之半導體層SM，形成有低濃度之p型雜質區域即延伸區域EX2。又，於半導體層SM上之一部分形成有磊晶層EP。於該磊晶層EP，形成有較延伸區域EX2更高濃度之p型雜質區域即擴散區域D2。該等延伸區域EX2及擴散區域D2構成MISFET2Tr之源極區域或汲極區域。
於區域TAp，與區域Ap同樣，形成有井區域NW。另，雖於井區域NW之表面形成有地平面區域GP2，但亦可不形成區域TAp之地平面區域GP2。如上所述，由於區域TAp中去除絕緣層BX及半導體層SM，故以與包含地平面區域GP2之井區域NW直接相接之方式，形成有磊晶層EP。又，於磊晶層EP，形成有n型雜質區域即擴散區域D1。因此，供給至區域TAp之插塞PG之電壓係經由磊晶層EP及井區域NW，供給至區域Ap之地平面區域GP2。
又，於之後說明，形成於區域An之擴散區域D1、與形成於區域TAp之擴散區域D1係由相同步驟形成之n型雜質區域。同樣地，形成於區域Ap之擴散區域D2、與形成於區域TAn之擴散區域D2係由相同步驟形成之p型雜質區域。
於閘極電極G1上、閘極電極G2上及磊晶層EP上，為了降低與插塞PG之接觸電阻，例如形成有包含矽化鎳(NiSi)或矽化鈷(CoSi2 )之矽化物層SI。
於區域An、區域Ap、區域TAn及區域TAp之主表面上，以覆蓋MISFET1Tr及MISFET2Tr之方式形成有層間絕緣膜IL1。作為層間絕緣膜IL1，可使用氧化矽膜之單體膜、或氮化矽膜與於其上形成較厚之氧化矽膜之積層膜等。於層間絕緣膜IL1形成有接觸孔，藉由於接觸孔內埋入以鎢(W)等為主體之導電性膜，而於層間絕緣膜IL1內形成有複數個插塞PG。各插塞PG係經由矽化物層SI，連接於閘極電極G1、閘極電極G2及磊晶層EP。
於埋入有插塞PG之層間絕緣膜IL1上，形成有層間絕緣膜IL2。於層間絕緣膜IL2形成有配線用之槽，藉由於配線用之槽內埋入例如以銅為主成分之導電性膜，而於層間絕緣膜IL2內形成有與插塞PG連接之配線M1。
＜關於本實施形態之半導體裝置之主要特徵＞ MISFET1Tr及MISFET2Tr係稱為SOTB(Silicon-On-Thin-Buried oxide：薄型埋入式氧化物上覆矽)之完全耗盡型之電晶體，且係閘極長為65 nm以下之電晶體。又，為了抑制雜質之偏差引起之閥值變動等，對成為通道區域之半導體層SM，未進行閥值調整用之離子注入。即，成為通道區域之半導體層SM為未導入n型或p型雜質之真性半導體層。或，即使於半導體層SM內導入p型雜質，該雜質濃度亦為1×1013 /cm3 以下。
此種電晶體係以0.75 V左右之超低電壓驅動，流動於各半導體層SM(通道區域)之電流之控制不僅使用施加於閘極電極G1及閘極電極G2之電壓而進行，亦使用施加於井區域PW及井區域NW之電壓而進行。即，MISFET1Tr係藉由對閘極電極G1及井區域PW個別地供給電壓而驅動。又，MISFET2Tr係藉由對閘極電極G2及井區域NW個別地供給電壓而驅動。
於本實施形態中，由於成為通道區域之半導體層SM為無摻雜物，故MISFET1Tr之閥值電壓主要藉由地平面區域GP1所包含之雜質之雜質濃度、與高介電常數膜HK1所包含之金屬之總原子數設定。同樣地，MISFET2Tr之閥值電壓主要藉由地平面區域GP2所包含之雜質之雜質濃度、與高介電常數膜HK1所包含之金屬之總原子數設定。
以下，使用圖2說明本申請案發明者進行之關於高介電常數膜HK1所含之金屬之比例之研究結果。
首先，本申請案發明者研究了為供n型MISFET1Tr使用而對高介電常數膜HK1導入鋁(Al)，但判定於p型MISFET2Tr中閥值電壓過低。如上所述，閥值電壓雖於地平面區域GP2亦可於某種程度上進行調整，但因地平面區域GP2由雜質區域構成，故不適用於更微細地調整閥值電壓。因此，雖期望藉由高介電常數膜HK1內之金屬進行閥值電壓之微調整，但根據本申請案發明者之研究，可明確知道鋁並非最適於p型MISFET2Tr。
因此，本申請案發明者研究了對高介電常數膜HK1不僅導入鋁，亦導入鉿(Hf)。藉由對高介電常數膜HK1亦導入鉿，可將p型MISFET2Tr之閥值電壓設計為適當值。此時，雖於n型MISFET1Tr中閥值電壓略微下降，但其變化量為適用範圍內。
又，根據本申請案發明者之研究可明確知道，於p型MISFET2Tr中，因高介電常數膜HK1中之鋁，NBTI(Negative Bias Temperature Instability：負偏壓溫度不穩定性)劣化。
圖2係本申請案發明者之實驗資料，藉由高介電常數膜HK1所含之第1金屬(Hf)及第2金屬(Al)之比例，顯示p型MISFET2Tr之NBTI之劣化量。橫軸顯示第1金屬之原子數(Hf)相對於第1金屬與第2金屬之總原子數(Hf+Al)之比例，縱軸係以相對值顯示p型MISFET2Tr之NBTI之劣化量。即，以縱軸之1.0作為基準，大於1.0之值表示NBTI之劣化量較大，MISFET2Tr之可靠性下降，小於1.0之值表示NBTI之劣化量較小，MISFET2Tr之可靠性提高。
如圖2所示，高介電常數膜HK1所含之第1金屬(Hf)之比例越大，高介電常數膜HK1所含之第2金屬(Al)之比例越小，判定NBTI越得到改善。尤其，當第1金屬之原子數(Hf)相對於第1金屬與第2金屬之總原子數(Hf+Al)之比例為75%以上時，便判定NBTI得到改善。
因此，期望將高介電常數膜HK1設為Hfx Al(1-x) ON(1＞X≧0.75)、或Hfx Al(1-x) O(1＞X≧0.75)。換言之，於高介電常數膜HK1中，期望將第1金屬之原子數(Hf)相對於第1金屬及第2金屬之總原子數(Hf+Al)之比例設為75%以上，且不滿100%。若高介電常數膜HK1為此種構成，便可改善p型MISFET2Tr之NBTI。因此，本實施形態之半導體裝置可將n型MISFET1Tr及p型MISFET2Tr之閥值電壓設計為最適值，且可使p型MISFET2Tr之可靠性提高。
＜關於本實施形態之半導體裝置之製造方法＞ 以下，使用圖3～圖11說明本實施形態之半導體裝置之製造方法。
於圖3，顯示所謂SOI基板，其具有：半導體基板SB，其為支持基板；絕緣層BX，其形成於半導體基板SB上；及半導體層SM，其形成於絕緣層BX之上。
半導體基板SB較佳包含具有1～10 Ωcm左右之電阻率之單晶矽，包含例如p型單晶矽。絕緣層BX包含例如氧化矽，絕緣層BX之厚度係例如10～20 nm左右。半導體層SM較佳包含具有1～10 Ωcm左右之電阻率之單晶矽，半導體層SM之厚度係例如10～20 nm左右。另，半導體層SM係藉由離子注入等未導入n型或p型之雜質之真性半導體層。或，即使於半導體層SM內導入p型雜質，其雜質濃度亦為1×1013 /cm3 以下。
於以下說明準備此種SOI基板之步驟之一例。SOI基板能夠以例如SIMOX(Separation by IMplanted OXygen：植氧分離)法製造。於SIMOX法中，於包含矽(Si)之半導體基板以高能量離子注入氧(O2 )，通過其後之熱處理使矽與氧結合，且於較半導體基板之表面略深之位置形成包含氧化矽之絕緣層BX。於該情形時，殘存於絕緣層BX上之矽之薄膜成半導體層SM，絕緣層BX下之半導體基板成半導體基板SB。又，亦可藉由貼合法形成SOI基板。於貼合法中，例如，於將包含矽之第1半導體基板之表面氧化而形成絕緣層BX後，藉由於該第1半導體基板於高溫下壓著包含矽之第2半導體基板而貼合，其後，將第2半導體基板薄膜化。於該情形時，殘存於絕緣層BX上之第2半導體基板之薄膜成為半導體層SM，絕緣層BX下之第1半導體基板成為半導體基板SB。進而，亦可使用其他方法例如智慧切割製程等，製造SOI基板。
接著，形成貫通半導體層SM及絕緣層BX且到達半導體基板SB之槽，且藉由於槽內埋入絕緣膜而形成元件分離部STI。區域An、區域Ap、區域TAn及區域TAp由元件分離部STI彼此分離。
接著，藉由光微影法及離子注入法，於區域An及區域TAn之半導體基板SB形成n型井區域DNW，於井區域DNW內形成p型井區域PW，於井區域PW內形成p型地平面區域GP1。
接著，藉由光微影法及離子注入法，於區域Ap及區域TAp之半導體基板SB形成n型井區域NW，於井區域NW內形成n型地平面區域GP2。
接著，藉由光微影法及乾蝕刻法，選擇性地去除區域TAn及區域TAp之半導體層SM，使區域TAn及區域TAp之絕緣層BX露出。
接著，如圖4所示，藉由例如熱氧化法，於區域An及區域Ap之半導體層SM上，形成包含例如氧化矽膜之絕緣膜IF1。絕緣膜IF1之膜厚係2～3 nm左右。該絕緣膜IF1於之後成為MISFET1Tr之閘極絕緣膜GF1之一部分及MISFET2Tr之閘極絕緣膜GF2之一部分。
接著，根據需要，亦可對絕緣膜IF1於包含例如氮之環境氛圍中進行電漿處理。藉由該電漿處理，將絕緣膜IF1之表面氮化。即，導入至較絕緣膜IF1之膜厚之一半更靠上部之氮濃度大於導入至較絕緣膜IF1之膜厚之一半更靠下部之氮濃度。換言之，絕緣膜IF1之下部為氧化矽膜，絕緣膜IF1之上部成為氮氧化矽膜。
藉由進行此種電漿處理，可獲得如以下之效果。例如，雖於後續之步驟形成閘極電極G1、G2，但因其後之製造步驟中之熱處理，有閘極電極G1、G2中之雜質擴散至半導體層SM之虞。於此處，藉由進行上述電漿處理，使絕緣膜IF1之表面氮化，可防止導入至例如閘極電極G2之硼(B)等p型雜質自閘極電極G2中向半導體層SM擴散。又，藉由包含氧化矽膜之絕緣膜IF1之表面氮化，可使閘極絕緣膜GF1及閘極絕緣膜GF2之介電常數提高。
於之後說明，於本實施形態中，進行上述電漿處理之情形時，高介電常數膜HK1成為Hfx Al(1-x) ON(1＞X≧0.75)，未進行上述電漿處理之情形時，高介電常數膜HK1成為Hfx Al(1-x) O(1＞X≧0.75)。
接著，如圖5所示，藉由濺鍍法使金屬膜MT1堆積於區域An、區域Ap、區域TAn及區域TAp。藉此，於區域An及區域Ap中，於絕緣膜IF1上形成金屬膜MT1。即，於區域An及區域Ap之各者中，對絕緣膜IF1添加(供給)構成金屬膜MT1之材料。本實施形態之金屬膜MT1係包含第1金屬(Hf)與第2金屬(Al)之膜，其膜厚係3 nm左右。作為金屬膜MT1之形成方法，例如首先於濺鍍裝置內之第1腔室內，使鉿(Hf)堆積。接著，於相同濺鍍裝置內之第2腔室內，使鋁(Al)堆積。使鉿與鋁堆積之順序可為任一者在前。又，第1金屬之原子數(Hf)相對於第1金屬及第2金屬之總原子數(Hf+Al)之比例為75%以上，且不足100%。
接著，對金屬膜MT1實施例如700℃左右之熱處理，且使絕緣膜IF1與金屬膜MT1反應，藉此形成高介電常數膜HK1。於本實施形態中，絕緣膜IF1之表面所包含之氧化矽(SiO2 )、與金屬膜MT1所包含之鉿(Hf)及鋁(Al)反應，作為高介電常數膜HK1形成Hfx Al(1-x) O膜。另，對絕緣膜IF1於氮之環境氛圍中進行電漿處理之情形時，絕緣膜IF1之表面所包含之氮氧化矽(SiON)、與金屬膜MT1所包含之鉿(Hf)及鋁(Al)反應，作為高介電常數膜HK1形成Hfx Al(1-x) ON膜。
又，亦可不個別地進行此種熱處理步驟，而利用附加於後述之其他步驟之熱，使絕緣膜IF1與金屬膜MT1反應。
圖6顯示緊接圖5之製造步驟，且顯示閘極電極G1、閘極電極G2、蓋膜CP、閘極絕緣膜GF1及閘極絕緣膜GF2之形成步驟。
首先，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，藉由例如CVD(Chemical Vapor Deposition：化學氣相沉積)法，作為閘極電極用之導電性膜，堆積例如多晶矽膜。另，於該CVD法中，施加600～700℃左右之熱處理。接著，使用光微影法及離子注入法，對各區域之導電性膜導入雜質。於此處，於區域An及區域TAn之導電性膜導入n型雜質，於區域Ap及區域TAp之導電性膜導入p型雜質。
另，構成各閘極電極之導電性膜不限定於多晶矽膜，亦可為金屬膜、或多晶矽膜與金屬膜之積層膜。
接著，於導電性膜上，藉由例如CVD法，作為閘極電極上之蓋膜用之絕緣膜，堆積例如氮化矽膜。另，於該CVD法中，施加600～700℃左右之熱處理。
於此處，亦可不個別地進行於圖6之前說明之用於使絕緣膜IF1與金屬膜MT1反應之熱處理步驟，而利用附加於圖6等其他步驟之熱。例如，亦可藉由於上述閘極電極用之導電性膜之成膜時、及於上述蓋膜用之絕緣膜之成膜時施加之熱處理，使絕緣膜IF1與金屬膜MT1反應，而形成高介電常數膜HK1。又，絕緣膜IF1與金屬膜MT1之反應亦可進而藉由於後續之步驟，即偏移間隔物OS形成步驟、虛設側壁間隔物DSW形成步驟、磊晶層EP形成步驟、側壁間隔物SW形成步驟、及擴散區域D1、D2形成後之活性化處理中實施之熱處理而進行。即，假設藉由於閘極電極用之導電性膜之成膜時、及蓋膜用之絕緣膜之成膜時施加之熱處理，絕緣膜IF1與金屬膜MT1未完全地反應，仍可藉由於後續之各步驟施加之熱處理，使絕緣膜IF1與金屬膜MT1反應。最終，於圖9所示之矽化物層SI之形成步驟後，絕緣膜IF1與金屬膜MT1之反應結束，作為高介電常數膜HK1形成有Hfx Al(1-x) ON膜或Hfx Al(1-x) ON膜。
接著，使用光微影法及乾蝕刻法，將上述絕緣膜與上述導電性膜圖案化。藉此，如圖6所示，於區域An形成閘極電極G1，於區域Ap形成閘極電極G2。又，於各閘極電極上分別形成蓋膜CP。接著，藉由去除自各閘極電極露出之高介電常數膜HK1(金屬膜MT1)及絕緣膜IF1，而於區域An之閘極電極G1下及區域Ap之閘極電極G2下，殘留高介電常數膜HK1、與絕緣膜IF1。另，於高介電常數膜HK1(金屬膜MT1)之去除步驟中，使用包含硝酸或硫酸之水溶液，於絕緣膜IF1之去除步驟中，使用包含氟酸之水溶液。又，於去除絕緣膜IF1時，亦去除殘留於區域TAn及區域TAp之絕緣層BX。
藉由以上，於區域An之閘極電極G1下，形成包含高介電常數膜HK1及絕緣膜IF1之閘極絕緣膜GF1，於區域Ap之閘極電極G2下，形成包含高介電常數膜HK1及絕緣膜IF1之閘極絕緣膜GF2。
圖7顯示偏移間隔物OS、虛設側壁間隔物DSW及磊晶層EP之形成步驟。
首先，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，藉由例如CVD法，形成包含例如氧化矽膜之絕緣膜。另，於該CVD法中，施加600～700℃左右之熱處理。接著，藉由對該絕緣膜進行各向異性蝕刻，而於閘極電極G1及閘極電極G2之各者之側面，形成偏移間隔物OS。此時，於區域TAn及區域TAp中，藉由各向異性蝕刻，去除偏移間隔物OS用之絕緣膜，露出半導體基板SB。
接著，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，藉由例如CVD法，形成包含例如氮化矽膜之絕緣膜。另，於該CVD法中，施加600～700℃左右之熱處理。接著，藉由對該絕緣膜進行各向異性蝕刻，而於閘極電極G1及閘極電極G2之各者之側面，介隔偏移間隔物OS形成虛設側壁間隔物DSW。此時，於區域TAn及區域TAp中，藉由各向異性蝕刻，去除虛設側壁間隔物DSW用之絕緣膜，露出半導體基板SB。
接著，藉由磊晶生長法，於區域An及區域Ap之半導體層SM上、以及區域TAn及區域TAp之半導體基板SB上，形成包含例如單晶矽之磊晶層EP(半導體層EP)。另，於該磊晶生長法中，施加650～750℃左右之熱處理。半導體層EP之膜厚係20 nm～40 nm左右。此時，由於閘極電極G1及閘極電極G2以蓋膜CP覆蓋，故於閘極電極G1及閘極電極G2上未形成磊晶層EP。
另，磊晶層EP與半導體層SM為相同材料故而一體化，於本實施形態中，為易於理解發明，以箭頭顯示磊晶層EP，以虛線顯示磊晶層EP與半導體層SM之邊界。
圖8顯示虛設側壁間隔物DSW及蓋膜CP之去除步驟、與延伸區域EX1、EX2之形成步驟。
首先，藉由以難以削減偏移間隔物OS之條件進行蝕刻處理，而於區域An及區域Ap中，去除虛設側壁間隔物DSW及蓋膜CP。又，由於虛設側壁間隔物DSW及蓋絕緣膜CP由相同之材料形成，故可同時去除該等。因此，因無需進行掩膜之追加，故可簡化製造步驟。
接著，使用光微影法及離子注入法，於區域An中，於閘極電極G1之兩側之半導體層SM及磊晶層EP形成n型延伸區域(雜質區域)EX1，於區域Ap中，於閘極電極G2之兩側之半導體層SM及磊晶層EP形成p型延伸區域(雜質區域)EX2。延伸區域EX1構成MISFET1Tr之源極區域之一部分或汲極區域之一部分，延伸區域EX2構成MISFET2Tr之源極區域之一部分或汲極區域之一部分。
另，延伸區域EX1亦形成於區域TAp之磊晶層EP之表面，延伸區域EX2形成於區域TAn之磊晶層EP之表面。然而，於區域TAp及區域TAn，亦可不形成延伸區域EX1及延伸區域EX2。
圖9顯示側壁間隔物SW、擴散區域D1、D2、及矽化物層SI之形成步驟。
首先，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，藉由例如CVD法，形成包含例如氮化矽膜之絕緣膜。另，於該CVD法中，施加600～700℃左右之熱處理。接著，藉由對該絕緣膜進行各向異性蝕刻，而於閘極電極G1及閘極電極G2之各者之側面，介隔偏移間隔物OS形成側壁間隔物SW。
接著，使用光微影法及離子注入法，於區域An之磊晶層EP及半導體層SM、以及區域TAp之磊晶層EP，形成n型擴散區域(雜質區域)D1，於區域Ap之磊晶層EP及半導體層SM、以及區域TAn之磊晶層EP，形成p型擴散區域(雜質區域)D2。
於區域An中，n型擴散區域D1具有較延伸區域EX1更高之雜質濃度，且與延伸區域EX1連接，構成MISFET1Tr之源極區域之一部分或汲極區域之一部分。
於區域Ap中，p型擴散區域D2具有較延伸區域EX2更高之雜質濃度，且與延伸區域EX2連接，構成MISFET2Tr之源極區域之一部分或汲極區域之一部分。
接著，出於使延伸區域EX1、EX2及擴散區域D1、D2所包含之雜質活化之目的，對半導體基板SB實施1050℃左右之熱處理。
接著，藉由自對準矽化物(Salicide：Self Aligned Silicide)技術，於擴散區域D1、擴散區域D2、閘極電極G1及閘極電極G2之各者之上表面上，形成低電阻之矽化物層SI。
矽化物層SI具體而言可如下形成。首先，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，形成矽化物層SI形成用之金屬膜。該金屬膜包含例如鈷、鎳或鎳鉑合金。接著，藉由對半導體基板SB實施600～700℃左右之熱處理，而使擴散區域D1、擴散區域D2、閘極電極G1及閘極電極G2與金屬膜反應。藉此，於擴散區域D1、擴散區域D2、閘極電極G1及閘極電極G2之各者之上表面上，形成矽化物層SI。其後，去除未反應之金屬膜。
藉由以上，於區域An形成MISFET1Tr，於區域Ap形成MISFET2Tr。
於圖9之製造步驟後，藉由形成層間絕緣膜IL1、IL2、插塞PG及配線M1，製造圖1所示之半導體裝置。
首先，以覆蓋區域An、區域Ap、區域TAn及區域TAp之方式，形成層間絕緣膜IL1。作為層間絕緣膜IL1，可使用氧化矽膜之單體膜，或氮化矽膜與於其上形成較厚之氧化矽膜之積層膜等。於層間絕緣膜IL1之形成後，根據需要，亦可通過CMP(Chemical Mechanical Polishing：化學機械研磨)法研磨層間絕緣膜IL1之上表面。
接著，藉由光微影法及乾蝕刻法，於層間絕緣膜IL1內形成接觸孔，藉由於接觸孔內埋入以鎢(W)等為主體之導電性膜，而於層間絕緣膜IL1內形成複數個插塞PG。形成於各區域之插塞PG經由矽化物層SI，連接於擴散區域D1、D2。另，閘極電極G1、G2亦連接於插塞PG，但於本實施形態中省略其圖示。
接著，於埋入有插塞PG之層間絕緣膜IL1上形成層間絕緣膜IL2。其後，於層間絕緣膜IL2形成配線用之槽後，藉由於配線用之槽內埋入例如以銅為主成分之導電性膜，而於層間絕緣膜IL2內形成與插塞PG連接之配線M1。該配線M1之構造稱為所謂鑲嵌(Damascene)配線構造。
其後，藉由雙鑲嵌(Dual Damascene)法等，形成第2層以後之配線，此處省略其說明及圖示。又，配線M1及較配線M1上層之配線並不限定於鑲嵌配線構造，亦可將導電性膜圖案化而形成，亦可設為例如鎢配線或鋁配線。
如以上所述，製造本實施形態之半導體裝置。
(實施形態2) 以下，使用圖10～圖12說明實施形態2之半導體裝置及其製造方法。另，於以下之說明中，主要說明與實施形態1之不同點。
首先，於實施形態1中，作為閘極絕緣膜GF1之一部分及閘極絕緣膜GF2之一部分，利用相同之高介電常數膜HK1。與此相對，於實施形態2中，作為閘極絕緣膜GF1之一部分利用高介電常數膜HK2，作為閘極絕緣膜GF2之一部分則利用包含與高介電常數膜HK2不同材料之高介電常數膜HK3。
圖10顯示緊接實施形態1之圖4之製造步驟。於圖4之製造步驟之結束時點，於區域An及區域Ap之半導體層SM上，形成有絕緣膜IF1。又，於絕緣膜IF1之表面，根據需要，於氮之環境氛圍中實施電漿處理。
自該狀態，如圖10所示，以將區域An及區域TAn開口，且覆蓋區域Ap及區域TAp之方式，形成包含例如光阻膜之掩膜圖案PR1。又，掩膜圖案PR1並不限定於光阻膜，亦可為經圖案化之氮化矽膜等絕緣膜。
接著，將掩膜圖案PR1作為掩膜，藉由濺鍍法，使包含例如鋁(Al)之金屬膜MT2堆積於區域An及區域TAn。藉此，於區域An中，於絕緣膜IF1上形成金屬膜MT2。即，對位於區域An內之絕緣膜IF1，添加(供給)構成金屬膜MT2之鋁。另，金屬膜MT2之膜厚係3 nm左右。其後，掩膜圖案PR1係藉由灰化等蝕刻處理去除。
接著，如圖11所示，以將區域Ap及區域TAp開口，且覆蓋區域An及區域TAn之方式，形成包含例如光阻膜之掩膜圖案PR2。又，掩膜圖案PR2並不限定於光阻膜，亦可為經圖案化之氮化矽膜等絕緣膜。
接著，將掩膜圖案PR2作為掩膜，藉由濺鍍法，使包含例如鉿(Hf)之金屬膜MT3，作為與金屬膜MT2不同之金屬膜堆積於區域Ap及區域TAp。藉此，於區域Ap中，於絕緣膜IF1上形成金屬膜MT3。即，對位於區域Ap內之絕緣膜IF1，添加(供給)構成金屬膜MT3之鉿。另，金屬膜MT3之膜厚係3 nm左右。其後，掩膜圖案PR2係藉由灰化等蝕刻處理去除。
另，亦可使圖10及圖11所示之製造步驟之順序相反。即，亦可首先於區域Ap形成金屬膜MT3，其後，於區域An形成金屬膜MT2。
接著，如圖12所示，以與實施形態1相同之方法，形成閘極電極G1、閘極電極G2、蓋膜CP、閘極絕緣膜GF1及閘極絕緣膜GF2。藉此，於區域An之閘極電極G1下，形成包含高介電常數膜HK2及絕緣膜IF1之閘極絕緣膜GF1，於區域Ap之閘極電極G2下，形成包含高介電常數膜HK3及絕緣膜IF1之閘極絕緣膜GF2。
即，與實施形態1同樣，藉由對金屬膜MT2及金屬膜MT3實施熱處理，而於區域An中金屬膜MT2與絕緣膜IF1反應，形成高介電常數膜HK2，於區域Ap中金屬膜MT3與絕緣膜IF1反應，形成高介電常數膜HK3。於實施形態2中，高介電常數膜HK2係AlO2 膜或AlON膜，高介電常數膜HK3係HfO2 膜或HfON膜。
又，與實施形態1同樣，亦可不個別地進行上述熱處理步驟，而利用添加於閘極電極G1、G2之形成步驟及蓋膜CP之形成步驟等其他步驟之熱處理。
以後之製造步驟與實施形態1之圖7以後之說明相同。
如此，於實施形態2中，MISFET1Tr之閘極絕緣膜GF1包含鋁(Al)，但不包含鉿(Hf)。又，MISFET2Tr之閘極絕緣膜GF2包含鉿(Hf)，但不包含鋁(Al)。因此，實施形態2之半導體裝置與實施形態1之半導體裝置相比，於n型MISFET1Tr中，可防止鉿引起之閥值電壓之降低，於p型MISFET2Tr中，可防止鋁引起之閥值電壓之降低，且可防止鋁引起之NBTI之劣化。
以上，雖對藉由本申請案發明者完成之發明基於其實施形態進行具體說明，但本發明並非限定於上述實施形態者，當然可於不脫離其主旨之範圍內進行各種變更。
此外，以下記載上述實施形態所記載之內容之一部分。
[附記1] 一種半導體裝置，其係具備形成第1導電型之第1MISFET之第1區域、及形成與上述第1導電型相反之導電型之第2導電型之第2MISFET之第2區域的半導體裝置，且具有： 絕緣層，其於上述第1區域及上述第2區域中，形成於半導體基板上； 半導體層，其形成於上述絕緣層上； 第1絕緣膜，其形成於上述半導體層上； 第1高介電常數膜，其形成於位於上述第1區域之上述第1絕緣膜上，且包含第1金屬； 第2高介電常數膜，其形成於位於上述第2區域之上述第1絕緣膜上，且包含與上述第1金屬不同之第2金屬； 上述第1MISFET之第1閘極電極，其形成於上述第1高介電常數膜上；及 上述第2MISFET之第2閘極電極，其形成於上述第2高介電常數膜上；且 上述第1高介電常數膜係不包含上述第2金屬之膜； 上述第2高介電常數膜係不包含上述第1金屬之膜； 上述第1MISFET之第1閘極絕緣膜包含上述第1區域之上述第1絕緣膜及上述第1高介電常數膜； 上述第2MISFET之第2閘極絕緣膜包含上述第2區域之上述第1絕緣膜及上述第2高介電常數膜。
[附記2] 如附記1記載之半導體裝置，其中 上述第1導電型係p型； 上述第2導電型係n型； 上述第1金屬係Hf； 上述第2金屬係Al； 上述第1高介電常數膜係包含Hf及O之膜； 上述第2高介電常數膜係包含Al及O之膜。
[附記3] 如附記2記載之半導體裝置，其中 於上述第1區域之上述半導體基板內，形成n型第1井區域； 於上述第1井區域內，且與上述絕緣層相接之位置，形成具有較上述第1井區域更高之雜質濃度之n型第1雜質區域； 上述第1MISFET之閥值電壓係藉由上述第1雜質區域內之雜質濃度、與上述第1高介電常數膜中之上述第1金屬設定； 於上述第2區域之上述半導體基板內，形成p型第2井區域； 於上述第2井區域內，且與上述絕緣層相接之位置，形成具有較上述第2井區域更高之雜質濃度之p型之第2雜質區域；且 上述第2MISFET之閥值電壓係藉由上述第2雜質區域內之雜質濃度、與上述第2高介電常數膜中之上述第2金屬設定。
[附記4] 如附記3記載之半導體裝置，其中 上述第1雜質區域之雜質濃度係1×1018 ～2×1019 /cm3 ； 上述第2雜質區域之雜質濃度係1×1018 ～2×1019 /cm3 。
[附記5] 如附記4記載之半導體裝置，其中 上述第1閘極電極下之上述半導體層、及上述第2閘極電極下之上述半導體層係真性半導體層，或，為導入1×1013 /cm3 以下之p型雜質之半導體層。
[附記6] 如附記2記載之半導體裝置，其中 導入至較上述第1絕緣膜之膜厚之一半更靠上部之氮濃度大於導入至較上述第1絕緣膜之膜厚之一半更靠下部之氮濃度； 上述第1高介電常數膜係包含Hf、O及N之膜； 上述第2高介電常數膜係包含Al、O及N之膜。
1Tr‧‧‧MISFET2Tr‧‧‧MISFETAn‧‧‧區域Ap‧‧‧區域BX‧‧‧絕緣層CP‧‧‧蓋膜D1‧‧‧擴散區域(雜質區域)D2‧‧‧擴散區域(雜質區域)DNW‧‧‧井區域DSW‧‧‧虛設側壁間隔物EP‧‧‧磊晶層(半導體層)EX1‧‧‧延伸區域(雜質區域)EX2‧‧‧延伸區域(雜質區域)G1‧‧‧閘極電極G2‧‧‧閘極電極GF1‧‧‧閘極絕緣膜GF2‧‧‧閘極絕緣膜GP1‧‧‧地平面區域(雜質區域)GP2‧‧‧地平面區域(雜質區域)HK1～HK3‧‧‧高介電常數膜IF1‧‧‧絕緣膜IL1‧‧‧層間絕緣膜IL2‧‧‧層間絕緣膜M1‧‧‧配線MT1～MT3‧‧‧金屬膜NW‧‧‧井區域OS‧‧‧偏移間隔物PG‧‧‧插塞PW‧‧‧井區域PR1‧‧‧掩膜圖案PR2‧‧‧掩膜圖案SB‧‧‧半導體基板SI‧‧‧矽化物層SM‧‧‧半導體層STI‧‧‧元件分離部SW‧‧‧側壁間隔物TAn‧‧‧區域TAp‧‧‧區域
圖1係顯示實施形態1之半導體裝置之剖視圖。 圖2係本申請案發明者之實驗資料。 圖3係顯示實施形態1之半導體裝置之製造步驟之剖視圖。 圖4係顯示緊接圖3之半導體裝置之製造步驟之剖視圖。 圖5係顯示緊接圖4之半導體裝置之製造步驟之剖視圖。 圖6係顯示緊接圖5之半導體裝置之製造步驟之剖視圖。 圖7係顯示緊接圖6之半導體裝置之製造步驟之剖視圖。 圖8係顯示緊接圖7之半導體裝置之製造步驟之剖視圖。 圖9係顯示緊接圖8之半導體裝置之製造步驟之剖視圖。 圖10係顯示實施形態2之半導體裝置之製造步驟之剖視圖。 圖11係顯示緊接圖10之半導體裝置之製造步驟之剖視圖。 圖12係顯示緊接圖11之半導體裝置之製造步驟之剖視圖。
1Tr‧‧‧MISFET
2Tr‧‧‧MISFET
An‧‧‧區域
Ap‧‧‧區域
BX‧‧‧絕緣層
D1‧‧‧擴散區域(雜質區域)
D2‧‧‧擴散區域(雜質區域)
DNW‧‧‧井區域
EP‧‧‧磊晶層(半導體層)
EX1‧‧‧延伸區域(雜質區域)
EX2‧‧‧延伸區域(雜質區域)
G1‧‧‧閘極電極
G2‧‧‧閘極電極
GF1‧‧‧閘極絕緣膜
GF2‧‧‧閘極絕緣膜
GP1‧‧‧地平面區域(雜質區域)
GP2‧‧‧地平面區域(雜質區域)
HK1‧‧‧高介電常數膜
IF1‧‧‧絕緣膜
IL1‧‧‧層間絕緣膜
IL2‧‧‧層間絕緣膜
M1‧‧‧配線
NW‧‧‧井區域
OS‧‧‧偏移間隔物
PG‧‧‧插塞
PW‧‧‧井區域
SB‧‧‧半導體基板
SI‧‧‧矽化物層
SM‧‧‧半導體層
STI‧‧‧元件分離部
SW‧‧‧側壁間隔物
TAn‧‧‧區域
TAp‧‧‧區域

Claims (17)

  1. 一種半導體裝置，其包含：半導體基板；絕緣層，其形成於上述半導體基板上；半導體層，其形成於上述絕緣層上；第1MISFET之第1閘極絕緣膜，其包含形成於上述半導體層上之第1絕緣膜、及形成於上述第1絕緣膜上之高介電常數膜；及上述第1MISFET之第1閘極電極，其形成於上述第1閘極絕緣膜上；且上述高介電常數膜為介電常數高於氧化矽膜之膜，且包含第1金屬、及不同於上述第1金屬之第2金屬；於上述高介電常數膜中，上述第1金屬之原子數相對於上述第1金屬與上述第2金屬之總原子數之比例為75%以上，且不滿100%；上述第1金屬係Hf；上述第2金屬係Al。
  2. 如請求項1之半導體裝置，其中上述高介電常數膜係包含Hf、Al及O之膜。
  3. 如請求項2之半導體裝置，其中上述第1MISFET係p型之MISFET。
  4. 如請求項3之半導體裝置，其中上述半導體裝置包含形成上述第1MISFET之第1區域、及形成n型第2MISFET之第2區域；且上述第2MISFET包含：第2閘極絕緣膜，其於上述第2區域中，包含形成於上述半導體層上之上述第1絕緣膜、及形成於上述第1絕緣膜上之上述高介電常數膜；及第2閘極電極，其形成於上述第2閘極絕緣膜上。
  5. 如請求項4之半導體裝置，其中於上述第1區域之上述半導體基板內，形成n型第1井區域；於上述第1井區域內，且與上述絕緣層相接之位置，形成具有較上述第1井區域高之雜質濃度之n型第1雜質區域；上述第1MISFET之閥值電壓，係藉由上述第1雜質區域內之雜質濃度、及上述高介電常數膜中之上述第1金屬與上述第2金屬之總原子數而設定；於上述第2區域之上述半導體基板內，形成p型之第2井區域；於上述第2井區域內，且與上述絕緣層相接之位置，形成具有較上述第2井區域高之雜質濃度之p型第2雜質區域；上述第2MISFET之閥值電壓，係藉由上述第2雜質區域內之雜質濃度、及上述高介電常數膜中之上述第1金屬與上述第2金屬之原子數而設定。
  6. 如請求項5之半導體裝置，其中 上述第1雜質區域之雜質濃度係1×1018~2×1019/cm3；上述第2雜質區域之雜質濃度係1×1018~2×1019/cm3。
  7. 如請求項6之半導體裝置，其中上述第1閘極電極下之上述半導體層、及上述第2閘極電極下之上述半導體層係本質半導體層，或為導入1×1013/cm3以下之p型雜質之半導體層。
  8. 如請求項2之半導體裝置，其中導入至較上述第1絕緣膜之膜厚之一半上部之氮濃度，大於導入至較上述第1絕緣膜之膜厚之一半下部之氮濃度；上述高介電常數膜係包含Hf、Al、O及N之膜。
  9. 一種半導體裝置之製造方法，其包含以下步驟：(a)準備半導體基板、形成於上述半導體基板上之絕緣層、及形成於上述絕緣層上之半導體層；(b)於上述半導體層上，形成第1絕緣膜；(c)於上述第1絕緣膜上，藉由濺鍍法使金屬膜堆積；及(d)藉由對上述金屬膜實施熱處理，使上述金屬膜與上述第1絕緣膜反應；且上述金屬膜包含第1金屬、及不同於上述第1金屬之第2金屬；上述第1金屬之原子數，相對於上述第1金屬與上述第2金屬之總原子數之比例係75%以上，且不滿100%； 上述第1金屬係Hf；上述第2金屬係Al。
  10. 如請求項9之半導體裝置之製造方法，其中於上述(d)步驟中，藉由使上述金屬膜與上述第1絕緣膜反應，而於上述第1絕緣膜上，形成具有較氧化矽膜高之介電常數之高介電常數膜；p型之第1MISFET之第1閘極絕緣膜，包含上述第1絕緣膜與上述高介電常數膜。
  11. 如請求項10之半導體裝置之製造方法，其中上述半導體裝置包含形成上述第1MISFET之第1區域、及形成n型第2MISFET之第2區域；且於上述(b)步驟中，於上述第1區域及上述第2區域中，於上述半導體層上形成第1絕緣膜；於上述(c)步驟中，於上述第1區域及上述第2區域中，於上述第1絕緣膜上形成上述金屬膜；於上述(d)步驟中，於上述第1區域及上述第2區域中，於上述第1絕緣膜上形成上述高介電常數膜；上述第2MISFET之第2閘極絕緣膜，包含上述第1絕緣膜及上述高介電常數膜。
  12. 如請求項9之半導體裝置之製造方法，其進而包含如下步驟：於上述(b)步驟後且上述(c)步驟前，於包含氮之環境氛圍中，對上述 第1絕緣膜之表面實施電漿處理。
  13. 如請求項9之半導體裝置之製造方法，其中上述(d)步驟為於上述金屬膜上形成導電性膜之步驟；上述(d)步驟之上述熱處理，係於上述導電性膜之形成時施加之熱處理。
  14. 一種半導體裝置之製造方法，其係包含形成第1導電型之第1MISFET之第1區域、及形成與上述第1導電型相反之導電型之第2導電型之第2MISFET之第2區域的半導體裝置之製造方法，且具有以下步驟：(a)準備半導體基板、形成於上述半導體基板上之絕緣層、及形成於上述絕緣層上之半導體層；(b)於上述第1區域及上述第2區域中，於上述半導體層上，形成第1絕緣膜；(c)於上述(b)步驟後，形成將上述第1區域開口，且覆蓋上述第2區域之第1掩膜圖案；(d)於上述(c)步驟後，於上述第1掩膜圖案存在之狀態下，藉由濺鍍法，使第1金屬膜堆積於上述第1絕緣膜上；(e)於上述(b)步驟後，形成將上述第2區域開口，且覆蓋上述第1區域之第2掩膜圖案；(f)於上述(e)步驟後，於上述第2掩膜圖案存在之狀態下，藉由濺鍍法，使第2金屬膜堆積於上述第1絕緣膜上；及(g)於上述(c)~(f)步驟後，藉由對上述第1金屬膜及上述第2金屬膜實 施熱處理，而於上述第1區域中使上述第1金屬膜與上述第1絕緣膜反應，並於上述第2區域中使上述第2金屬膜與上述第1絕緣膜反應；且上述第1金屬膜係Hf膜；上述第2金屬膜係Al膜。
  15. 如請求項14之半導體裝置之製造方法，其中上述第1導電型係p型；上述第2導電型係n型。
  16. 如請求項14之半導體裝置之製造方法，其進而包含如下步驟：於上述(b)步驟後且上述(c)~(f)步驟前，於包含氮之環境氛圍中，對上述第1絕緣膜之表面實施電漿處理。
  17. 如請求項14之半導體裝置之製造方法，其中上述(g)步驟係於上述第1金屬膜上及上述第2金屬膜上形成導電性膜之步驟；上述(g)步驟之上述熱處理係於上述導電性膜之形成時施加之熱處理。
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