TWI783011B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI783011B
TWI783011B TW107125133A TW107125133A TWI783011B TW I783011 B TWI783011 B TW I783011B TW 107125133 A TW107125133 A TW 107125133A TW 107125133 A TW107125133 A TW 107125133A TW I783011 B TWI783011 B TW I783011B
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郭建億
傅少甫
詹佳玲
白易芳
舒麗麗
呂惟皓
江威德
李啟弘
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例一般關於磊晶方式,其用以形成半導體裝置(如n型通道裝置)中的源極/汲極區。在一例中,半導體裝置的形成方法包括形成主動區於基板上。主動區包括源極/汲極區。源極/汲極區的形成步驟包括:沿著主動區中的凹陷之下表面與側表面形成阻障區。阻障區包括第一摻質濃度的砷。源極/汲極區的形成步驟亦包括形成磊晶材料於凹陷中的阻障區上。磊晶材料包括第二摻質濃度的磷。

Description

半導體裝置與其形成方法
本發明實施例關於用於半導體裝置(可為鰭狀場效電晶體裝置如n型的鰭狀場效電晶體裝置)中的源極/汲極區之磊晶方式。
半導體裝置用於多種電子應用中,比如個人電腦、手機、數位相機、或其他電子設備。隨著半導體產業進展至奈米技術製程節點以求更高的裝置密度、更高效能、更低能耗、與更低成本,製作與設計面臨的問題導致三維設計如鰭狀場效電晶體的發展。鰭狀場效電晶體裝置通常包含通道與源極/汲極區形成其中的半導體鰭狀物。閘極沿著鰭狀結構的側壁並形成於鰭狀結構上(如包覆鰭狀結構),具有增加通道表面積的優點,以產生更快、更可信、與更易控制的半導體裝置。然而,尺寸縮小也讓積體電路製程面臨新的挑戰。
本發明一實施例提供之半導體裝置的形成方法,包括:形成主動區於基板上,且主動區包括源極/汲極區,其中源極/汲極區的形成步驟包括:沿著主動區中的凹陷之下表面與側表面形成阻障區,且阻障區包括第一摻質濃度的砷;以 及形成磊晶材料於凹陷中的阻障區上,且磊晶材料包括第二摻質濃度的磷。
A-A、B-B:剖面
d:距離
m1、m2:斜率
70:半導體基板
74:鰭狀物
78:隔離區
80、101:界面介電層
82:虛置閘極
84:遮罩
86:閘極間隔物
90:凹陷
91:阻障區
92:磊晶源極/汲極區
96:接點蝕刻停止層
100:第一層間介電層
102:閘極介電層
103:順應層
104:閘極導電充填材料
120:導電結構
122:第二層間介電層
202、204、206、208、210:步驟
300:箭頭
400:圖表
402a:第一退火前輪廓
404a:第二退火前輪廓
402b:第一退火後輪廓
404b:第二退火後輪廓
第1A至1C、2A與2B、3A與3B、4A與4B、5A與5B、6A與6B、7A與7B、及8A與8B圖係一些實施例中,形成半導體裝置如鰭狀場效電晶體的例示性製程其製作階段中的個別中間結構之多種圖式。
第9圖係一些實施例中,用於形成半導體裝置的例示性步驟的流程圖。
第10圖係一些實施例中,第7A圖的中間結構其部份的細節剖視圖。
第11圖係一些實施例中,沿著第10圖中的參考方向之多種摻質輪廓的圖表。
本發明實施例提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本揭露之多種例子中可重複標號,但這些重複僅用以簡化與清楚說明,不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外,空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元 件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
本發明實施例關於用於半導體裝置(可為鰭狀場效電晶體裝置如n型的鰭狀場效電晶體裝置)中的源極/汲極區之磊晶方式。舉例來說,下述內容為電晶體的源極/汲極區與其形成方法。此處提供的技術與設備採用含砷的阻障區(如砷化矽或摻雜砷的矽)以形成源極/汲極區於半導體基板中,其可具有較低的汲極誘發能障降低,並改善電晶體電流。
用於形成源極/汲極區的技術例子將以鰭狀場效電晶體進行說明,然而本發明實施例範疇的磊晶方式亦可實施於平面電晶體及/或其他半導體裝置。此外,亦說明形成鰭狀場效電晶體的中間階段。此處所述的一些實施例採用置換閘極製程形成鰭狀場效電晶體。其他例子可採用閘極優先製程,如本技術領域中具有通常知識者所理解。下述內容說明例示性的方法與結構的一些變化。本技術領域中具有通常知識者應理解,其他調整屬於其他實施例的範疇。雖然以特定順序描述方法的實施例,但可採用任何邏輯性的順序進行多種其他方法的實施例,且其他方法的實施例可具有比此處所述的步驟更多或更少的步驟。
第1A至1C圖到第8A與8B圖係一些實施例中,形成鰭狀場效電晶體的例示性製程中的個別中間結構之圖式。第9圖係一些實施例中,例示性製程的例示性步驟之流程圖。
第1A與1B圖係中間結構的個別剖視圖,而第1C圖係中間結構的透視圖。第1C圖亦顯示用於剖面圖的剖面A-A與B-B。圖式末尾為「A」者沿著第1C圖中的剖面A-A,而圖式末尾為「B」者沿著第1C圖中的剖面B-B。
第1A至1C圖的中間結構包含多個鰭狀物74形成於半導體基板70上,而個別的隔離區78形成於相鄰的鰭狀物74之間的半導體基板70上。多個虛置閘極堆疊沿著鰭狀物74的個別側壁並形成於鰭狀物74上。多個虛置閘極堆疊各自包含界面介電層80、虛置閘極82、與遮罩84。
半導體基板70可為或包含基體半導體基板、絕緣層上半導體基板、或類似物,其可摻雜(比如摻雜p型或n型摻質)或未摻雜。在一些實施例中,半導體基板70的半導體材料可包含半導體元素如矽或鍺、半導體化合物、半導體合金、或上述之組合。
鰭狀物74形成於半導體基板70中。舉例來說,可蝕刻半導體基板70,使溝槽形成於相鄰的一對鰭狀物74之間,因此鰭狀物74自半導體基板70凸起。上述結構的形成方法可採用合適的光微影與蝕刻製程。隔離區78各自形成於對應的溝槽中。隔離區78可包含或可為絕緣材料如氧化物(比如氧化矽)、氮化物、類似物、或上述之組合,且絕緣材料的沉積方法可採用合適的沉積製程。在沉積絕緣材料以形成隔離區78之後,可使絕緣材料凹陷。絕緣材料凹陷後,鰭狀物可自相鄰的隔離區78之間凸起,因此其可定義(至少部份的)鰭狀物74為半導體基板70上的主動區。本技術領域中具有通常知識者應理解,上述 製程僅用以舉例說明如何形成鰭狀物74。在其他例子中,鰭狀物74可由其他製程形成,且可包含異質磊晶結構及/或同質磊晶結構。
虛置閘極堆疊形成於鰭狀物74上。在此處所述的置換閘極製程中,可由合適製程依序形成用於虛置閘極堆疊的界面介電層80、虛置閘極82、與遮罩84之個別層狀物。接著以合適的光微影與蝕刻製程將這些層狀物圖案化成虛置閘極堆疊。舉例來說,界面介電層80可包含或可為氧化矽、氮化矽、類似物、或上述之多層。虛置閘極82可包含或可為矽(如多晶矽)或另一材料。遮罩84可包含或可為氮化矽、氮氧化矽、氮碳化矽、類似物、或上述之組合。
第1C圖中的剖面A-A沿著相對的源極/汲極區之間的一鰭狀物74中的通道。第1C圖中的剖面B-B垂直於剖面A-A,並橫越相鄰的鰭狀物74中的個別源極/汲極區。
如第2A與2B圖所示,形成閘極間隔物86。沿著虛置閘極堆疊的側壁(如界面介電層80、虛置閘極82、與遮罩84的側壁),形成閘極間隔物86。舉例來說,閘極間隔物86的形成方法可為順應性地沉積用於閘極間隔物86的一或多個層狀物,並非等向地蝕刻一或多個層狀物。用於閘極間隔物86的一或多個層狀物可包含或可為氮化矽、氮氧化矽、碳氮化矽、類似物、上述之多層、或上述之組合。
如第3A與3B圖所示,形成凹陷90於鰭狀物74中,以用於靠近虛置閘極堆疊的源極/汲極區,如第9圖的步驟202所述。如圖所示,凹陷90形成於鰭狀物74中,且位於虛置閘極 堆疊的兩側上。凹陷方法可為蝕刻製程。蝕刻製程可為等向或非等向,且可進一步對半導體基板70的一或多個結晶平面具有選擇性。因此凹陷90可具有多種剖面輪廓,端視實施的蝕刻製程而定。蝕刻製程可為乾蝕刻(如反應性離子蝕刻、中性束蝕刻、或類似方法);或濕蝕刻(如採用氫氧化四甲基銨、氫氧化銨、或另一蝕刻劑的蝕刻方法)。
如第4A與4B圖所示,沿著凹陷90定義之鰭狀物74的表面,形成阻障區91,如第9圖的步驟204所述。在一些例子中,阻障區91的形成方法為磊晶成長含阻障物種的材料於凹陷90的表面上,如第9圖的步驟206所述。在其他例子中,阻障區91的形成方法為沿著凹陷90的表面摻雜阻障物種,使阻障物種穿過凹陷90的表面以摻雜鰭狀物74,如第9圖的步驟208所述。如下詳述,阻障區91可避免導電摻質物種自形成於個別阻障區91上的源極/汲極區向外擴散。一般而言,阻障區91包含阻障物種,其可避免向外擴散。在此處所述的一些例子中,阻障物種包含砷,不過亦可採用其他元素或材料。
在一些例子中,阻障區91的形成方法為磊晶成長阻障區91於凹陷90中。在一些例子中,阻障區91可磊晶成長於凹陷90的下表面與側表面上。在這些例子中,阻障區91可包含半導體材料與阻障物種。阻障區91的磊晶成長方法可為遠端電漿增強化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、分子束磊晶、液相磊晶、氣相磊晶、類似方法、或上述之組合。在一些例子中,阻障物種為砷,而阻障區91可為磊晶成長的砷化矽層。為形成砷化矽層,可實施遠端電漿增強化學 氣相沉積製程。遠端電漿增強化學氣相沉積的矽源前驅物氣體可包含矽烷、二矽烷、三矽烷、二氯矽烷、三氯矽烷、另一含矽前驅物、及/或任何上述組合。遠端電漿增強化學氣相沉積的砷源前驅物氣體可包含砷化氫、另一含砷前驅物、及/或任何上述組合。其他氣體如載氣(比如氮氣、氫氣、或類似氣體)可與前驅物混合。矽源前驅物的流速可介於約500sccm至約1000sccm之間,而砷源前驅物的流速可介於約50sccm至約300sccm之間。遠端電漿增強化學氣相沉積的壓力可介於約50Torr至約500Torr之間。遠端電漿增強化學氣相沉積的溫度可介於約600℃至約800℃之間。在一些例子中,這些參數可依製程變化。遠端電漿增強化學氣相沉積製程可為循環的沉積-蝕刻製程,如本技術領域中具有通常知識者所理解。此外,本技術領域中具有通常知識者應理解可實施不同製程以達磊晶成長砷化矽的阻障區91,或含有不同阻障物種的另一材料。
在另一例中,阻障區91的形成方法可為經由凹陷90的表面。將阻障物種摻雜至鰭狀物74。阻障區91的形成方法可為經由凹陷90的表面,電漿摻雜及/或佈植阻障物種。在一些例子中,阻障物種為砷,而阻障區91可為鰭狀物74中摻雜砷的矽區(當鰭狀物74為矽時),其形成方法可為電漿摻雜砷至凹陷90。本技術領域中具有通常知識者應理解,可採用不同製程以達摻雜砷的矽之阻障區91,或含有不同阻障物種的另一材料。
在一些實施例中,阻障區91的厚度小於或等於約20nm,比如小於或等於約5nm。阻障層91在凹陷90的表面上的 厚度可一致或不一致。當阻障區91的形成方法為磊晶成長時,可經由磊晶成長的阻障區91量測阻障層91自個別凹陷90的表面的厚度;及/或當阻障區91的形成方法為摻雜鰭狀物74時,可經由電漿摻雜的阻障區91量測阻障層91自個別凹陷90的表面至鰭狀物74中的厚度。
阻障區91可具有阻障物種的多種濃度。當阻障物種為砷時,阻障區91中的砷濃度可大於或等於約1018cm-3,比如介於約1×1020cm-3至約2×1021cm-3之間。阻障區91的額外細節將說明如下,特別是阻障物種為砷的內容。
如第5A與5B圖所示,形成磊晶源極/汲極區92於阻障區91上及凹陷中,如第9圖的步驟210所述。雖然阻障區91與對應的源極/汲極區92描述為分開的構件,但兩者可一起作為源極/汲極區。一般而言,磊晶源極/汲極區92包含的半導體材料含有導電摻質物種。具有阻障物種的阻障區91可減少或避免磊晶源極/汲極區92的導電摻質物種向外擴散至鰭狀物74中,比如向外擴散至鰭狀物74中的通道區。
磊晶源極/汲極區92的形成方法,可為磊晶成長磊晶源極/汲極區92於阻障區91上與凹陷90中。磊晶源極/汲極區92可摻雜導電摻質物種(如n型摻質),且摻雜方法可為磊晶成長時的原位摻雜及/或磊晶成長後的佈植。在一些例子中,磊晶源極/汲極區92可包含磷化矽、碳磷化矽、或類似物,其中磊晶源極/汲極區92可原位摻雜導電摻質物種(如磷)。在其他例子中,磊晶源極/汲極區92可包含矽、碳化矽、II-VI族半導體化合物、III-V族半導體化合物、或類似物,且接著可將導電摻質 物種(如磷)佈植至磊晶源極/汲極區92。磊晶成長可為遠端電漿增強化學氣相沉積、低壓化學氣相沉積、有機今屬化學氣相沉積、分子束磊晶、液相磊晶、氣相磊晶、類似方法、或上述之組合。
在導電摻質物種為磷且磊晶源極/汲極區92為磷化矽的一些例子中,磊晶源極/汲極區92可為磊晶成長的磷化矽。為形成化矽區,可實施遠端電漿增強化學氣相沉積製程。遠端電漿增強化學氣相沉積的矽源前驅物可包含矽烷、二矽烷、三矽烷、二氯矽烷、三氯矽烷、另一含矽前驅物、及/或任何上述組合,而遠端電漿增強化學氣相沉積製程的磷源前驅物可包含磷化氫、另一含磷前驅物、及/或任何上述組合。其他氣體如載氣(比如氮氣、氫氣、或類似氣體)可與前驅物混合。矽源前驅物的流速可介於約600sccm至約900sccm之間,而磷源前驅物的流速可介於約150sccm至約300sccm之間。遠端電漿增強化學氣相沉積的壓力可介於約50Torr至約300Torr之間。遠端電漿增強化學氣相沉積的溫度可介於約600℃至約750℃之間。在一些例子中,這些參數可依製程變化。遠端電漿增強化學氣相沉積製程可為循環的沉積-蝕刻製程,如本技術領域中具有通常知識者所理解。此外,本技術領域中具有通常知識者應理解可實施不同製程以達磊晶成長磷化矽的源極/汲極區92,或含有不同導電摻質物種的另一材料。
在一些例子中,由於隔離區78的阻擋,磊晶源極/汲極區92的磊晶成長材料可先垂直地成長於凹陷90中,此時磊晶源極/汲極區92的磊晶成長材料不會水平地成長。在磊晶成 長材料填滿凹陷90之後,磊晶成長材料可垂直地與水平地成長以形成晶面,其可對應半導體基板70的結晶平面。
磊晶源極/汲極區92可具有導電摻質物種的多種濃度。當導電摻質物種為磷(比如來自磊晶成長時的磷及/或佈植磷),磊晶源極/汲極區92中的磷濃度可介於約1019cm-3至約5×1021cm-3之間,比如介於約2×1021cm-3至約5×1021cm-3之間。磊晶源極/汲極區92的額外細節將說明如下,特別是導電摻質物種為磷的內容。
如第6A與6B圖所示,形成接點蝕刻停止層96與第一層間介電層100。一般而言,蝕刻停止層在形成接點或通孔時,可提供停止蝕刻製程的機制。蝕刻停止層的組成可為介電材料,其蝕刻選擇性不同於相鄰的層狀物(如第一層間介電層100)。接點蝕刻停止層96順應性地沉積於磊晶源極/汲極區92、虛置閘極堆疊、閘極間隔物86、與隔離區78上,而第一層間介電層100沉積於接點蝕刻停止層96上。蝕刻停止層可包含或可為氮化矽、碳氮化矽、碳氧化矽、氮化碳、類似物、或上述之組合。第一層間介電層100可包含或可為氧化矽、低介電常數的介電材料(介電常數低於氧化矽的介電常數之材料)、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、旋轉塗佈聚合物、碳矽材料、上述之化合物、上述之複合物、類似物、或上述之組合。接點蝕刻停止層96與第一層間介電層100的沉積方法可為任何合適的沉積技術。
如第7A與7B圖所示,將虛置閘極堆疊取代為置換閘極結構。進行平坦化製程如化學機械研磨,使接點蝕刻停止層96與第一層間介電層100的上表面齊平於虛置閘極82的上表面。化學機械研磨亦可移除虛置閘極82上的遮罩。在一些實施例中,化學機械研磨亦移除虛置閘極82上的閘極間隔物86的上側部份。綜上所述,經由接點蝕刻停止層96與第一層間介電層100露出虛置閘極82的上表面。接著移除虛置閘極82與界面介電層80以露出鰭狀物74中的個別通道區,且移除方法可為一或多道蝕刻製程。
接著可沉積用於形成置換閘極結構的層狀物於移除虛置閘極堆疊處,比如順應性地沉積一些層狀物、並以平坦化製程如化學機械研磨移除這些層狀物的多餘部份,即形成置換閘極結構。置換閘極結構各自包含界面介電層101、閘極介電層102、一或多個視情況形成的順應層103、與閘極導電充填材料104,如第7A圖所示。
沿著通道區形成界面介電層101於鰭狀物74的側壁與上表面上,即移除虛置閘極堆疊處。舉例來說,界面介電層101可為界面介電層80(若未被移除)、氧化物(如氧化矽)、氮化物(如氮化矽)、及/或另一介電層。閘極介電層102順應性地沉積於界面介電層101上,沿著閘極間隔物86的側壁,並沉積於接點蝕刻停止層96與第一層間介電層100的上表面上。閘極介電層102可為或包括氧化矽、氮化矽、高介電常數的介電材料、上述之多層、或其他介電材料。高介電常數的介電材料其介電常數可大於約7.0,且可包含鉿、鋁、鋯、鑭、鎂、鋇 、鈦、或鉛的金屬氧化物或金屬矽酸鹽,上述之多層,或上述之組合。
接著可順應性(及依序,若層狀物數目超過一)地沉積一或多個視情況形成的順應層103於閘極介電層102上。一或多個視情況形成的順應層103可包含一或多個阻障及/或蓋層,以及一或多個功函數調整層。一或多個阻障及/或蓋層可包含鉭及/或鈦的氮化物、氮矽化物、碳氮化物、及/或鋁氮化物;鎢的氮化物、碳氮化物、及/或碳化物;類似物;或上述之組合。一或多個功函數調整層可包含或可為鈦及/或鉭的氮化物、氮矽化物、碳矽化物、鋁氮化物、鋁氧化物、及/或鋁碳化物;鎢、鈷、或鉑的氮化物、碳氮化物、及/或碳化物;類似物;或上述之組合。
閘極導電充填材料104形成於閘極介電層102及/或一或多個視情況形成的順應層103(若存在)上。閘極導電充填材料104可填入移除虛置閘極堆疊後的剩餘區域。閘極導電充填材料104可為或包括含金屬的材料,比如鎢、鈷、釕、鋁、上述之多層、或上述之組合。
如第8A與8B圖所示,形成第二層間介電層122,與到磊晶源極/汲極區92的導電結構120。第二層間介電層122沉積(比如由合適的沉積製程)於第一層間介電層100、置換閘極結構、與接點蝕刻停止層96的上表面上。第二層間介電層122可包含或可為氧化矽、低介電常數的介電材料、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗 佈玻璃、旋轉塗佈聚合物、碳矽材料、上述之化合物、上述之複合物、類似物、或上述之組合。接著形成開口穿過第二層間介電層122、第一層間介電層100、與接點蝕刻停止層96,以露出個別的磊晶源極/汲極區92,且開口的形成方法可採用合適的光微影與蝕刻製程。
接著形成導電結構120於開口中,以至磊晶源極/汲極區92。導電結構120可包含順應性的黏著及/或阻障層,其沿著開口側壁(如第一層間介電層100與第二層間介電層122的側壁)。導電結構120亦可包含導電的充填材料於黏著及/或阻障層上,以填入開口。舉例來說,黏著及/或阻障層可為或包含鈦、鈷、鎳、氮化鈦、氧化鈦、氮化鉭、氧化鉭、類似物、或上述之組合。導電充填材料可為或包含鎢、銅、鋁、金、銀、上述之合金、或類似物。矽化物區亦可形成於磊晶源極/汲極區92的上側部份上。矽化物區的形成方法可為磊晶源極/汲極區92的上側部份與黏著及/或阻障層之間的反應。可進行退火以利磊晶源極/汲極區92與黏著及/或阻障層之間的反應。在沉積用於導電結構120的導電充填材料之後,可採用平坦化製程如化學機械研磨以移除多餘材料,使導電結構120的上表面與第二層間介電層122的上表面共平面。導電結構120可稱作接點、插塞、或類似物。
第10圖係本發明實施例中,第7A圖的中間結構其部份的細節剖視圖。雖然可實施不同材料及/或物種,此例中的鰭狀物74為矽,而阻障區91為摻雜砷的矽區或磊晶的砷化矽層,且磊晶源極/汲極區92為原位摻雜的磷化矽區。如圖所示 ,阻障區91最靠近置換閘極結構的表面,與置換閘極結構的側壁平面之間具有距離d。在一些例子中,距離d小於或等於約10nm,比如介於3nm至10nm之間。第10圖所示的箭頭300自磊晶源極/汲極區92穿過阻障區91至鰭狀物74中。箭頭300為用於第11圖的參考位置。箭頭亦可為穿過相同區域及/或材料的不同位置。
第11圖係本發明實施例中,沿著第10圖中的箭頭之多種摻質輪廓的圖表400。圖表400係沿著箭頭300的摻質其濃度對位置的函數。圖表400顯示磷的第一退火前輪廓402a,砷的第二退火前輪廓404a,磷的第一退火後輪廓402b、以及砷的第二退火後輪廓404b。第一退火前輪廓402a與第二退火前輪廓404a可為剛剛磊晶成長磊晶源極/汲極區92之後的個別輪廓。第一退火後輪廓402b與第二退火後輪廓404b所指的退火可為磊晶成長磊晶源極/汲極區92之後的任何退火,比如形成矽化物區於磊晶源極/汲極區92上的退火。
在形成積體電路時的大多數製程溫度下,砷通常比磷更難溶於矽中。舉例來說,矽中的砷摻雜濃度為約1021cm-3時,其於約800℃下的擴散性為約8×10-16cm2/s。當矽中的磷摻雜濃度為約1021cm-3時,其於約800℃下的擴散性為約6×10-14cm2/s。砷的尺寸與原子量(約1.19Å與約74.9amu)比磷的尺寸與原子量(約1Å與約31amu)大,據信為砷在矽中的溶解度與擴散性較低的原因。此外,據信砷的這些特性可讓砷得以降低或避免磷向外擴散至矽中。
在第11圖的圖表400中,第二退火前輪廓404a與第 二退火後輪廓404b之間,自阻障區91與鰭狀物74之間的界面至鰭狀物74中的砷濃度減少程度實質上未改變。砷濃度減少程度實質上未改變的原因,可能是砷在矽中的低擴散度與低溶解度如前述。第二退火前輪廓404a與第二退火後輪廓404b中的砷濃度降低,其斜率m1可介於約0.1decades/nm至約0.3decades/nm之間。第二退火前輪廓404a與第二退火後輪廓404b亦顯示一些砷自阻障區91與磊晶源極/汲極區92的界面,擴散至磊晶源極/汲極區92。將磷摻入磊晶源極/汲極區92中,可讓更多砷擴散至源極/汲極區92中。
第一退火前輪廓402a與第一退火後輪廓402b顯示一些磷擴散至穿過阻障區91至鰭狀物74中。然而退火後(比如第一退火後輪廓402b與第二退火後輪廓404b)的鰭狀物74中任何位置的磷濃度,均比阻障區91與源極/汲極區92的界面處之磷濃度小30倍以上,並小於鰭狀物74之對應位置中的砷濃度。此外,第一退火後輪廓402b中自阻障區91與鰭狀物74之間的界面至鰭狀物74中的磷濃度下降程度,大於第二退火後輪廓404b中自阻障區91與鰭狀物74之間的界面至鰭狀物74中的砷濃度下降程度。第一退火後輪廓402b中減少的斜率m2可介於約0.1decades/nm至約0.3decades/nm之間。斜率m2大於斜率m1,如上所述。
發明人觀察到當阻障區91的砷濃度大於或等於約1018cm-3時,砷可阻擋磷擴散至矽中(即砷的瞬時濃度大於磷的對應濃度)。因此一些例子中的阻障區91其砷濃度大於或等於約1018cm-3,比如介於約1×1020cm-3至約2×1021cm-3之間。
此外,由於鰭狀物74中的第二退火前輪廓404a與第二退火後輪廓404b實質上維持未變化,自初始形成的阻障區91至後續製程中,阻障區91可實質上維持相同的濃度輪廓擴散於鰭狀物74中。同樣如上所述,此砷濃度輪廓可阻擋鰭狀物74中的磷擴散。這些實施例可讓源極/汲極區(比如包含阻障區91與磊晶源極/汲極區92)的位置更精確。假設形成阻障區91時具有較精確的控制,其可達摻質輪廓中的劇烈下降(比如斜率m1與m2較大),以形成更靠近通道的源極/汲極區。因此可減少第10圖中的距離d。
此外,可阻擋導電摻質物種如磷擴散至鰭狀物74中的通道區。這可減少汲極誘發能障降低及其他問題的風險。源極/汲極區亦可摻雜更高濃度的導電摻質物種,以降低通道電阻、降低寄生電阻、及/或改善電流,即改良裝置效能。
在一實施例中,提供半導體裝置的形成方法。形成主動區於基板上。主動區包括源極/汲極區。源極/汲極區的形成步驟包括:沿著主動區中的凹陷之下表面與側表面形成阻障區。阻障區包括第一摻質濃度的砷。形成磊晶材料於凹陷中的阻障區上。磊晶材料包括第二摻質濃度的磷。
在一實施例中,上述方法形成阻障區的步驟包括磊晶成長阻障區,且在磊晶成長阻障區時原位摻雜砷。
在一實施例中,上述方法形成阻障區的步驟包括經由凹陷的下表面與側表面,電漿摻雜砷至主動區。
在一實施例中,上述方法形成阻障區的方法包括採用化學氣相沉積製程磊晶成長阻障區,且阻障區為砷化矽層 。
在一實施例中,上述方法的主動區包括鰭狀物,且電晶體為n型通道的鰭狀場效電晶體。
在一實施例中,上述方法的第一摻質濃度介於約1×1020cm-3至約2×1021cm-3之間。
在一實施例中,上述方法的阻障區厚度介於約1nm至約20nm之間。
在一實施例中,上述方法包括形成閘極結構於主動區上,最橫向靠近源極/汲極區的閘極結構的側壁定義平面,且磊晶材料的表面與平面之間的距離小於10nm。
在另一實施例中,提供結構。結構一般包含電晶體的主動區。主動區包括源極/汲極區。源極/汲極區包括:阻障區,其沿著源極/汲極區的下表面與側表面。阻障區含第一摻質濃度的砷。源極/汲極區亦包含磊晶材料於阻障區上。磊晶材料包括第二摻質濃度的磷。結構亦包含閘極結構於靠近源極/汲極區的主動區上。
在一實施例中,上述結構的主動區包括鰭狀物,且電晶體為n型通道的鰭狀場效電晶體。
在一實施例中,上述結構的第一摻質濃度介於約1×1020cm-3至約2×1021cm-3之間。
在一實施例中,上述結構的阻障區厚度介於約1nm至約20nm之間。
在一實施例中,上述結構中最橫向靠近源極/汲極區的閘極結構的側壁定義平面,且磊晶材料的表面與平面之間 的距離小於10nm。
在另一實施例中,提供另一方法。方法包括在靠近閘極結構的鰭狀物中蝕刻凹陷。閘極結構位於基板上的鰭狀物上。方法包括沿著凹陷的下表面與側表面形成阻障區。阻障區包括砷。方法包括磊晶成長磊晶材料於阻障區上。磊晶材料包括磷。
在一實施例中,上述方法形成阻障區的步驟包括磊晶成長阻障區於凹陷中。
在一實施例中,上述方法磊晶成長阻障區的步驟包括進行化學氣相沉積製程,以成長砷化矽磊晶層以作為阻障區。
在一實施例中,上述方法形成阻障區的步驟包括經由凹陷的下表面與側表面,摻雜砷至主動區。
在一實施例中,上述方法形成阻障區的步驟包括經由凹陷的下表面與側表面,電漿摻雜砷至主動區。
在一實施例中,上述方法的阻障區中的砷濃度介於約1×1020cm-3至約2×1021cm-3之間。
在一實施例中,上述方法的阻障區厚度介於1nm至20nm之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與 範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
d:距離
70:半導體基板
74:鰭狀物
86:閘極間隔物
91:阻障區
92:磊晶源極/汲極區
96:接點蝕刻停止層
100:第一層間介電層
101:界面介電層
102:閘極介電層
103:順應層
104:閘極導電充填材料
300:箭頭

Claims (11)

  1. 一種半導體裝置的形成方法,包括:形成一主動區於一基板上,且該主動區包括一源極/汲極區,其中該源極/汲極區的形成步驟包括:沿著該主動區中的一凹陷之下表面與側表面形成一阻障區,且該阻障區包括一第一摻質濃度的砷;以及形成一磊晶材料於該凹陷中的該阻障區上,且該磊晶材料包括一第二摻質濃度的磷。
  2. 如請求項1所述之半導體裝置的形成方法,其中形成該阻障區的步驟包括磊晶成長一阻障區,且在磊晶成長該阻障區時原位摻雜砷。
  3. 一種半導體裝置的形成方法,包括:在靠近一閘極結構的一鰭狀物中蝕刻一凹陷,且該閘極結構位於一基板上的該鰭狀物上;沿著該凹陷的下表面與側表面形成一阻障區,且該阻障區包括砷;以及在該阻障區上磊晶成長一磊晶材料,且該磊晶材料包括磷。
  4. 如請求項3所述的半導體裝置的形成方法,其中形成該阻障區的步驟包括在該凹陷中磊晶成長該阻障區。
  5. 一種半導體裝置的形成方法,包括:形成一第一閘極結構於一第一半導體鰭狀物上;形成一第一凹陷與一第二凹陷於該第一閘極結構的兩側上的該第一半導體鰭狀物中; 沿著該第一凹陷與該第二凹陷的下表面與側壁形成一阻障區,且該阻障區包括砷;以及磊晶成長一磊晶材料於該阻障區上,且該磊晶材料包括一n型摻質。
  6. 如請求項5所述的半導體裝置的形成方法,其中該n型摻質包括磷。
  7. 一種半導體裝置,包括:一電晶體的一主動區,該主動區包括一源極/漏極區,且該源極/漏極區包括:一阻障區,沿著該源極/漏極區的下表面與側表面,且該阻障區包含一第一摻質濃度的砷;以及一磊晶材料,位於該阻障區上,且該磊晶材料包括一第二摻質濃度的磷;以及一閘極結構,位於靠近該源極/漏極區的該主動區上。
  8. 如請求項7所述的半導體裝置,其中該主動區包括鰭狀物,且該電晶體為n型通道的鰭狀場效電晶體。
  9. 一種半導體裝置,包括:一半導體鰭狀物;一第一閘極結構,延伸於該半導體鰭狀物的上表面與側壁上;一源極/汲極磊晶區,與該第一閘極結構相鄰,且該源極/汲極磊晶區包括導電摻質;以及一阻障區,夾設於該源極/汲極磊晶區與該半導體鰭狀物之間,該阻障區包括一阻障物種摻質,且該阻障物種摻質與 該導電摻質不同,且該阻障物種摻質使擴散至該半導體鰭狀物中的該導電摻質減少,其中該導電摻質為n型摻質,且該阻障物種摻質為砷。
  10. 一種半導體裝置,包括:一半導體鰭狀物;一閘極結構,延伸於該半導體鰭狀物的上表面與側壁上;一源極/汲極磊晶區,與該閘極結構相鄰,該源極/汲極磊晶區包括一導電摻質的第一摻質輪廓,以及一阻障物種摻質的第一摻質輪廓;以及一阻障區,夾設於該源極/汲極磊晶區與該半導體鰭狀物之間,該阻障區包括該導電摻質的第二摻質輪廓,以及該阻障物種摻質的第二摻質輪廓,其中該阻障物種的第一摻質輪廓的峰值,小於該阻障物種摻質的第二摻質輪廓的峰值。
  11. 如請求項10所述的半導體裝置,其中該導電摻質的第二摻質輪廓自該阻障區的上表面,隨著由該源極/汲極磊晶區朝該半導體鰭狀物的方向持續減少。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220320294A1 (en) * 2019-08-01 2022-10-06 Applied Materials, Inc. Arsenic diffusion profile engineering for transistors
US11264508B2 (en) * 2020-01-24 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage prevention structure and method
US11532750B2 (en) * 2020-02-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11955482B2 (en) * 2020-05-18 2024-04-09 Intel Corporation Source or drain structures with high phosphorous dopant concentration
US12068395B2 (en) * 2021-04-14 2024-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an undoped region under a source/drain

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201331994A (zh) * 2012-01-31 2013-08-01 United Microelectronics Corp 半導體結構及其製程
US20150214223A1 (en) * 2012-06-11 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation of source and drain regions
US20170194321A1 (en) * 2016-01-04 2017-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with epitaxial source/drain
TW201731110A (zh) * 2016-02-25 2017-09-01 台灣積體電路製造股份有限公司 鰭式場效電晶體
US20170301786A1 (en) * 2016-04-13 2017-10-19 International Business Machines Corporation Self aligned epitaxial based punch through control

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372583B1 (en) * 2000-02-09 2002-04-16 Intel Corporation Process for making semiconductor device with epitaxially grown source and drain
US7288828B2 (en) * 2005-10-05 2007-10-30 United Microelectronics Corp. Metal oxide semiconductor transistor device
CN101071774B (zh) * 2006-05-12 2010-12-08 联华电子股份有限公司 金属氧化物半导体场效应晶体管及其制造方法
US20100012988A1 (en) * 2008-07-21 2010-01-21 Advanced Micro Devices, Inc. Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
KR20120062367A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 반도체 소자의 제조방법
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9418897B1 (en) 2015-06-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap around silicide for FinFETs
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9812363B1 (en) 2016-11-29 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US9923081B1 (en) * 2017-04-04 2018-03-20 Applied Materials, Inc. Selective process for source and drain formation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201331994A (zh) * 2012-01-31 2013-08-01 United Microelectronics Corp 半導體結構及其製程
US20150214223A1 (en) * 2012-06-11 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation of source and drain regions
US20170194321A1 (en) * 2016-01-04 2017-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with epitaxial source/drain
TW201731110A (zh) * 2016-02-25 2017-09-01 台灣積體電路製造股份有限公司 鰭式場效電晶體
US20170301786A1 (en) * 2016-04-13 2017-10-19 International Business Machines Corporation Self aligned epitaxial based punch through control

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